K4D64163HE-TC60 [SAMSUNG]

DDR DRAM, 4MX16, 0.75ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66;


型号：	K4D64163HE-TC60
厂家：	SAMSUNG
描述：	DDR DRAM, 4MX16, 0.75ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 动态存储器双倍数据速率光电二极管内存集成电路
文件：	总16页 (文件大小：233K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Target

64M DDR SDRAM

K4D64163HE

64Mbit DDR SDRAM

1M x 16Bit x 4 Banks

Double Data Rate Synchronous RAM

Revision 0.2

October 2001

Samsung Electronics reserves the right to change products or specification without notice.

- 1 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

Revision History

Revision 0.2 (October 25, 2001) - Target Spec

• Removed K4D64163HE-TC33/36 from the spec.

Revision 0.1 (October 13, 2001) - Target Spec

• Changed VDD from 3.3V + 10% to 3.3V + 5%

Revision 0.0 (October 12, 2001) - Target Spec

• Defined Target Specification

- 2 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

1M x 16Bit x 4 Banks Double Data Rate Synchronous RAM

with Bi-directional Data Strobe and DLL

FEATURES

• 3.3V + 5% power supply for device operation

• 2.5V + 5% power supply for I/O interface

• SSTL_2 compatible inputs/outputs

• 4 banks operation

• 2 DQSs’ ( 1DQS / Byte )

• Data I/O transactions on both edges of Data strobe

• DLL aligns DQ and DQS transitions with Clock transition

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

• DM for write masking only

• MRS cycle with address key programs

-. Read latency 3 (clock)

-. Burst length (2, 4, 8 and Full page)

-. Burst type (sequential & interleave)

• Full page burst length for sequential burst type only

• Start address of the full page burst should be even

• All inputs except data & DM are sampled at the positive

going edge of the system clock

• Auto & Self refresh

• 64ms refresh period (4K cycle)

• 66pin TSOP-II

• Maximum clock frequency up to 250MHz

• Maximum data rate up to 500Mbps/pin

• Differential clock input

• No Wrtie-Interrupted by Read Function

ORDERING INFORMATION

Part NO.

Max Freq.

250MHz

222MHz

200MHz

183MHz

166MHz

Max Data Rate

500Mbps/pin

444Mbps/pin

400Mbps/pin

366Mbps/pin

333Mbps/pin

Interface

Package

K4D64163HE-TC40

K4D64163HE-TC45

K4D64163HE-TC50

K4D64163HE-TC55

K4D64163HE-TC60

SSTL_2

66 pin TSOP-II

GENERAL DESCRIPTION

FOR 1M x 16Bit x 4 Bank DDR SDRAM

The K4D64163H is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,976 words by 16

bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to 1.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of

operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of

high performance memory system applications.

- 3 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

PIN CONFIGURATION (Top View)

VSS

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

66 PIN TSOP(II)

(400mil x 875mil)

(0.65 mm Pin Pitch)

VSSQ

UDQS

VDDQ

LDQS

VREF

VSS

VDD

UDM

LDM

CAS

RAS

CKE

A11

BA0

BA1

AP/A10

VSS

VDD

PIN DESCRIPTION

CK,CK

CKE

Differential Clock Input

Clock Enable

BA0, BA1

A0 ~A11

DQ0 ~ DQ15

VDD

Bank Select Address

Address Input

Data Input/Output

Power

Chip Select

RAS

Row Address Strobe

Column Address Strobe

Write Enable

CAS

VSS

Ground

VDDQ

Power for DQ’s

Ground for DQ’s

No Connection

LDQS,UDQS

LDM,UDM

Data Strobe

VSSQ

Data Mask

- 4 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

Symbol

Type

Function

The differential system clock Input.

CK, CK*1

Input

All of the inputs are sampled on the rising edge of the clock except

DQ’s and DM’s that are sampled on both edges of the DQS.

Activates the CK signal when high and deactivates the CK signal

when low. By deactivating the clock, CKE low indicates the Power

down mode or Self refresh mode.

CKE

CS enables the command decoder when low and disabled the com-

mand decoder when high. When the command decoder is disabled,

new commands are ignored but previous operations continue.

Latches row addresses on the positive going edge of the CK with

RAS low. Enables row access & precharge.

RAS

CAS

Input

Latches column addresses on the positive going edge of the CK with

CAS low. Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Data Strobe : Output with read data, input with write data. Edge-

aligned with read data, centered in write data. Used to capture write

data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ;

UDQS corresponds to the data on DQ8-DQ15.

LDQS,(U)DQS

LDM,UDM

Input/Output

Input Data Mask : DM is an input mask signal for write data. Input

data is masked when DM is sampled HIGH along with that input data

during a WRITE access. DM is sampled on both edges of DQS. DM

pins include dummy loading internally, to matches the DQ and DQS

loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ;

UDM correspons to the data on DQ8-DQ15.

Input

DQ0 ~ DQ15

BA0, BA1

Input/Output

Input

Data inputs/Outputs are multiplexed on the same pins.

Selects which bank is to be active.

Row/Column addresses are multiplexed on the same pins.

Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7.

A0 ~ A11

VDD/VSS

Input

Power Supply

Power and ground for the input buffers and core logic.

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

VDDQ/VSSQ

VREF

Reference voltage for inputs, used for SSTL interface.

NC/RFU

No connection/

This pin is recommended to be left "No connection" on the device

Reserved for future use

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply VREF to CK pin.

- 5 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

BLOCK DIAGRAM (1Mbit x 16I/O x 4 Bank)

Intput Buffer

LWE

LDMi

CK, CK

Data Input Register

Serial to parallel

Bank Select

1Mx16

x16

DQi

CK,CK

ADDR

Column Decoder

Latency & Burst Length

Data Strobe

Programming Register

LWCBR

DLL

LCKE

LRAS LCBR

LWE

LCAS

CK,CK

LDMi

Timing Register

UDM

CK,CK

CKE

RAS

CAS

LDM

- 6 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

FUNCTIONAL DESCRIPTION

• Power-Up Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)

- Apply VDD before VDDQ .

- Apply VDDQ before VREF & VTT

2. Start clock and maintain stable condition for minimum 200us.

3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .

4. Issue precharge command for all banks of the device.

5. Issue a EMRS command to enable DLL

6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

*1,2 7. Issue precharge command for all banks of the device.

8. Issue at least 2 or more auto-refresh commands.

9. Issue a mode register set command with A8 to low to initialize the mode register.

*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.

*2 Sequence of 6&7 is regardless of the order.

Power up & Initialization Sequence

12 13

16 17

CK,CK

tRP

2 Clock min.

tRFC

2 Clock min.

tRP

2 Clock min.

Command

precharge

ALL Banks

precharge

ALL Banks

2nd Auto

Refresh

MRS

DLL Reset

1st Auto

Refresh

Mode

Any

Command

EMRS

200 Clock min.

Inputs must be

stable for 200us

- 7 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

MODE REGISTER SET(MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,

addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for

variety of different applications. The default value of the mode register is not defined, therefore the mode register must be

written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and

WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of

address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.

Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents

can be changed using the same command and clock cycle requirements during operation as long as all banks are in the

idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,

addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is

used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes

for various burst length, addressing modes and CAS latencies.

Address Bus

BA1

BA0

A11

A10

Mode Register

RFU

DLL

CAS Latency

Burst Length

Burst Type

DLL

Test Mode

Type

DLL Reset

mode

Sequential

Interleave

Normal

Test

Yes

Burst Length

Burst Type

CAS Latency

Sequential Interleave

BA0

An ~ A0

MRS

A6 A5 A4 Latency

Reserve

Reserved

EMRS

* RFU(Reserved for future use)

should stay "0" during MRS

cycle.

Reserve

Full page

Reserve

Full page

Reserved

MRS Cycle

CK, CK

Precharge

All Banks

Any

Command

NOP

MRS

NOP

tMRD=2 tCK

tRP

*1 : MRS can be issued only at all banks precharge state.

*2 : Minimum tRP is required to issue MRS command.

- 8 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

EXTENDED MODE REGISTER SET(EMRS)

The extended mode register stores the data for enabling or disabling DLL and selecting output driver

strength. The default value of the extended mode register is not defined, therefore the extened mode register

must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-

ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE

already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11

and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1

and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are

required to complete the write operation in the extended mode register. The mode register contents can be

changed using the same command and clock cycle requirements during operation as long as all banks are in

the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address

pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific

codes.

Address Bus

BA1

BA0

A11

A10

Extended

Mode Register

RFU

D.I.C

RFU

D.I.C DLL

BA0

An ~ A0

MRS

DLL Enable

Enable

Output Driver Impedence Control

A6 A1

N/A

Weak

Do not use

60%

EMRS

Disable

N/A

Do not Use

30%

Matched Impedance

*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.

- 9 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD

Value

-0.5 ~ 3.6

-1.0 ~ 3.6

-0.5 ~ 3.6

-55 ~ +150

1.0

Unit

VDDQ

TSTG

°C

Power dissipation

Short circuit current

IOS

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)

Parameter

Device Supply voltage

Output Supply voltage

Reference voltage

Symbol

VDD

Min

3.135

Typ

Max

3.465

Unit

Note

3.3

VDDQ

VREF

Vtt

2.375

2.50

2.625

0.49*VDDQ

VREF-0.04

VREF+0.15

-0.30

0.51*VDDQ

VREF+0.04

VDDQ+0.30

VREF-0.15

Termination voltage

VREF

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Output leakage current

VIH(DC)

VIL(DC)

VOH

Vtt+0.76

IOH=-15.2mA

VOL

Vtt-0.76

IOL=+15.2mA

IIL

-5

IOL

-5

Note :

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to

peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error

and an additional + 25mV for AC noise.

3. Vtt of the transmitting device must track VREF of the receiving device.

4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.

- 10 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

DC CHARACTERISTICS

Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)

Version

Parameter

Symbol

Test Condition

Unit Note

-40

-45

-50

-55

-60

Burst Lenth=2 tRC ³ tRC(min)

IOL=0mA, tCC= tCC(min)

Operating Current

(One Bank Active)

ICC1

TBD

Precharge Standby Current

in Power-down mode

ICC2P

ICC2N

ICC3P

ICC3N

ICC4

TBD

CKE £ VIL(max), tCC= tCC(min)

CKE ³ VIH(min), CS ³ VIH(min),

tCC= tCC(min)

Precharge Standby Current

in Non Power-down mode

Active Standby Current

power-down mode

CKE £ VIL(max), tCC= tCC(min)

CKE ³ VIH(min), CS ³ VIH(min),

tCC= tCC(min)

Active Standby Current in

in Non Power-down mode

Operating Current

( Burst Mode)

tRC ³ tRFC(min)tRC ³ tRFC(min)

Page Burst, All Banks activated.

Refresh Current

ICC5

ICC6

TBD

tRC ³ tRFC(min)

CKE £ 0.2V

Self Refresh Current

Note : 1. Measured with outputs open.

2. Refresh period is 64ms.

AC INPUT OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to VSS=0V, VDD=3.3V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65°C)

Parameter

Symbol

VIH

Min

VREF+0.35

Typ

Max

Unit

Note

Input High (Logic 1) Voltage; DQ

Input Low (Logic 0) Voltage; DQ

VIL

VREF-0.35

VDDQ+0.6

0.5*VDDQ+0.2

Clock Input Differential Voltage; CK and CK

Clock Input Crossing Point Voltage; CK and CK

VID

0.7

VIX

0.5*VDDQ-0.2

Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same

- 11 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

AC OPERATING TEST CONDITIONS (VDD=3.3V±5%, TA= 0 to 65°C)

Parameter

Value

Unit

Note

Input reference voltage for CK(for single ended)

CK and CK signal maximum peak swing

CK signal minimum slew rate

0.50*VDDQ

1.5

1.0

VREF+0.35/VREF-0.35

VREF

V/ns

Input Levels(VIH/VIL)

Input timing measurement reference level

Output timing measurement reference level

Output load condition

Vtt

See Fig.1

Vtt=0.5*VDDQ

RT=50W

VREF

Output

Z0=50W

=0.5*VDDQ

CLOAD=30pF

(Fig. 1) Output Load Circuit

CAPACITANCE (VDD=3.3V, TA= 25°C, f=1MHz)

Parameter

Input capacitance( CK, CK )

Symbol

CIN1

Min

1.0

Max

5.0

Unit

Input capacitance(A0~A11, BA0~BA1)

CIN2

1.0

4.0

Input capacitance

( CKE, CS, RAS,CAS, WE )

CIN3

1.0

4.0

Data & DQS input/output capacitance(DQ0~DQ31)

Input capacitance(DM0 ~ DM3)

COUT

CIN4

1.0

6.5

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

CDC1

Value

Unit

Decoupling Capacitance between VDD and VSS

Decoupling Capacitance between VDDQ and VSSQ

0.1 + 0.01

CDC2

Note :

1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

- 12 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

AC CHARACTERISTICS

-40

-45

-50

-55

-60

Sym-

Parameter

bol

Unit Note

Min

4.0

0.45

-0.6

Max

Min

4.5

0.45

-0.7

Max

0.55

0.7

0.45

1.1

0.6

1.2

Min

5.0

0.45

-0.7

Max

0.55

0.7

0.45

1.1

0.6

1.2

Min

5.5

Max

Min

6.0

Max

CK cycle time

CL=3

tCK

CK high level width

CK low level width

0.55

0.6

0.4

1.1

0.6

1.15

0.45

0.55

0.75

0.5

1.1

0.6

1.25

0.45

-0.75

0.55 tCK

tCH

tCL

DQS out access time from CK

Output access time from CK

Data strobe edge to Dout edge

Read preamble

-0.75

0.75

0.5

tDQSCK

tAC

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPREH

tWPST

tDQSH

tDQSL

tIS

0.9

0.4

0.85

0.9

0.4

0.8

0.9

0.4

0.8

0.9

0.4

0.75

0.9

1.1

tCK

Read postamble

0.4

0.6

CK to valid DQS-in

0.75

1.25 tCK

DQS-In setup time

tCK

DQS-in hold time

0.35

0.4

0.9

0.4

0.3

0.4

1.0

0.45

0.3

0.4

1.0

0.45

0.25

0.4

1.1

0.5

0.25

0.4

DQS write postamble

0.6

DQS-In high level width

DQS-In low level width

Address and Control input setup

Address and Control input hold

DQ and DM setup time to DQS

DQ and DM hold time to DQS

0.4

1.1

tIH

0.5

tDS

0.5

tDH

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

Clock half period

tHP

tQH

tHP

0.4

tHP

0.45

tHP

0.45

tHP

0.5

tHP

0.5

Data output hold time from DQS

Note 1 :

- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data

strobe and all data associated with that data strobe are coincidentally valid.

- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst

case

output vaild window even then the clock duty cycle applied to the device is better than 45/55%

- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle

variation and replaces tDV

- tQHmin = tHP-X where

. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)

. X=A frequency dependent timing allowance account for tDQSQmax

- 13 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

AC CHARACTERISTICS (I)

-40

-45

-50

-55

-60

Unit Note

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Row cycle time

tCK

tRC

Refresh row cycle time

Row active time

tRFC

tRAS

tRCD

tRP

100K

RAS to CAS delay

Row precharge time

Row active to Row active

tRRD

Last data in to Row precharge

@Normal Precharge

Last data in to Row precharge

@Auto Precharge

tWR

tCK

tWR_A

Last data in to Read command

Col. address to Col. address

Mode register set cycle time

tCK

tCDLR

tCCD

tMRD

Auto precharge write recovery

+ Precharge

Exit self refresh to read com-

tCK

tDAL

tXSR

200

1tCK+

tIS

1tCK+

tIS

1tCK+

tIS

1tCK+

tIS

1tCK+

tIS

Power down exit time

Refresh interval time

tPDEX

tREF

15.6

Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM

AC CHARACTERISTICS (II)

(Unit : Number of Clock)

K4D64163HE-TC40

Unit

tCK

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCD

tRP

tRRD

tDAL

250MHz ( 4.0ns )

222MHz ( 4.5ns )

200MHz ( 5.0ns )

183MHz ( 5.5ns )

166MHz ( 6.0ns )

K4D64163HE-TC45

Frequency

222MHz ( 4.5ns )

200MHz ( 5.0ns )

183MHz ( 5.5ns )

166MHz ( 6.0ns )

Cas Latency

tRC

tRFC

tRAS

tRCD

tRP

tRRD

tDAL

Unit

tCK

K4D64163HE-TC50

Frequency

200MHz ( 5.0ns )

183MHz ( 5.5ns )

166MHz ( 6.0ns )

Unit

tCK

Cas Latency

tRC

tRFC

tRAS

tRCD

tRP

tRRD

tDAL

- 14 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

K4D64163HE-TC55

Unit

tCK

Frequency

183MHz ( 5.5ns )

166MHz ( 6.0ns )

Cas Latency

tRC

tRFC

tRAS

tRCD

tRP

tRRD

tDAL

K4D64163HE-TC60

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCD

tRP

tRRD

tDAL

Unit

166MHz ( 6.0ns )

tCK

Simplified Timing @ BL=4

CK, CK

BA[1:0]

BAa

BAb

BAa

BAb

A8/AP

ADDR

(A0~A7,

A9,A10)

DQS

Da0

Da0 Da1 Da2 Da3

Da1 Da2 Da3 Db0 Db1 Db2 Db3

COMMAND

ACTIVEA

WRITEA

PRECH

ACTIVEA

ACTIVEB WRITEA

WRITEB

tRCD

tRAS

tRP

tRC

tRRD

Normal Write Burst

(@ BL=4)

Multi Bank Interleaving Write Burst

(@ BL=4)

- 15 -

Rev. 0.2(Oct. 2001)

Target

64M DDR SDRAM

K4D64163HE

PACKAGE DIMENSIONS (66pin TSOP-II)

Units : Millimeters

#66

#34

(10×)

#33

+0.075

-0.035

0.125

(1.50)

22.22±0.10

(10×)

0.10 MAX

0.25TYP

(0.71)

0.65TYP

0.65±0.08

0.30±0.08

[

]

0.075 MAX

NOTE

1. (

0×~8×

) IS REFERENCE

2. [

] IS ASS’Y OUT QUALITY

- 16 -

Rev. 0.2(Oct. 2001)

K4D64163HE-TC60 [SAMSUNG]

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SI9130DB

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SI9135_11

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SI9130CG-T1-E3

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SI9130_11

SI9137

SI9137DB

SI9137LG

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