K4E171614C-TL60 [SAMSUNG]
EDO DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-50/44;
| 型号： | K4E171614C-TL60 |
| 厂家： | 
SAMSUNG |
| 描述： | EDO DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-50/44 动态存储器 光电二极管 |
| 文件： | 总35页 (文件大小：635K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4E171613(4)C
CMOS DRAM
Low Power 1M x 16Bit CMOS Dynamic RAM with EDO
DESCRIPTION
This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs with low operating & self refresh voltage. Extended Data Out
Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+3.0V/
+2.5V), access time (-60/-70), power consumption and package type(TSOP-Il) are optional features of this family. All of this family have
CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-ver.
This 1Mx16 EDO Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as buffer memory or main memory unit for mobile system.
FEATURES
• Extended Data Out Mode operation
(Fast Page Mode with Extended Data Out)
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• Part Identification
Operating
Voltage
Self-Refresh
Voltage(min)
Part No.
• RAS-only and Hidden refresh capability
• Self-refresh capability
K4E171613C-TL
K4E171613C-TN*
K4E171614C-TL
K4E171614C-TN*
3.0V
2.5V
2.5V
2.3V
• Self-refresh bump capability(3.0V product)
• LVTTL(3.0V/2.5V) compatible inputs and ouputs
• Early Write or output enable controlled write
• Available in plastic TSOP(ll) packages
• Single 3.0V+0.6V/-0.3V power supply (3.0V product)
• Single 2.5V±0.2V power supply (2.5V product)
* Extended temperature : -25°C to 85°C
• Active Power Dissipation
Unit : mW
Operation Voltage
Part No.
Speed
3.0V
324
-
2.5V
216
189
K4E171613C-TL(N)
K4E171614C-TL(N)
-60
-70
FUNCTIONAL BLOCK DIAGRAM
RAS
UCAS
LCAS
W
• Refresh Cycles
Part No.
Vcc
Vss
Control
Clocks
Refresh period
4K/128ms
VBB Generator
K4E171613C-TL(N)
K4E171614C-TL(N)
Lower
Data in
Buffer
DQ0
to
Row Decoder
Refresh Timer
Refresh Control
DQ7
Lower
Data out
Buffer
• Performance Range
Memory Array
1,048,576 x16
Cells
Speed
Part No.
tRAC tCAC
tRC
tHPC
OE
Refresh Counter
Row Address Buffer
Col. Address Buffer
Upper
Data in
Buffer
K4E171613C-TL(N)
K4E171614C-TL(N)
-60 60ns 17ns 104ns 25ns
-70 70ns 20ns 124ns 30ns
DQ8
to
DQ15
A0-A11
A0 - A7
Upper
Data out
Buffer
K4E171614C-TL(N)
Column Decoder
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
K4E171613(4)C
CMOS DRAM
PIN CONFIGURATION (Top Views)
• K4E171613(4)C-TL(N)
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
1
44
43
42
41
40
39
38
37
36
35
34
VSS
2
DQ15
DQ14
DQ13
DQ12
VSS
3
4
5
6
7
DQ11
DQ10
DQ9
DQ8
N.C
8
9
10
11
N.C
LCAS
UCAS
OE
N.C
N.C
W
RAS
A11
A10
A0
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
A9
A8
A7
A6
A1
A2
A3
A5
A4
VSS
VCC
(T : 400mil, 50(44) TSOP II)
Pin Name
A0 - A11
DQ0 - 15
VSS
Pin Function
Address Inputs
Data In/Out
Ground
RAS
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Read/Write Input
Data Output Enable
Power(3.0V)
UCAS
LCAS
W
OE
Vcc
N.C
Power(2.5V)
No Connection
K4E171613(4)C
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN,VOUT
VCC
K4E171613C-TL(N)
-0.5 to +4.6
K4E171614C-TL(N)
Units
V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
-0.5 to +3.6
-0.5 to +3.6
-55 to +150
-0.5 to +4.6
V
Tstg
-55 to +150
°C
W
Power Dissipation
PD
1
Short Circuit Output Current
IOS
50
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA =0°C to 70°C, -25°C to 85°C)
K4E171613C-TL(N)
K4E171614C-TL(N)
Parameter
Symbol
Power
Units
Min
2.7
2.5
0
Typ
Max
Min
Typ
Max
Read Write Supply Voltage
Self Refresh Supply Voltage
Ground
Don¢t care
L-ver
3.0
3.6
3.6
0
2.3
2.3
0
2.5
2.7
2.7
0
V
V
V
V
VCC
-
0
-
-
0
-
VSS
VIH
Don¢t care
Don¢t care
Vcc+0.3*1
0.8
Vcc+0.2*1
0.7
Input High Voltage
2.0
1.8
-0.3*2
-0.2*2
Input Low Voltage
VIL
Don¢t care
-
-
V
*1 : VCC+1.1V/12ns(3.0V), VCC+0.9V/10ns(2.5V), Pulse width is measured at VCC.
*2 : -1.1V/12ns(3.0V), -0.9V/10ns(2.5V), Pulse width is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0£VIN£VIN+0.3V,
all other input pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
-5
5
uA
K4E171613C-TL(N)
Output High Voltage Level(IOH=-2mA)
Output Low Voltage Level(IOL=2mA)
VOH
VOL
2.0
-
-
V
V
0.5
Input Leakage Current (Any input 0£VIN£VIN+0.3V,
all other input pins not under test=0 Volt)
II(L)
-5
-5
5
5
uA
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
K4E171614C-TL(N)
Output High Voltage Level(IOH=-2mA)
Output Low Voltage Level(IOL=2mA)
VOH
VOL
1.7
-
-
V
V
0.7
K4E171613(4)C
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol
Power
Speed
K4E171613C-TL(N)
K4E171614C-TL(N)
Units
-60
-70
90
-
80
70
mA
mA
ICC1
Don¢t care
ICC2
ICC3
Don¢t care
Don¢t care
Don¢t care
1
0.5
mA
-60
-70
90
-
80
70
mA
mA
-60
-70
100
-
90
80
mA
mA
ICC4
ICC5
ICC6
ICC7
Don¢t care
Don¢t care
Don¢t care
Don¢t care
Don¢t care
150
100
uA
-60
-70
90
-
80
70
mA
mA
Don¢t care
220
200
uA
Vcc=3.6V
Vcc=2.5V*1
Vcc=2.3V
150
100
-
-
-
uA
uA
uA
Don¢t care
ICCS
100
ICC1*2 : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3*2 : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)
ICC4*2 : Hyper Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6*2 : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=0.2V,
DQ=Don¢t care, TRC=31.25us(4K/L-ver),
TRAS=TRASmin~300ns
ICCS : Self Refresh Current
RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,
DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open.
Note *1 : Self-Refresh bumping voltage(=Minimum voltage in self refresh mode)
Note *2 :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one Hyper page mode cycle time, tHPC.
K4E171613(4)C
CMOS DRAM
CAPACITANCE (TA=25°C, VCC @K4E171613C-TL(N) & @K4E171614C-TL(N), f=1MHz)
Parameter
Input capacitance [A0 ~ A11]
Symbol
CIN1
Min
Max
Units
pF
-
-
-
5
7
7
Input capacitance [RAS, UCAS, LCAS, W, OE]
Output capacitance [DQ0 - DQ15]
CIN2
pF
CDQ
pF
AC CHARACTERISTICS (0°C£TA£70°C, -25°C£TA£85°C, See note 1,2)
Test condition (K4E171613C-TL(N)) : VCC=3.0V+0.6V/-0.3V, Vih/Vil=2.2V/0.6V, Voh/Vol=1.8V/1.0V
Test condition (K4E171614C-TL(N)) : VCC=2.5V±0.2V, Vih/Vil=2.0V/0.6V, Voh/Vol=1.8V/0.6V
-60*1
-70*1
Parameter
Symbol
Units
Notes
Min
104
140
Max
Min
124
170
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tRWC
tRAC
tCAC
tAA
60
17
30
70
20
35
3,4,10
3,4,5
3,10
3
Access time from CAS
Access time from column address
CAS to output in Low-Z
3
3
3
3
tCLZ
tCEZ
tOLZ
tT
Output buffer turn-off delay from CAS
OE to output in Low-Z
15
50
20
50
6,19
3
3
3
Transition time (rise and fall)
RAS precharge time
2
2
2
40
60
17
50
10
20
15
5
50
70
20
60
15
20
15
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
CAS hold time
CAS pulse width
10K
43
10K
50
18
4
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
30
35
10
0
0
10
0
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
11
11
10
30
0
15
35
0
0
0
8
8
0
0
10
10
15
10
15
15
20
15
tRWL
tCWL
14
*1 : K4E171613C-TL(N) supports -60 only and K4E171614C-TL(N) supports -60/-70.
K4E171613(4)C
CMOS DRAM
AC CHARACTERISTICS (Continued)
-60*1
-70*1
Parameter
Symbol
Units
Notes
Min
0
Max
Min
0
Max
Data set-up time
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ms
ms
9,17
9,17
tDS
Data hold time
10
15
tDH
Refresh period (L-version)
128
128
tREF
Write command set-up time
CAS to W delay time
0
0
7
7,13
7
tWCS
tCWD
tRWD
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
tHPC
tHPRWC
tCP
36
79
49
54
5
44
94
59
64
5
RAS to W delay time
Column address W delay time
CAS precharge to W delay time
CAS set-up time (CAS -before-RAS refresh)
CAS hold time (CAS -before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper Page mode cycle time
Hyper Page read-modify-write cycle time
CAS precharge time (Hyper Page cycle)
RAS pulse width (Hyper Page cycle)
RAS hold time from CAS precharge
OE access time
7
7
15
16
10
5
15
5
35
40
3
25
56
10
60
35
30
71
10
70
40
18
18
12
200K
15
200K
20
tRASP
tRHCP
tOEA
tOED
tOEZ
tOEH
tDOH
tREZ
3
6
OE to data delay
15
3
20
3
Output buffer turn off delay time from OE
OE command hold time
15
20
15
5
20
5
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
3
15
15
3
20
20
6,19
6
3
3
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
tRASS
tRPS
tCHS
tENT
15
5
20
5
OE to CAS hold time
CAS hold time to OE
5
5
OE precharge time
5
5
W pulse width (Hyper Page Cycle)
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)
Entrance Time to BUMP voltage
Exit time from BUMP voltage
Voltage Transition time
5
5
100
110
-50
0
100
130
-50
0
20,21,22
20,21,22
20,21,22
23
256
0.5
256
0.5
23
tEXT
23
tBMP
*1 : K4E171613C-TL(N) supports -60 only and K4E171614C-TL(N) supports -60/-70.
K4E171613(4)C
CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
1.
2.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 1 TTL 100pF(3.0V) and 50pF(2.5V) loads.
3.
4.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5. Assumes that tRCD³ tRCD(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCS³ tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min), tAWD³ tAWD(min) and tCPWD³ tCPWD(min), then the cycle is a read-
modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is
satisfied, the condition of the data out is indeterminate.
7.
8. Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and
read-modify-write cycles.
9.
10.
11.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
tASC, tCAH are referenced to the earlier CAS falling edge.
12. tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
tCWL is specified from W falling edge to the earlier CAS rising edge.
13.
14.
K4E171613(4)C-TL(N) Truth Table
RAS
H
L
LCAS
UCAS
W
X
X
H
H
H
L
OE
X
X
L
DQ0 - DQ7
Hi-Z
DQ8-DQ15
Hi-Z
STATE
Standby
Refresh
X
H
L
X
H
H
L
Hi-Z
Hi-Z
L
DQ-OUT
Hi-Z
Hi-Z
Byte Read
Byte Read
Word Read
Byte Write
Byte Write
Word Write
-
L
H
L
L
DQ-OUT
DQ-OUT
-
L
L
L
DQ-OUT
DQ-IN
-
L
L
H
L
H
H
H
H
L
H
L
L
DQ-IN
DQ-IN
Hi-Z
L
L
L
DQ-IN
Hi-Z
L
L
L
H
K4E171613(4)C
CMOS DRAM
15.
16.
tCSR is referenced to the earlier CAS falling edge before RAS transition low.
tCHR is referenced to the later CAS rising edge after RAS transition low.
RAS
LCAS
UCAS
tCSR
tCHR
17. tDS, tDH is independently specified for lower byte DQ(0-7), upper byte DQ(8-15).
tASC³ 6ns, Assume tT=2.0ns.
18.
19.
If RAS goes to high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes to high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
If tRASS³ 100us, then RAS precharge time must use tRPS instead of tRP.
20.
21. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K) cycles of burst refresh must be executed within 64ms
before and after self refresh, in order to meet refresh specification.
22. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.
In case of Self Refresh Bump Mode, the Vcc can be forced down to 2.5V(at K4E171613C-TL(N)).
The whole operation can be achieved by following timing diagram.
23.
tBMP
tENT
tBMP
VCC
tEXT
tRASS
tRPS
tRPC
VIH -
RAS
VIL -
tCHS
tCSR
VIH -
LCAS
UCAS VIL -
Don¢t care
OE, W , A = Don¢t care
DQ0~DQ15=Hi-Z
K4E171613(4)C
CMOS DRAM
WORD READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCSH
tCRP
tCRP
tCRP
tRCD
tRCD
tRSH
tCAS
VIH -
UCAS
VIL -
tCRP
tRSH
tCAS
VIH -
LCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
ROW
ADDRESS
COLUMN
ADDRESS
A
VIL -
tRCH
tRRH
VIH -
W
VIL -
tAA
tOLZ
tOEA
VIH -
OE
VIL -
tCAC
tCLZ
tCEZ
tCEZ
tOEZ
DATA-OUT
DQ0 ~ DQ7
VOH -
tRAC
OPEN
OPEN
VOL -
tCAC
tCLZ
tOEZ
DATA-OUT
DQ8 ~ DQ15
VOH -
tRAC
VOL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
LOWER BYTE READ CYCLE
NOTE : DIN = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tRPC
tCRP
VIH -
UCAS
VIL -
tCSH
tCRP
tRCD
tRSH
tCAS
VIH -
LCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tRCH
tRRH
VIH -
VIL -
tCEZ
tOEZ
tAA
VIH -
VIL -
tOEA
tCAC
OE
tCLZ
DQ0 ~ DQ7
tRAC
VOH -
OPEN
DATA-OUT
VOL -
tOLZ
DQ8 ~ DQ15
VOH -
OPEN
VOL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
UPPER BYTE READ CYCLE
NOTE : DIN = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
UCAS
VIL -
tCRP
tRPC
VIH -
LCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
ROW
COLUMN
ADDRESS
A
ADDRESS
VIL -
tRCH
tRRH
VIH -
VIL -
W
tCEZ
tOEZ
tAA
VIH -
VIL -
tOEA
tOLZ
OE
DQ0 ~ DQ7
VOH -
OPEN
VOL -
tCAC
tCLZ
DQ8 ~ DQ15
tRAC
VOH -
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
UCAS
VIL -
tCRP
tCRP
tRCD
tRSH
VIH -
tCAS
LCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tWCS
tWCH
VIH -
VIL -
tWP
VIH -
VIL -
OE
tDS
tDS
DQ0 ~ DQ7
tDH
DATA-IN
VIH -
VIL -
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
VIL -
RAS
UCAS
LCAS
tCRP
tCRP
VIH -
VIL -
tCSH
tCRP
tRCD
tRSH
VIH -
VIL -
tCAS
tRAD
tRAH tASC
tRAL
tASR
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tWCS
tWCH
VIH -
VIL -
tWP
VIH -
VIL -
OE
tDS
tDH
DATA-IN
DQ0 ~ DQ7
VIH -
VIL -
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
VIL -
RAS
UCAS
LCAS
tCSH
tCRP
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
VIH -
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tWCS
tWCH
VIH -
VIL -
tWP
W
VIH -
VIL -
OE
DQ0 ~ DQ7
VIH -
VIL -
tDS
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
WORD WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tRCD
tCRP
tRSH
tCAS
VIH -
VIL -
UCAS
LCAS
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
VIL -
tCAS
tRAD
tASC
tRAL
tASR
tRAH
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tCWL
tRWL
VIH -
VIL -
tWP
VIH -
VIL -
OE
tOEH
tOED
tDS
tDS
tDH
DATA-IN
DQ0 ~ DQ7
VIH -
VIL -
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tRPC
tCRP
VIH -
UCAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
LCAS
tRAD
tRAH tASC
tRAL
tASR
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
tCWL
tRWL
VIH -
VIL -
tWP
W
VIH -
VIL -
tOEH
OE
tOED
tDS
tDH
DATA-IN
DQ0 ~ DQ7
VIH -
VIL -
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
UCAS
LCAS
tCRP
tCRP
VIH -
VIL -
tRAD
tASC
tRAL
tASR
tRAH
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
tCWL
tRWL
VIH -
VIL -
W
tWP
VIH -
VIL -
tOEH
OE
tOED
DQ0 ~ DQ7
VIH -
VIL -
tDS
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
WORD READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
RAS
VIL -
tCRP
tCRP
tRCD
tRCD
tRSH
tCAS
VIH -
VIL -
UCAS
LCAS
tRSH
tCAS
VIH -
VIL -
tRAD
tRAH
tCSH
tASR
tASC
tCAH
VIH -
VIL -
ROW
ADDR.
COLUMN
ADDRESS
A
tAWD
tRWL
tCWL
tWP
tCWD
VIH -
VIL -
W
tRWD
tOEA
VIH -
VIL -
OE
tOLZ
tCLZ
tCAC
tAA
tOED
tOEZ
tDS
tDH
DQ0 ~ DQ7
tRAC
VI/OH -
VALID
DATA-OUT
VALID
DATA-IN
VI/OL -
tOLZ
tCLZ
tCAC
tAA
tOED
tOEZ
tDS
tDH
DQ8 ~ DQ15
tRAC
VI/OH -
VALID
DATA-OUT
VALID
DATA-IN
VI/OL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
LOWER-BYTE READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
RAS
VIL -
tRPC
tCRP
VIH -
UCAS
VIL -
tCRP
tRCD
tRSH
VIH -
VIL -
tCAS
LCAS
tRAD
tRAH
tCSH
tASR
tASC
tCAH
VIH -
VIL -
ROW
ADDR.
COLUMN
ADDRESS
A
tAWD
tRWL
tCWL
tWP
tCWD
VIH -
VIL -
W
tRWD
tOEA
VIH -
VIL -
OE
tOLZ
tCLZ
tCAC
tOED
tOEZ
tAA
tDS
tDH
DQ0 ~ DQ7
VI/OH -
tRAC
VALID
DATA-OUT
VALID
DATA-IN
VI/OL -
DQ8 ~ DQ15
VOH -
OPEN
VOL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
UPPER-BYTE READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
VIL -
RAS
UCAS
LCAS
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
tRPC
VIH -
VIL -
tRAD
tRAH
tCSH
tASR
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tAWD
tRWL
tCWL
tWP
tCWD
VIH -
VIL -
W
tRWD
tOEA
VIH -
VIL -
OE
DQ0 ~ DQ7
VOH -
OPEN
VOL -
tOLZ
tCLZ
tCAC
tOED
tOEZ
tAA
tDS
tDH
DQ8 ~ DQ15
tRAC
VI/OH -
VALID
DATA-OUT
VALID
DATA-IN
VI/OL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
HYPER PAGE MODE WORD READ CYCLE
tRASP
tRP
VIH -
RAS
VIL -
tCSH
tHPC
tRHCP
tCAS
tHPC
tCAS
tHPC
tCRP
tCP
tCP
tCP
tRCD
tCAS
tCAS
VIH -
VIL -
UCAS
tREZ
tCRP
tASR
tCP
tCP
tCP
tRCD
tCAS
tCAH
tCAS
tCAH
tCAS
tCAH
tCAS
tCAH
VIH -
VIL -
LCAS
A
tRAD
tRAH tASC
tASC
tASC
tASC
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
ADDRESS
tRAL
tRRH
tRCS
tRCH
VIH -
VIL -
W
tCPA
tCAC
tAA
tAA
tCPA
tCAC
tCAC
tAA
tCPA
tCHO
tOEP
tOCH
tOEA
tOEA
VIH -
VIL -
OE
tCAC
tOEP
tOEZ
tDOH
DQ0 ~ DQ7
VOH -
tRAC
tOEZ
tOEZ
VALID
VALID
VALID
VALID
VALID
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
VOL -
tOLZ
tCLZ
tCAC
tOEP
tOEZ
tDOH
tOEZ
tRAC
DQ8 ~ DQ15
VOH -
VALID
VALID
VALID
VALID
VALID
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
VOL -
tOLZ
tCLZ
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
HYPER PAGE MODE LOWER BYTE READ CYCLE
tRP
tRASP
VIH -
RAS
VIL -
¡ó
tRPC
tCRP
VIH -
UCAS
tCSH
tRHCP
tHPC
VIL -
tHPC
tHPC
tREZ
tCP
tCP
tCP
tRCD
tCAS
tCAH
tCAS
tCAS
tCAS
tCAH
VIH -
VIL -
LCAS
A
tRAD
tRAH tASC
tASR
tASC
tCAH
tASC
tCAH tASC
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
ADDRESS
tRAL
tRRH
tRCS
tRCH
VIH -
VIL -
W
tCPA
tCAC
tAA
tAA
tCPA
tCAC
tCAC
tAA
tCPA
tAA
tOEA
tCHO
tOEP
tOCH
tOEA
VIH -
VIL -
OE
tCAC
tOEP
tOEZ
tDOH
DQ0 ~ DQ7
tOEZ
tOEZ
tRAC
VOH -
VALID
DATA-OUT
VALID
VALID
VALID
VALID
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
VOL -
tOLZ
tCLZ
DQ8 ~ DQ15
VOH -
OPEN
VOL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
HYPER PAGE MODE UPPER BYTE READ CYCLE
tRASP
tRP
VIH -
RAS
VIL -
¡ó
tCSH
tRHCP
tCAS
tHPC
tHPC
tCAS
tHPC
tCRP
tCP
tCP
tCP
tRPC
tRPC
tRCD
tCAS
tCAS
VIH -
VIL -
UCAS
tCRP
tASR
VIH -
VIL -
LCAS
A
tRAD
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
tREZ
VIH -
VIL -
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR.
COLUMN
ADDRESS
tRAL
tRRH
tRCS
tRCH
VIH -
VIL -
W
tCPA
tCAC
tAA
tCAC
tAA
tCPA
tAA
tCPA
tCAC
tCHO
tOEP
tOCH
tOEA
tOEA
VIH -
VIL -
OE
DQ0 ~ DQ7
VOH -
OPEN
VOL -
tCAC
tOEP
tOEZ
tDOH
tOEZ
tOEZ
tRAC
DQ8 ~ DQ15
VOH -
VALID
DATA-OUT
VALID
VALID
VALID
VALID
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
VOL -
tOLZ
tCLZ
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP
tRP
VIH -
RAS
tRHCP
VIL -
¡ó
tHPC
tHPC
tHPC
tHPC
tRSH
tCRP
tCRP
tCP
tCP
tCP
tCP
tCRP
tRCD
tRCD
VIH -
VIL -
tCAS
tCAS
tCAS
¡ó
tCAS
UCAS
LCAS
tRSH
VIH -
VIL -
tCAS
¡ó
tCAS
tRAD
tRAH
tRAL
tCAH
tCSH
tASC
tASR
tCAH
tASC
tCAH
tASC
¡ó
¡ó
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
A
tWCS tWCH
tWP
tWCS
tWCH
tWP
tWCS
tWCH
tWP
¡ó
VIH -
VIL -
W
¡ó
¡ó
VIH -
VIL -
OE
tDS
tDS
tDH
tDS
tDH
tDS
tDH
DQ0 ~ DQ7
¡ó
¡ó
VIH -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
VIL -
tDH
tDS
tDH
tDS
tDH
DQ8 ~ DQ15
¡ó
¡ó
VIH -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
VIL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP
tRP
VIH -
tRHCP
RAS
VIL -
¡ó
tRPC
tCRP
VIH -
UCAS
VIL -
tHPC
tHPC
tRSH
tCRP
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
¡ó
tCAS
tRAL
tCAH
LCAS
tRAD
tCSH
tASC
tASR
tASC
tCAH
tRAH
tASC
tCAH
COLUMN
¡ó
¡ó
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
A
ADDRESS
tWCS
tWP
tWCH
tWCS
tWCH
tWP
tWCS
tWCH
tWP
¡ó
VIH -
VIL -
W
¡ó
¡ó
VIH -
VIL -
OE
tDS
tDH
tDS
tDH
tDS
tDH
DQ0 ~ DQ7
¡ó
¡ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP
tRP
VIH -
tRHCP
RAS
VIL -
¡ó
tHPC
tHPC
tRSH
tCRP
tCRP
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
¡ó
tCAS
UCAS
LCAS
tRPC
VIH -
VIL -
tRAD
tRAH
tRAL
tCAH
tCSH
tASC
tASR
tCAH
tASC
tCAH
COLUMN
tASC
¡ó
¡ó
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
A
ADDRESS
tWCS
tWP
tWCH
tWCS
tWCH
tWP
tWCS
tWCH
tWP
¡ó
VIH -
VIL -
W
¡ó
¡ó
VIH -
VIL -
OE
DQ0 ~ DQ7
¡ó
¡ó
VIH -
VIL -
tDS
tDH
tDS
tDH
tDS
tDH
DQ8 ~ DQ15
¡ó
¡ó
VIH -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
VIL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE
tRP
tRASP
VIH -
VIL -
tCSH
tHPRWC
RAS
tRSH
tCAS
tCRP
tCRP
tRCD
tRCD
tCRP
tCRP
tCP
tCP
VIH -
VIL -
tCAS
tCAS
UCAS
LCAS
VIH -
VIL -
tCAS
tRAD
tRAH
tRAL
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
ADDR
COL.
ADDR
A
W
tRWL
tCWL
tRCS
tCWL
tRCS
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tCAC
tCLZ
tDH
tDH
tAA
tAA
tDS
tDS
tOEZ
tOEZ
DQ0 ~ DQ7
tRAC
VI/OH -
VI/OL -
tCLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
tOED
tOED
tCAC
tAA
tCAC
tDH
tDH
tAA
tDS
tDS
tOEZ
tOEZ
DQ8 ~ DQ15
tRAC
tCLZ
VI/OH -
VI/OL -
tCLZ
VALID
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-OUT
DATA-IN
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
tRP
tRASP
VIH -
VIL -
tCSH
tHPRWC
RAS
tRPC
tCRP
tCRP
VIH -
VIL -
UCAS
LCAS
tRSH
tCAS
tCP
tCRP
tRCD
VIH -
VIL -
tCAS
tRAD
tRAH
tRAL
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
ADDR
COL.
ADDR
A
W
tRWL
tCWL
tRCS
tRCS
tCWL
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tCWD
tAWD
tCPWD
tRWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tCAC
tDH
tAA
tDH
tAA
tDS
tOEZ
tDS
DQ0 ~ DQ7
tRAC
tOEZ
VI/OH -
VI/OL -
tCLZ
tCLZ
tOLZ
tOLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
DQ8 ~ DQ15
VI/OH -
OPEN
VI/OL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
tRP
tRASP
VIH -
VIL -
tCSH
tHPRWC
RAS
tRSH
tCAS
tCRP
tCRP
tCP
tRCD
tCRP
VIH -
VIL -
tCAS
UCAS
LCAS
tRPC
VIH -
VIL -
tRAD
tRAH
tRAL
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
ADDR
COL.
ADDR
A
W
tRWL
tCWL
tRCS
tRCS
tCWL
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
DQ0 ~ DQ7
VI/OH -
OPEN
VI/OL -
tOLZ
tOLZ
tOED
tOED
tCAC
tCAC
tAA
tDH
tDH
tAA
tDS
tOEZ
tDS
DQ8 ~ DQ15
tRAC
tCLZ
tOEZ
VI/OH -
VI/OL -
tCLZ
VALID
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
DATA-IN
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
HYPER PAGE READ AND WRITE MIXED CYCLE
tRP
tRASP
VIH -
VIL -
READ(tCAC)
READ(tCPA)
WRITE
READ(tAA)
RAS
tRHCP
tHPC
tHPC
tHPC
tCP
tCP
tCP
tCP
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAS
tCAS
tHPC
tCAS
tHPC
UCAS
LCAS
tRCD
tHPC
tCAS
VIH -
VIL -
tCAS
tCAS
tCAH
tRAD
tRAH
tASC
tCAH
tASR
tCAH
tASC
tASC
tCAH
tASC
VIH -
VIL -
COLUMN
ADDRESS
COL.
ADDR
COL.
ADDR
ROW
ADDR
COLUMN
A
ADDRESS
tRCS
tRAL
tRCH
tRCS
tRCH
tWCH
tRCH
VIH -
VIL -
tWCS
W
tWPE
tCPA
tCLZ
tWED
VIH -
VIL -
OE
tOEA
tDH
tDS
tWEZ
tCAC
tAA
tRAC
tWEZ
tAA
tAA
tREZ
DQ0 ~ DQ7
VI/OH -
VALID
VALID
VALID
DATA-OUT
VALID
DATA-OUT
DATA-IN
DATA-OUT
VI/OL -
tOEA
tCAC
tAA
tRAC
tDH
tDS
tWEZ
tWEZ
tREZ
DQ8 ~ DQ15
VI/OH -
VALID
VALID
VALID
VALID
DATA-OUT
DATA-IN
DATA-OUT
DATA-OUT
VI/OL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
RAS - ONLY REFRESH CYCLE
NOTE : W, OE , DIN = Don¢t care
DOUT = OPEN
tRC
tRP
VIH -
tRAS
RAS
VIL -
tRPC
tCRP
VIH -
UCAS
VIL -
tCRP
VIH -
LCAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCSR
tCSR
VIH -
VIL -
tCHR
tCHR
UCAS
LCAS
tCP
VIH -
VIL -
DQ0 ~ DQ7
tCEZ
VOH -
OPEN
OPEN
VOL -
DQ8 ~ DQ15
VOH -
VOL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
tRAS
tRC
tRAS
tRP
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tRSH
tCHR
VIH -
VIL -
UCAS
LCAS
tCRP
tCHR
tRCD
VIH -
VIL -
tRAD
tASR
ROW
tRAH
tASC
tCAH
COLUMN
ADDRESS
VIH -
VIL -
A
W
ADDRESS
tWRH
tRCS
VIH -
VIL -
tRAL
tAA
VIH -
VIL -
tOEA
tOLZ
OE
tCEZ
tREZ
tCAC
tCLZ
tRAC
tWEZ
DQ0 ~ DQ7
tOEZ
VOH -
DATA-OUT
OPEN
VOL -
DQ8 ~ DQ15
VOH -
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tRSH
tCHR
tCHR
VIH -
UCAS
VIL -
tCRP
tRCD
VIH -
LCAS
VIL -
tRAD
tASR
ROW
tRAH
tASC
tCAH
COLUMN
ADDRESS
VIH -
VIL -
A
W
ADDRESS
tWRH
tWRP
tWCS
tWCH
VIH -
VIL -
tWP
VIH -
VIL -
OE
tDS
tDS
tDH
DATA-IN
DQ0 ~ DQ7
VIH -
VIL -
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCHS
tCHS
tCSR
tCSR
VIH -
VIL -
UCAS
LCAS
tCP
VIH -
VIL -
tCEZ
DQ0 ~ DQ7
VOH -
OPEN
OPEN
VOL -
DQ8 ~ DQ15
VOH -
VOL -
Don¢t care
Undefined
K4E171613(4)C
CMOS DRAM
50(44) TSOP(II) 400mil
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.841 (21.35)
MAX
0.821 (20.85)
0.829 (21.05)
0.047 (1.20)
MAX
0.010 (0.25)
TYP
0.034 (0.875)
0.0315 (0.80)
0.002 (0.05)
MIN
0.010 (0.25)
0.018 (0.45)
O
0~8
0.018 (0.45)
0.030 (0.75)
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