K4H560438N-LLB3 [SAMSUNG]

DDR DRAM, 64MX4, 0.7ns, CMOS, PDSO66;


型号：	K4H560438N-LLB3
厂家：	SAMSUNG
描述：	DDR DRAM, 64MX4, 0.7ns, CMOS, PDSO66 动态存储器双倍数据速率光电二极管
文件：	总24页 (文件大小：589K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Rev. 1.01, May. 2010

K4H560438N

K4H560838N

K4H561638N

256Mb N-die DDR SDRAM

66TSOP-(II) with Lead-Free & Halogen-Free

(RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung

Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property

right is granted by one party to the other party under this document, by implication, estoppel or other-

wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or

similar applications where product failure could result in loss of life or personal or physical harm, or any

military or defense application, or any governmental procurement to which special terms or provisions

may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

- 1 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

Revision History

Revision No.

History

Draft Date

Apr. 2010

May. 2010

Remark

Editor

S.H.Kim

1.0

- First Release

1.01

- Corrected Typo.

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Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

Table Of Contents

256Mb N-die DDR SDRAM

1. Key Features.................................................................................................................................................................4

2. Ordering Information.....................................................................................................................................................4

3. Operating Frequencies .................................................................................................................................................4

4. Pin / Ball Description.....................................................................................................................................................5

5. Package Physical Dimension........................................................................................................................................6

6. Block Diagram (16Mb x4 / 8Mbx8 / 4Mx16 I/O x4 Banks) ............................................................................................7

7. Input/Output Function Description ................................................................................................................................8

8. Command Truth Table..................................................................................................................................................9

9. General Description ......................................................................................................................................................10

10. Absolute Maximum Rating..........................................................................................................................................10

11. DC Operating Conditions............................................................................................................................................10

12. DDR SDRAM Spec Items & Test Conditions..............................................................................................................11

13. Input/Output Capacitance ...........................................................................................................................................11

14. Detailed test condition for DDR SDRAM IDD1 & IDD7A ............................................................................................12

15. DDR SDRAM IDD Spec Table....................................................................................................................................13

16. AC Operating Conditions ............................................................................................................................................14

17. AC Overshoot/Undershoot specification for Address and Control Pins ......................................................................14

18. Overshoot/Undershoot specification for Data, Strobe and Mask Pins........................................................................15

19. AC Timing Parameters & Specifications.....................................................................................................................16

20. System Characteristics for DDR SDRAM ...................................................................................................................17

21. Component Notes.......................................................................................................................................................18

22. System Notes..............................................................................................................................................................20

23. IBIS : I/V Characteristics for Input and Output Buffers................................................................................................21

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DDR SDRAM

1. Key Features

• V_DD: 2.5V ± 0.2V, V_DDQ: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)

• Four banks operation

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• MRS cycle with address key programs

-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

• Data I/O transactions on both edges of data strobe

• Edge aligned data output, center aligned data input

• LDM,UDM for write masking only (x16)

• DM for write masking only (x4, x8)

• Auto & Self refresh

• 7.8us refresh interval(8K/64ms refresh)

• Maximum burst refresh cycle : 8

• 66pin TSOP II Lead-Free & Halogen-Free package

• RoHS compliant

2. Ordering Information

Part No.

K4H560438N-LC/LB3

K4H560438N-LC/LB0

K4H560838N-LC/LCC

K4H560838N-LC/LB3

K4H561638N-LC/LCC

K4H561638N-LC/LB3

Org.

Max Freq.

Interface

Package

NOTE

1, 2

B3(DDR333@CL=2.5)

B0(DDR266@CL=2.5)

CC(DDR400@CL=3)

B3(DDR333@CL=2.5)

CC(DDR400@CL=3)

B3(DDR333@CL=2.5)

66pin TSOP II

Lead-Free & Halogen-Free

64M x 4

SSTL2

66pin TSOP II

Lead-Free & Halogen-Free

32M x 8

SSTL2

1, 2

66pin TSOP II

Lead-Free & Halogen-Free

16M x 16

1, 2

NOTE :

1. "-B3"(DDR333, CL=2.5) can support "-B0"(DDR266, CL=2.5)/ "-A2"(DDR266, CL=2).

2. "L" of Part number(12th digit) stands for RoHS compliant and Halogen-Free product.

3. Operating Frequencies

CC(DDR400@CL=3)

B3(DDR333@CL=2.5)

A2(DDR266@CL=2.0)

B0(DDR266@CL=2.5)

Speed @CL2

Speed @CL2.5

Speed @CL3

CL-tRCD-tRP

133MHz

166MHz

133MHz

100MHz

133MHz

166MHz

200MHz

3-3-3

2.5-3-3

2-3-3

2.5-3-3

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datasheet

DDR SDRAM

4. Pin / Ball Description

16Mb x 16

32Mb x 8

64Mb x 4

VSS

V^SSQ

DQ³

VDDQ

V^SSQ

DQ²

VDDQ

VSSQ

DQS

V^REF

V^SS

CKE

A¹²

A11

V^SS

DQ⁷

V^SSQ

VSS

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

DQ0

V^DDQ

VDD

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

V^DDQ

DQ⁶

V^DDQ

DQ¹

V^SSQ

DQ⁰

VSSQ

DQ⁵

V^SSQ

DQ²

V^DDQ

66Pin TSOPII

(400mil x 875mil)

(0.65mm Pin Pitch)

DQ⁴

V^DDQ

DQ3

V^SSQ

DQ¹

VSSQ

Bank Address

BA0~BA1

V^SSQ

DQS

VSSQ

UDQS

V^DDQ

LDQS

V^DDQ

Auto Precharge

A10

V^REF

V^SS

V^REF

V^SS

VDD

V^DD

UDM

LDM

CAS

RAS

CAS

RAS

CAS

RAS

CKE

A¹²

A¹¹

A¹²

A11

BA0

BA1

AP/A10

BA⁰

BA¹

AP/A¹⁰

A⁰

BA0

BA1

AP/A10

A⁹

A⁸

A⁷

A⁶

A¹

A⁵

A²

A⁴

A³

V^SS

VSS

V^DD

256Mb TSOP-II Package Pinout

Organization

64Mx4

Row Address

A0~A12

Column Address

A0-A9, A11

A0-A9

32Mx8

A0~A12

16Mx16

A0~A12

A0-A8

DM is internally loaded to match DQ and DQS identically.

Figure 1. Row & Column address configuration

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datasheet

DDR SDRAM

5. Package Physical Dimension

Unit : mm

#66

#34

#33

(1.50)

+0.075

- 0.035

0.125

22.22 ± 0.10

(10ℜ°)

0.10 MAX

[

(10ℜ°)

0.65TYP

[0.65 ± 0.08]

0.075 MAX

[

(0.71)

Detail A

Detail B

0.25TYP

NOTE

1. ( ) IS REFERENCE

2. [ ] IS ASS‚ÄôY OUT QUALITY

Detail A

(0ℜ° ∼ 8ℜ°)

± 0.08

0.30

0.25

Figure 2. 66Pin TSOP(II) Package Dimension

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Rev. 1.01

K4H560438N

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datasheet

DDR SDRAM

6. Block Diagram (16Mb x4 / 8Mbx8 / 4Mx16 I/O x4 Banks)

LWE

x4/8/16

CK, CK

Data Input Register

Serial to parallel

LDM (x4x8)

LUDM (x16)

Bank Select

x8/16/32

8Mx8 / 4Mx16 / 2Mx32

x8/16/32

x4/8/16

DQi

CK, CK

ADD

Column Decoder

Latency & Burst Length

Data Strobe

Programming Register

LWCBR

LCKE

LDM (x4x8)

LUDM (x16)

LRAS LCBR

LWE

LCAS

CK, CK

DM Input Register

Timing Register

LDM (x4x8)

LUDM (x16)

CK, CK

CKE

RAS

CAS

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DDR SDRAM

7. Input/Output Function Description

SYMBOL

TYPE

DESCRIPTION

Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the

positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Inter-

nal clock signals are derived from CK/CK.

CK, CK

Input

Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buf-

fers and output drivers. Taking CKE Low provides PRECHARGE POWER-DOWN and SELF REFRESH

operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for

POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH

exit, and for output disable. CKE must be maintained high throughput READ and WRITE accesses. Input

buffers, excluding CK, CK and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are

disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS Low level after V_DD

CKE

Input

is applied upon 1st power up, After V_REFhas become stable during the power on and initialization

sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH

entry and exit, V_REFmust be maintained to this input.

Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All com-

mands are masked when CS is registered HIGH. CS provides for external bank selection on systems with

multiple banks. CS is considered part of the command code.

Input

RAS, CAS, WE

Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled

HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although

DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds

to the data on DQ0~D7 ; UDM corresponds to the data on DQ8~DQ15. DM may be driven high, low, or

floating during READs.

LDM,(UDM)

BA0, BA1

Input

Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE

command is being applied.

Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO

PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the

respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE

applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is

selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET com-

mand. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command

(MRS or EMRS).

A [0 : 12]

Input

I/O

Data Input/Output : Data bus

Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write

data. Used to capture write data. For the x16, LDQS corresponds to the data on

DQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15.

LDQS,(U)DQS

LDQS is NC on x4 and x8.

No Connect : No internal electrical connection is present.

DQ Power Supply : +2.5V ± 0.2V.

DQ Ground.

V_DDQ

Supply

Input

V_SSQ

V_DD

Power Supply : +2.5V ± 0.2V.

Ground.

V_SS

V_REF

SSTL_2 reference voltage.

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K4H561638N

datasheet

DDR SDRAM

8. Command Truth Table

(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)

A0 ~ A9,

A11 ~ A12

COMMAND

CKEn-1 CKEn

RAS

CAS

BA0,1

A10/AP

OP CODE

NOTE

Extended MRS

Mode Register Set

Auto Refresh

1, 2

OP CODE

Entry

Exit

Refresh

Self

Refresh

Bank Active & Row Addr.

Row Address

Read &

Column Address

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

Column

Address

Write &

Column Address

Column

Address

4, 6

Burst Stop

Precharge

Bank Selection

All Banks

Entry

Exit

Active Power Down

Entry

Precharge Power Down Mode

Exit

DM(UDM/LDM for x16 only)

No operation (NOP) : Not defined

NOTE :

1. OP Code : Operand Code. A0 ~ A12& BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges

(Write UDM/LDM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

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K4H560438N

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datasheet

DDR SDRAM

16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks Double Data Rate SDRAM

9. General Description

The K4H560438N / K4H560838N / K4H561638N is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 16,777,216 / 4x 8,388,608

/ 4x 4,194,304 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable

burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

10. Absolute Maximum Rating

Parameter

Symbol

Value

Unit

Voltage on any pin relative to V_SS

V_IN, V_OUT

-0.5 ~ 3.6

Voltage on V_DD& V_DDQsupply relative to V_SS

Storage temperature

V_DD, V_DDQ

T_STG

P_D

1.0 ~ 3.6

°C

-55 ~ +150

Power dissipation

Short circuit current

I_OS

NOTE : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommend operation condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

11. DC Operating Conditions

Recommended operating conditions(Voltage referenced to V_SS=0V, TA=0 to 70°C)

Parameter

Symbol

Min

Max

Unit

NOTE

Supply voltage

V_DD

2.3

2.7

I/O Supply voltage

V_DDQ

2.3

2.7

0.51*V_DDQ

V_REF+0.04

V_DDQ+0.3

V_REF-0.15

V_DDQ+0.3

V_DDQ+0.6

1.4

I/O Reference voltage

V_REF

V_TT

0.49*V_DDQ

I/O Termination voltage(system)

Input logic high voltage

Input logic low voltage

V_REF-0.04

_IH(DC)

V_REF+0.15

-0.3

0.36

0.71

-2

V_IL(DC)

V_IN(DC)

V_ID(DC)

V_I(Ratio)

I_I

Input Voltage Level, CK and CK inputs

Input Differential Voltage, CK and CK inputs

V-I Matching: Pullup to Pulldown Current Ratio

Input leakage current

Output leakage current

I_OZ

-5

Output High Current(Normal strengh driver) ;V_OUT= V_TT+ 0.84V

Output High Current(Normal strengh driver) ;V_OUT= V_TT- 0.84V

Output High Current(Half strengh driver) ;V_OUT= V_TT+ 0.45V

Output High Current(Half strengh driver) ;V_OUT= V_TT- 0.45V

NOTE :

I_OH

-16.8

16.8

-9

I_OL

I_OH

I_OL

1. V

is expected to be equal to 0.5*V

of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on V

may not exceed +/-2% of the

REF

DDQ

REF

dc value.

2. V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to V and must track variations in the DC level

REF,

of V

REF,

3. V is the magnitude of the difference between the input level on CK and the input level on CK.

4. The ratio of the Pull-up current to the Pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to

source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between Pull-up and Pull-down drivers due to process variation. The full varia-

tion in the ratio of the maximum to minimum Pull-up and Pull-down current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.

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DDR SDRAM

12. DDR SDRAM Spec Items & Test Conditions

Conditions

Symbol

IDD0

Operating current - One bank Active-Precharge;

tRC=tRCmin; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;

DQ,DM and DQS inputs changing once per clock cycle;

address and control inputs changing once every two clock cycles.

Operating current - One bank operation ; One bank open, BL=4, Reads

- Refer to the following page for detailed test condition

IDD1

Precharge power-down standby current; All banks idle; power - down mode;

CKE = <V_IL(max); tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;

IDD2P

V_IN= V_REFfor DQ,DQS and DM.

Precharge Floating standby current; CS > =V_IH(min);All banks idle; CKE > = V_IH(min); tCK=10ns for DDR200,tCK=7.5ns for

DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs changing once per clock cycle; V_IN= V_REFfor

DQ,DQS and DM

IDD2F

IDD2Q

Precharge Quiet standby current; CS > = V_IH(min); All banks idle;

CKE > = V_IH(min); tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control

inputs stable at >= V_IH(min) or =<V_IL(max); V_IN= V_REFfor DQ ,DQS and DM

Active power - down standby current ; one bank active; power-down mode;

CKE=< V_IL(max); tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;

IDD3P

IDD3N

IDD4R

Vin = Vref for DQ,DQS and DM

Active standby current; CS >= V_IH(min); CKE>=V_IH(min);

one bank active; tRC=tRASmax; tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ, DQS and

DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle

Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing

once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2 at 7.5ns for DDR266, CL=2.5 at tCK=7.5ns for DDR266, tCK=6ns for

DDR333, CL=3 at tCK=5ns for DDR400; 50% of data changing on every transfer; lout = 0 m A

Operating current - burst write; Burst length = 2; writes; continuous burst;

One bank active address and control inputs changing once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2 at tCK=7.5ns

for DDR266, CL=2.5 at tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ, DM and DQS inputs changing twice per

clock cycle, 50% of input data changing at every burst

IDD4W

Auto refresh current; tRC = tRFC(min) which is 8*tCK for DDR200 at tCK=10ns; 10*tCK for DDR266 at tCK=7.5ns; 12*tCK for

DDR333 at tCK=6ns, 14*tCK for DDR400 at tCK=5ns; distributed refresh

IDD5

IDD6

Self refresh current; CKE =< 0.2V; External clock on; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for

DDR400.

Operating current - Four bank operation ; Four bank interleaving with BL=4

-Refer to the following page for detailed test condition

IDD7A

13. Input/Output Capacitance

( T_A= 25°C, f=100MHz)

Parameter

Symbol

Min

Max

DeltaCap(max)

Unit

NOTE

Input capacitance

(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)

C_IN1

0.5

C_IN2

C_OUT

C_IN3

Input capacitance( CK, CK )

0.25

0.5

Data & DQS input/output capacitance

1,2,3,4

Input capacitance(DM for x4/8, UDM/LDM for x16)

NOTE :

1.These values are guaranteed by design and are tested on a sample basis only.

2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.

This is required to match signal propagation times of DQ, DQS, and DM in the system.

3. Unused pins are tied to ground.

4. This parameteer is sampled. V

= +2.5V +0.2V, V = +2.5V+0.2V. For all devices, f=100MHz, tA=25°C, V

(DC) = V

/2,

DDQ

OUT

DDQ

(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level).

OUT

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datasheet

DDR SDRAM

14. Detailed test condition for DDR SDRAM IDD1 & IDD7A

IDD1 : Operating current: One bank operation

1. Typical Case: Vdd = 2.5V, T=25°C

Worst Case : Vdd = 2.7V, T=10°C

2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once

per clock cycle. lout = 0mA

3. Timing patterns

- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK

Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- A2 (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK

Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- B3(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC = 10*tCK, tRAS=7*tCK

Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK

Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing

*50% of data changing at every transfer

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT

IDD7A : Operating current: Four bank operation

1. Typical Case: V_DD= 2.5V, T=25°C

Worst Case : V_DD= 2.7V, T= 10°C

2. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not

changing. lout = 0mA

4. Timing patterns

- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 N A0 N A1 R0 - repeat the same timing with random address changing

*50% of data changing at every burst

- A2(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 N A0 N A1 R0 - repeat the same timing with random address changing

*50% of data changing at every burst

- B3(166Mhz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 N A0 N A1 R0 - repeat the same timing with random address changing

*50% of data changing at every burst

- CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 N A0 N A1 R0 - repeat the same timing with random address changing

*50% of data changing at every transfer

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT

- 12 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

15. DDR SDRAM IDD Spec Table

64Mx4 (K4H560438N)

Symbol

Unit NOTE

B3(DDR333@CL=2.5)

B0(DDR266@CL=2.5)

IDD0

IDD1

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

Normal

Low power

IDD7A

IDD6

1.5

105

1.5

32Mx8 (K4H560838N)

Symbol

Unit NOTE

CC(DDR400@CL=3)

B3(DDR333@CL=2.5)

IDD0

IDD1

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

Normal

Low power

IDD7A

IDD6

1.5

125

1.5

110

16Mx16 (K4H561638N)

Symbol

Unit NOTE

CC(DDR400@CL=3)

B3(DDR333@CL=2.5)

IDD0

IDD1

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

100

Normal

Low power

IDD7A

IDD6

1.5

140

1.5

120

- 13 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

16. AC Operating Conditions

Parameter/Condition

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

Input Differential Voltage, CK and CK inputs

Symbol

Min

Max

Unit

NOTE

V_IH(AC)

V_IL(AC)

V_ID(AC)

V_IX(AC)

V_REF+ 0.31

V_REF- 0.31

V_DDQ+0.6

0.7

0.5*V_DDQ-0.2

0.5*V_DDQ+0.2

Input Crossing Point Voltage, CK and CK inputs

NOTE :

1. V is the magnitude of the difference between the input level on CK and the input level on CK.

2. The value of V is expected to equal 0.5*V

of the transmitting device and must track variations in the dc level of the same.

DDQ

17. AC Overshoot/Undershoot specification for Address and Control Pins

Specification

Parameter

DDR400

1.5 V

DDR333

1.5 V

DDR200/266

1.5 V

Maximum peak amplitude allowed for overshoot

Maximum peak amplitude allowed for undershoot

1.5 V

The area between the overshoot signal and V_DDmust be less than or equal to

4.5 V-ns

The area between the undershoot signal and GND must be less than or equal to

Overshoot

Maximum Amplitude = 1.5V

Area

-1

-2

-3

-4

-5

Maximum Amplitude = 1.5V

GND

0.6875

0.5 1.0

1.5

2.5

3.5

4.5

5.5

6.3125

6.0 6.5

undershoot

7.0

2.0

3.0

4.0

5.0

Tims(ns)

Figure 3. AC overshoot/Undershoot Definition

- 14 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

18. Overshoot/Undershoot specification for Data, Strobe and Mask Pins

Specification

Parameter

DDR400

1.2 V

DDR333

1.2 V

DDR200/266

1.2 V

Maximum peak amplitude allowed for overshoot

Maximum peak amplitude allowed for undershoot

1.2 V

The area between the overshoot signal and V_DDmust be less than or equal to

2.4 V-ns

The area between the undershoot signal and GND must be less than or equal to

DDQ

Overshoot

Maximum Amplitude = 1.2V

Area

-1

-2

-3

-4

-5

Maximum Amplitude = 1.2V

GND

0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0

Tims(ns)

undershoot

Figure 4. DQ/DM/DQS AC overshoot/Undershoot Definition

- 15 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

19. AC Timing Parameters & Specifications

(DDR400@CL=3.0)

(DDR333@CL=2.5) (DDR266@CL=2.0)

(DDR266@CL=2.5)

Parameter

Symbol

Unit NOTE

Min

Max

Min

Max

Min

Max

Min

Max

Row cycle time

tRC

tRFC

tRAS

tRCD

tRP

tCK

Refresh row cycle time

Row active time

70K

120K

RAS to CAS delay

Row precharge time

Row active to Row active delay

Write recovery time

tRRD

tWR

Last data in to Read command

tWTR

CL=2.0

CL=2.5

CL=3.0

7.5

Clock cycle time

tCK

7.5

Clock high level width

tCH

tCL

0.45

-0.55

-0.65

0.55

+0.55

+0.65

0.4

0.45

-0.6

-0.7

0.55

+0.6

+0.7

0.45

1.1

0.45

-0.75

0.55

+0.75

0.5

0.45

-0.75

0.55

+0.75

0.5

tCK

Clock low level width

DQS-out access time from CK/CK

tDQSCK

tAC

Output data access time from CK/CK

Data strobe edge to ouput data edge

Read Preamble

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPRE

tDSS

tCK

0.9

0.4

0.72

1.1

0.9

0.4

0.75

0.9

0.4

0.75

1.1

0.9

0.4

0.75

1.1

Read Postamble

0.6

CK to valid DQS-in

1.28

1.25

DQS-in setup time

DQS-in hold time

0.25

0.2

0.35

0.6

0.25

0.2

0.35

0.75

0.25

0.2

0.35

0.9

0.25

0.2

0.35

0.9

tCK

DQS falling edge to CK rising-setup time

DQS falling edge from CK rising-hold time

DQS-in high level width

tDSH

tDQSH

tDQSL

tIS

DQS-in low level width

15, 17~19

Address and Control Input setup time(fast)

Address and Control Input hold time(fast)

tIH

Address and Control Input setup

time(slow)

tIS

0.7

0.8

1.0

16~19

Address and Control Input hold time(slow)

tIH

tHZ

0.7

-0.65

0.8

-0.7

1.0

-0.75

1.0

-0.75

tCK

16~19

Data-out high impedence time from CK/CK

Data-out low impedence time from CK/CK

Mode register set cycle time

+0.65

+0.7

+0.75

tLZ

tMRD

tDS

DQ & DM setup time to DQS

0.4

0.45

2.2

0.5

j, k

DQ & DM hold time to DQS

tDH

0.4

0.5

Control & Address input pulse width

DQ & DM input pulse width

tIPW

tDIPW

tXSNR

tXSRD

tREFI

2.2

1.75

Exit self refresh to non-Read command

Exit self refresh to read command

Refresh interval time

200

7.8

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

Output DQS valid window

Clock half period

tQH

tHP

tCLmin

or tCHmin

tCLmin

or tCHmin

tCLmin

or tCHmin

tCLmin

or tCHmin

20, 21

Data hold skew factor

tQHS

0.5

0.6

0.55

0.6

0.75

0.6

0.75

0.6

DQS write postamble time

tWPST

0.4

tCK

Active to Read with Auto precharge

command

tRAP

(tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK)

Autoprecharge write recovery +

Precharge time

tDAL

tCK

Power Down Exit Time

tPDEX

- 16 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

20. System Characteristics for DDR SDRAM

The following specification parameters are required in systems using DDR400 and DDR333 devices to ensure proper system performance. these char-

acteristics are for system simulation purposes and are guaranteed by design.

[ Table 1 ] Input Slew Rate for DQ, DQS, and DM

AC CHARACTERISTICS

PARAMETER

DDR400

DDR333

DDR266

SYMBOL

Units

NOTE

MIN

MAX

MIN

MAX

MIN

MAX

DQ/DM/DQS input slew rate measured between

DCSLEW

0.5

4.0

0.5

4.0

0.5

4.0

V/ns

a, l

_IH(DC), V_IL(DC) and V_IL(DC), V_IH(DC)

[ Table 2 ] Input Setup & Hold Time Derating for Slew Rate

Input Slew Rate

0.5 V/ns

ΔtIS

ΔtIH

Units

NOTE

0.4 V/ns

+50

+100

0.3 V/ns

[ Table 3 ] Input/Output Setup & Hold Time Derating for Slew Rate

Input Slew Rate

0.5 V/ns

ΔtDS

ΔtDH

Units

NOTE

0.4 V/ns

+75

+150

+75

+150

0.3 V/ns

[ Table 4 ] Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate

Delta Slew Rate

+/- 0.0 V/ns

ΔtDS

ΔtDH

Units

NOTE

+/- 0.25 V/ns

+/- 0.5 V/ns

+50

+100

+50

+100

[ Table 5 ] Output Slew Rate Characteristice (X4, X8 Devices only)

Typical Range

Minimum

(V/ns)

Maximum

(V/ns)

Slew Rate Characteristic

(V/ns)

NOTE

Pull-up Slew Rate

Pull-down slew

1.2 ~ 2.5

1.0

4.5

a,c,d,f,g,h

b,c,d,f,g,h

1.0

[ Table 6 ] Output Slew Rate Characteristice (X16 Devices only)

Typical Range

Minimum

(V/ns)

Maximum

(V/ns)

Slew Rate Characteristic

(V/ns)

NOTE

Pull-up Slew Rate

Pull-down slew

1.2 ~ 2.5

0.7

5.0

a,c,d,f,g,h

b,c,d,f,g,h

[ Table 7 ] Output Slew Rate Matching Ratio Characteristics

AC CHARACTERISTICS

DDR400

DDR333

DDR266

NOTE

e, l

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

Output Slew Rate Matching Ratio (Pullup to Pulldown)

0.67

1.5

0.67

1.5

0.67

1.5

- 17 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

21. Component Notes

1. All voltages referenced to V_SS

2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related speci-

fications and device operation are guaranteed for the full voltage range specified.

3. Figure 5 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise rep-

resentation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or

other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions

(generally a coaxial transmission line terminated at the tester electronics).

V_TT

50Ω

Output

(Vout)

30pF

Figure 5. Timing Reference Load

4. AC timing and IDD tests may use a V_ILto V_IHswing of up to 1.5 V in the test environment, but input timing is still referenced to V_REF(or to the crossing

point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew rate

for the input signals is 1 V/ns in the range between V_IL(AC) and V_IH(AC).

5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing

the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level.

6. Inputs are not recognized as valid until V_REFstabilizes. Exception: during the period before V_REFstabilizes, CKE ℜ≤ 0.2V_DDQis recognized as LOW.

7. Enables on.chip refresh and address counters.

8. IDD specifications are tested after the device is properly initialized.

9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other

than CK/CK, is V_REF

10. The output timing reference voltage level is V_TT

11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage

level but specify when the device output is no longer driving (HZ), or begins driving (LZ).

12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance

(bus turnaround) will degrade accordingly.

13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. Avalid transition is

defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, DQS will

be transitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this

time, depending on tDQSS.

14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

15. For command/address input slew rate ℜ≥ 1.0 V/ns

16. For command/address input slew rate ℜ≥ 0.5 V/ns and < 1.0 V/ns

17. For CK & CK slew rate ℜ≥ 1.0 V/ns

18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester

correlation.

19. Slew Rate is measured between VOH(AC) and VOL(AC).

- 18 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater

than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of

the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.

21. tQH = tHP - tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration dis-

tortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transi-

tion, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.

22. tDQSQ

Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.

23. tDAL = (tWR/tCK) + (tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR400 at CL=3 and tCK=5ns tDAL = (15 ns /

5 ns) + (15 ns/ 5ns) = (3) + (3) tDAL = 6 clocks

- 19 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

22. System Notes

a. Pull-up slew rate is characteristized under the test conditions as shown in Figure 6.

Test point

Output

50Ω

V_SSQ

Figure 6. Pull-up slew rate test load

b. Pull-down slew rate is measured under the test conditions shown in Figure 7.

V_DDQ

50Ω

Output

Test point

Figure 7. Pull-down slew rate test load

c. Pull-up slew rate is measured between (V_DDQ/2 - 320 mV +/- 250 mV)

Pull-down slew rate is measured between (V_DDQ/2 + 320 mV +/- 250 mV)

Pull-up and Pull-down slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output

switching.

Example : For typical slew rate, DQ0 is switching

For minmum slew rate, all DQ bits are switching from either high to low, or low to high.

The remaining DQ bits remain the same as for previous state.

d. Evaluation conditions

Typical : 25 °C (T Ambient), V_DDQ= 2.5V, typical process

Minimum : 70 °C (T Ambient), V_DDQ= 2.3V, slow - slow process

Maximum : 0 °C (T Ambient), V_DDQ= 2.7V, fast - fast process

e. The ratio of Pull-up slew rate to Pull-down slew rate is specified for the same temperature and voltage, over the entire temperature

and voltage range. For a given output, it represents the maximum difference between Pull-up and Pull-down drivers due to process

variation.

f. Verified under typical conditions for qualification purposes.

g. TSOPII package divices only.

h. Only intended for operation up to 400 Mbps per pin.

i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns

as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either V_IH(AC) to V_IL(AC) or

V_IH(DC) to V_IL(DC), similarly for rising transitions.

j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.

Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the

slew rates determined by either V_IH(AC) to V_IL(AC) or V_IH(DC) to V_IL(DC), similarly for rising transitions.

The delta rise/fall rate is calculated as:

{1/(Slew Rate1)} - {1/(Slew Rate2)}

For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this

would result in the need for an increase in tDS and tDH of 100 ps.

k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser

on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter

mined by either V_IH(AC) to V_IL(AC) or V_IH(DC) to V_IL(DC), and similarly for rising transitions.

l. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi

tions through the DC region must be monotonic.

- 20 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

23. IBIS : I/V Characteristics for Input and Output Buffers

DDR SDRAM Output Driver V-I Characteristics

DDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1.

Figures 4, 5 and 6 show the driver characteristics graphically, and tables 8, 9 and 10 show the same data in tabular format suitable for

input into simulation tools. The driver characteristcs evaluation conditions are:

Typical

Minimum

Maximum

25xC

70xC

0xC

V_DD/V_DDQ= 2.5V, typical process

V_DD/V_DDQ= 2.3V, slow-slow process

V_DD/V_DDQ= 2.7V, fast-fast process

Output Driver Characteristic Curves Notes:

1. The full variation in driver current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I

curve of Figures 4, 5 and 6.

2. It is recommended that the "typical" IBIS V-I curve lie within the inner bounding lines of the V-I curves of Figures 4, 5 and 6.

3. The full variation in the ratio of the "typical" IBIS Pull-up to "typical" IBIS Pull-down current should be unity +/- 10%, for device drain to source voltages

from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed.

160

Maximum

140

120

100

Typical High

Typical Low

Minimum

0.0

0.5

1.0

1.5

2.0

2.5

Vout(V)

Pull-down Characteristics for Full Strength Output Driver

0.0

1.0

2.0

-20

-40

Minumum

-60

Typical Low

-80

-100

-120

-140

-160

-180

-200

-220

Typical High

Maximum

Pull-up Characteristics for Full Strength Output Driver

Vout(V)

Figure 8. I/V characteristics for input/output buffers : Pull-down(above) and Pull-up(below)

- 21 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

[ Table 8 ] Full Strength Driver Characteristics

Pull-down Current (mA)

Pull-up Current (mA)

Voltage

(V)

Typical

Low

Typical

High

Typical

Low

Typical

High

Minimum

Maximum

Minimum

Maximum

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

6.0

6.8

13.5

20.1

26.6

33.0

39.1

44.2

49.8

55.2

60.3

65.2

69.9

74.2

78.4

82.3

85.9

89.1

92.2

95.3

97.2

99.1

100.9

101.9

102.8

103.8

104.6

105.4

4.6

9.6

-6.1

-7.6

-4.6

-10.0

-20.0

12.2

18.1

24.1

29.8

34.6

39.4

43.7

47.5

51.3

54.1

56.2

57.9

59.3

60.1

60.5

61.0

61.5

62.0

62.5

62.9

63.3

63.8

64.1

64.6

64.8

65.0

9.2

18.2

-12.2

-18.1

-24.0

-29.8

-34.3

-38.1

-41.1

-41.8

-46.0

-47.8

-49.2

-50.0

-50.5

-50.7

-51.0

-51.1

-51.3

-51.5

-51.6

-51.8

-52.0

-52.2

-52.3

-52.5

-52.7

-52.8

-14.5

-9.2

13.8

18.4

23.0

27.7

32.2

36.8

39.6

42.6

44.8

46.2

47.1

47.4

47.7

48.0

48.4

48.9

49.1

49.4

49.6

49.8

49.9

50.0

50.2

50.4

50.5

26.0

-21.2

-13.8

-18.4

-23.0

-27.7

-32.2

-36.0

-38.2

-38.7

-39.0

-39.2

-39.4

-39.6

-39.9

-40.1

-40.2

-40.3

-40.4

-40.5

-40.6

-40.7

-40.8

-40.9

-41.0

-41.1

-41.2

-29.8

33.9

-27.7

-38.8

41.8

-34.1

-46.8

49.4

-40.5

-54.4

56.8

-46.9

-61.8

63.2

-53.1

-69.5

69.9

-59.4

-77.3

76.3

-65.5

-85.2

82.5

-71.6

-93.0

88.3

-77.6

-100.6

-108.1

-115.5

-123.0

-130.4

-136.7

-144.2

-150.5

-156.9

-163.2

-169.6

-176.0

-181.3

-187.6

-192.9

-198.2

93.8

-83.6

99.1

-89.7

103.8

108.4

112.1

115.9

119.6

123.3

126.5

129.5

132.4

135.0

137.3

139.2

140.8

-95.5

-101.3

-107.1

-112.4

-118.7

-124.0

-129.3

-134.6

-139.9

-145.2

-150.5

-155.3

-160.1

- 22 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

Maximum

Typical High

Typical Low

Minimum

0.0

1.0

2.0

Pull-down Characteristics for Weak Output Driver

Vout(V)

0.0

1.0

2.0

-10

-20

-30

-40

-50

-60

-70

-80

-90

Minumum

Typical Low

Typical High

Maximum

Vout(V)

Pull-up Characteristics for Weak Output Driver

Figure 9. I/V characteristics for input/output buffers : Pull-down(above) and Pull-up(below)

- 23 -

Rev. 1.01

K4H560438N

K4H560838N

K4H561638N

datasheet

DDR SDRAM

[ Table 9 ] Weak Driver Characteristics

Pull-down Current (mA)

Pull-up Current (mA)

Voltage

(V)

Typical

Low

Typical

High

Typical

Low

Typical

High

Minimum

Maximum

Minimum

Maximum

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

3.4

3.8

2.6

5.0

-3.5

-4.3

-2.6

-5.0

6.9

7.6

5.2

9.9

-6.9

-8.2

-5.2

-9.9

10.3

13.6

16.9

19.6

22.3

24.7

26.9

29.0

30.6

31.8

32.8

33.5

34.0

34.3

34.5

34.8

35.1

35.4

35.6

35.8

36.1

36.3

36.5

36.7

36.8

11.4

15.1

18.7

22.1

25.0

28.2

31.3

34.1

36.9

39.5

42.0

44.4

46.6

48.6

50.5

52.2

53.9

55.0

56.1

57.1

57.7

58.2

58.7

59.2

59.6

7.8

14.6

19.2

23.6

28.0

32.2

35.8

39.5

43.2

46.7

50.0

53.1

56.1

58.7

61.4

63.5

65.6

67.7

69.8

71.6

73.3

74.9

76.4

77.7

78.8

79.7

-10.3

-13.6

-16.9

-19.4

-21.5

-23.3

-24.8

-26.0

-27.1

-27.8

-28.3

-28.6

-28.7

-28.9

-29.0

-29.2

-29.3

-29.5

-29.6

-29.7

-29.8

-29.9

-12.0

-15.7

-19.3

-22.9

-26.5

-30.1

-33.6

-37.1

-40.3

-43.1

-45.8

-48.4

-50.7

-52.9

-55.0

-56.8

-58.7

-60.0

-61.2

-62.4

-63.1

-63.8

-64.4

-65.1

-65.8

-7.8

-14.6

-19.2

-23.6

-28.0

-32.2

-35.8

-39.5

-43.2

-46.7

-50.0

-53.1

-56.1

-58.7

-61.4

-63.5

-65.6

-67.7

-69.8

-71.6

-73.3

-74.9

-76.4

-77.7

-78.8

-79.7

10.4

13.0

15.7

18.2

20.8

22.4

24.1

25.4

26.2

26.6

26.8

27.0

27.2

27.4

27.7

27.8

28.0

28.1

28.2

28.3

28.4

28.5

28.6

-10.4

-13.0

-15.7

-18.2

-20.4

-21.6

-21.9

-22.1

-22.2

-22.3

-22.4

-22.6

-22.7

-22.8

-22.9

-23.0

-23.1

-23.2

-23.3

- 24 -

K4H560438N-LLB3 [SAMSUNG]

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