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K4H561638D-GCA20 [SAMSUNG]

DDR DRAM, 16MX16, 0.75ns, CMOS, PBGA60, FBGA-60;
K4H561638D-GCA20
型号： K4H561638D-GCA20
厂家： SAMSUNG    SAMSUNG
描述：

DDR DRAM, 16MX16, 0.75ns, CMOS, PBGA60, FBGA-60

动态存储器 双倍数据速率 内存集成电路
文件： 总26页 (文件大小：291K)
中文：  中文翻译
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256Mb  
DDR SDRAM  
Key Features  
• Double-data-rate architecture; two data transfers per clock cycle  
• Bidirectional data strobe(DQS)  
• Four banks operation  
• Differential clock inputs(CK and CK)  
• DLL aligns DQ and DQS transition with CK transition  
• MRS cycle with address key programs  
-. Read latency 2, 2.5 (clock)  
-. Burst length (2, 4, 8)  
-. Burst type (sequential & interleave)  
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)  
• Data I/O transactions on both edges of data strobe  
• Edge aligned data output, center aligned data input  
• LDM,UDM/DM for write masking only  
• Auto & Self refresh  
• 7.8us refresh interval(8K/64ms refresh)  
• Maximum burst refresh cycle : 8  
• 60 Ball FBGA package  
ORDERING INFORMATION  
Part No.  
Org.  
Max Freq.  
Interface  
Package  
K4H560438D-GC(L)B3  
K4H560438D-GC(L)A2  
K4H560438D-GC(L)B0  
K4H560838D-GC(L)B3  
K4H560838D-GC(L)A2  
K4H560838D-GC(L)B0  
K4H561638D-GC(L)B3  
K4H561638D-GC(L)A2  
K4H561638D-GC(L)B0  
B3(DDR333@CL=2.5)  
A2(DDR266@CL=2)  
B0(DDR266@CL=2.5)  
B3(DDR333@CL=2.5)  
A2(DDR266@CL=2)  
B0(DDR266@CL=2.5)  
B3(DDR333@CL=2.5)  
A2(DDR266@CL=2)  
B0(DDR266@CL=2.5)  
64M x 4  
SSTL2  
60 ball FBGA  
32M x 8  
SSTL2  
SSTL2  
60 ball FBGA  
60 ball FBGA  
16M x 16  
Operating Frequencies  
- B3(DDR333)  
133MHz  
- A2(DDR266A)  
- B0(DDR266B)  
100MHz  
Speed @CL2  
133MHz  
133MHz  
Speed @CL2.5  
166MHz  
133MHz  
*CL : Cas Latency  
Rev. 2.2 Mar. ’03  
- 1 -  
256Mb  
DDR SDRAM  
Package Dimension  
8.00  
± 0.10  
0.80 x 8 = 6.40  
ENCAPSULANT AREA  
0.80 x 4 = 3.20  
0.80 x 2 = 1.60  
0.80 x 2 = 1.60  
8.0 0± 0.10  
9
8
7
6
5
4
3
2
1
0.80  
A
B
C
D
E
F
G
H
J
K
L
M
(0.90)  
(0.90)  
0.35  
± 0.05  
60 - 0.45  
±
0.05  
π
(1.80)  
TOP VIEW  
1.10± 0.10  
BOTTOM VIEW  
Organization  
64Mx4  
Column Address  
A0-A9, A11  
A0-A9  
32Mx8  
16Mx16  
A0-A8  
DM is internally loaded to match DQ and DQS identically.  
Column address configuration  
Rev. 2.2 Mar. ’03  
- 2 -  
K4H561638D  
DDR SDRAM  
Pin configuration  
64M x 4  
60Ball CSP  
A
B
C
D
E
F
G
H
J
K
L
M
1
2
3
7
8
9
VSSQ  
NC  
NC  
NC  
NC  
NC  
VREF  
VSS  
DM  
VDDQ VSSQ VDDQ VSSQ  
CK  
CK  
A12  
CKE  
RAS  
CS  
A11  
A9  
A8  
A7  
A6  
A5  
A2  
A1  
A4  
VSS  
VDD  
A3  
VSS  
VDD  
NC  
DQ3  
DQ0  
NC  
NC  
DQ2  
DQ1  
DQS  
NC  
NC  
WE  
CAS  
BA1  
BA0  
A0  
VSSQ VDDQ VSSQ VDDQ VDD  
A10  
VDDQ  
NC  
NC  
NC  
NC  
NC  
32M x 8  
60Ball CSP  
A
B
C
D
E
F
G
H
J
K
L
M
1
2
3
7
8
9
VSSQ  
NC  
NC  
NC  
NC  
VREF  
VSS  
DM  
DQ7  
VSS  
VDDQ VSSQ VDDQ VSSQ  
CK  
CK  
A12  
CKE  
RAS  
CS  
A11  
A9  
A8  
A7  
A6  
A5  
A2  
A1  
A4  
VSS  
VDD  
A3  
DQ6  
DQ1  
DQ5  
DQ2  
DQ4  
DQ3  
DQS  
NC  
VDD  
DQ0  
NC  
WE  
CAS  
BA1  
BA0  
A0  
VSSQ VDDQ VSSQ VDDQ VDD  
A10  
VDDQ  
NC  
NC  
NC  
NC  
NC  
16M x 16  
60Ball CSP  
F
A
B
C
D
E
G
H
J
K
L
M
1
2
3
7
8
9
VSSQ DQ14 DQ12 DQ10  
DQ8  
VREF  
VSS  
DQ15 VDDQ VSSQ VDDQ VSSQ  
CK  
CK  
A12  
CKE  
RAS  
CS  
A11  
A9  
A8  
A7  
A6  
A5  
A2  
A1  
A4  
VSS  
VDD  
A3  
VSS  
VDD  
DQ13 DQ11  
DQ2 DQ4  
DQ9  
DQ6  
UDQS UDM  
LDQS LDM  
WE  
CAS  
BA1  
BA0  
A0  
DQ0  
VSSQ VDDQ VSSQ VDDQ VDD  
DQ1 DQ3 DQ5 DQ7 NC  
A10  
VDDQ  
Pin Name  
CLK  
Pin Function  
System Clock  
Chip Select  
CS  
CKE  
Clock Enable  
A0 ~ A12  
BA0 ~ BA1  
RAS  
Address  
Bank Select Address  
Row Address Strobe  
CAS  
Column Address Strobe  
Write Enable  
WE  
L(U)DQM  
DQ0 ~ 15  
VDD/VSS  
VDDQ/VSSQ  
Data Input/Output Mask  
Data Input/Output  
Power Supply/Ground  
Data Output Power/Ground  
Rev. 2.2 Mar. ’03  
- 3 -  
256Mb  
DDR SDRAM  
Block Diagram (16Mbit x 4 I/O x 4 Banks)  
WE  
4
DM  
CK, CK  
Data Input Register  
Serial to parallel  
Bank Select  
8
8Mx8  
8Mx8  
8Mx8  
8Mx8  
8
4
x4  
DQi  
CK, CK  
ADD  
Column Decoder  
Latency & Burst Length  
Data Strobe  
Programming Register  
LWCBR  
LCKE  
LRAS LCBR  
LWE  
LCAS  
CK, CK  
Timing Register  
CK, CK  
CKE  
CS  
RAS  
CAS  
WE  
Rev. 2.2 Mar. ’03  
- 4 -  
256Mb  
DDR SDRAM  
Block Diagram (8Mbit x 8 I/O x 4 Banks)  
WE  
8
DM  
CK, CK  
Data Input Register  
Serial to parallel  
Bank Select  
16  
4Mx16  
4Mx16  
4Mx16  
4Mx16  
16  
8
x8  
DQi  
CK, CK  
ADD  
Column Decoder  
Latency & Burst Length  
Data Strobe  
Programming Register  
LWCBR  
LCKE  
LRAS LCBR  
LWE  
LCAS  
CK, CK  
Timing Register  
CK, CK  
CKE  
CS  
RAS  
CAS  
WE  
Rev. 2.2 Mar. ’03  
- 5 -  
256Mb  
DDR SDRAM  
Block Diagram (4Mbit x 16 I/O x 4 Banks)  
LWE  
16  
LDM  
CK, CK  
Data Input Register  
Serial to parallel  
Bank Select  
32  
2Mx32  
2Mx32  
2Mx32  
2Mx32  
32  
16  
x16  
DQi  
ADD  
Column Decoder  
Latency & Burst Length  
Data Strobe  
Programming Register  
LWCBR  
LCKE  
LRAS LCBR  
LWE  
LCAS  
CK, CK  
Timing Register  
CK, CK  
CKE  
CS  
RAS  
CAS  
WE  
Rev. 2.2 Mar. ’03  
- 6 -  
256Mb  
DDR SDRAM  
Input/Output Function Description  
SYMBOL  
TYPE  
DESCRIPTION  
CK, CK  
Input  
Clock : CK and CK are differential clock inputs. All address and control input signals are sam-  
pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to  
both edges of CK. Internal clock signals are derived from CK/CK.  
CKE  
Input  
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and  
device input buffers and output drivers. Deactivating the clock provides PRECHARGE  
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN  
(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,  
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled  
during power-down and self refresh modes, providing low standby power. CKE will recognize  
an LVCMOS LOW level prior to VREF being stable on power-up.  
CS  
Input  
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command  
decoder. All commands are masked when CS is registered HIGH. CS provides for external  
bank selection on systems with multiple banks. CS is considered part of the command code.  
RAS, CAS, WE  
LDM,(U)DM  
Input  
Input  
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.  
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is  
sampled HIGH along with that input data during a WRITE access. DM is sampled on both  
edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-  
ing. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on  
DQ8-DQ15.  
BA0, BA1  
A [n : 0]  
Input  
Input  
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-  
CHARGE command is being applied.  
Address Inputs : Provide the row address for ACTIVE commands, and the column address  
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the  
memory array in the respective bank. A10 is sampled during a PRECHARGE command to  
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10  
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address  
inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1  
define which mode register is loaded during the MODE REGISTER SET command (MRS or  
EMRS).  
DQ  
I/O  
I/O  
Data Input/Output : Data bus  
LDQS,(U)DQS  
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-  
tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on  
DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15.  
NC  
-
No Connect : No internal electrical connection is present.  
DQ Power Supply : +2.5V ± 0.2V.  
DQ Ground.  
VDDQ  
VSSQ  
VDD  
Supply  
Supply  
Supply  
Supply  
Input  
Power Supply : +2.5V ± 0.2V (device specific).  
Ground.  
VSS  
VREF  
SSTL_2 reference voltage.  
Rev. 2.2 Mar. ’03  
- 7 -  
256Mb  
DDR SDRAM  
Command Truth Table  
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)  
A11,A12  
A9 ~ A0  
CKEn-1  
CKEn  
CS  
RAS  
CAS  
WE  
BA0,1  
A10/AP  
Note  
COMMAND  
Extended MRS  
Register  
Register  
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE  
OP CODE  
1, 2  
1, 2  
3
Mode Register Set  
Auto Refresh  
H
L
L
L
H
X
X
Entry  
3
Refresh  
Self  
Refresh  
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit  
L
H
H
H
X
X
3
Bank Active & Row Address  
V
V
Row Address  
L
Read &  
Auto Precharge Disable  
Auto Precharge Enable  
Auto Precharge Disable  
Auto Precharge Enable  
4
4
Column  
L
H
L
H
Column Address  
Address  
H
L
Write &  
4
Column  
Address  
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
Column Address  
H
4, 6  
7
Burst Stop  
Precharge  
X
Bank Selection  
All Banks  
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry  
Exit  
H
L
L
H
L
Active Power Down  
X
X
X
H
L
Entry  
H
Precharge Power Down Mode  
H
L
Exit  
L
H
H
H
X
DM  
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined  
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)  
2.EMRS/ MRS can be issued only at all banks precharge state.  
A new command can be issued 2 clock cycles after EMRS or MRS.  
3. Auto refresh functions are same as the CBR refresh of DRAM.  
The automatical precharge without row precharge command is meant by "Auto".  
Auto/self refresh can be issued only at all banks precharge state.  
4. BA0 ~ BA1 : Bank select addresses.  
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.  
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.  
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.  
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.  
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.  
6. During burst write with auto precharge, new read/write command can not be issued.  
Another bank read/write command can be issued after the end of burst.  
New row active of the associated bank can be issued at tRP after the end of burst.  
7. Burst stop command is valid at every burst length.  
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).  
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.  
Rev. 2.2 Mar. ’03  
- 8 -  
K4H560438D  
DDR SDRAM  
16M x 4Bit x 4 Banks Double Data Rate SDRAM  
GENERAL DESCRIPTION  
The K4H560438D is 268,435,456 bits of double data rate synchronous DRAM organized as 4 x 16,777,216 words by 4 bits, fabricated  
with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to  
333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and  
programmable latencies allow the device to be useful for a variety of high performance memory system applications.  
Absolute Maximum Rating  
Parameter  
Voltage on any pin relative to VSS  
Voltage on VDD & VDDQ supply relative to VSS  
Storage temperature  
Symbol  
VIN, VOUT  
VDD, VDDQ  
TSTG  
Value  
-0.5 ~ 3.6  
-1.0 ~ 3.6  
-55 ~ +150  
1.5  
Unit  
V
V
°C  
W
Power dissipation  
PD  
Short circuit current  
IOS  
50  
mA  
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.  
Functional operation should be restricted to recommend operation condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability  
DC Operating Conditions  
Recommended operating conditions(Voltage referenced to VSS=0V, TA= 0 to 70°C)  
Parameter  
Supply voltage(for device with a nominal VDD of 2.5V)  
I/O Supply voltage  
Symbol  
VDD  
Min  
2.3  
Max  
2.7  
Unit  
Note  
VDDQ  
VREF  
2.3  
2.7  
V
V
I/O Reference voltage  
VDDQ/2-50mV VDDQ/2+50mV  
1
2
4
4
I/O Termination voltage(system)  
Input logic high voltage  
V
VREF-0.04  
VREF+0.15  
-0.3  
VREF+0.04  
VDDQ+0.3  
VREF-0.15  
VDDQ+0.3  
VDDQ+0.6  
1.35  
V
TT  
VIH(DC)  
VIL(DC)  
VIN(DC)  
VID(DC)  
VIX(DC)  
II  
V
Input logic low voltage  
V
Input Voltage Level, CK and CK inputs  
Input Differential Voltage, CK and CK inputs  
Input crossing point voltage, CK and CK inputs  
Input leakage current  
-0.3  
V
0.3  
V
3
5
1.15  
V
-2  
2
uA  
uA  
Output leakage current  
IOZ  
-5  
5
Output High Current(Normal strengh driver)  
IOH  
IOL  
IOH  
IOL  
-16.8  
16.8  
-9  
mA  
mA  
mA  
mA  
;V  
= V + 0.84V  
OUT  
TT  
Output High Current(Normal strengh driver)  
;V = V - 0.84V  
OUT  
TT  
Output High Current(Half strengh driver)  
;V = V + 0.45V  
OUT  
TT  
Output High Current(Half strengh driver)  
;V = V - 0.45V  
9
OUT  
TT  
Rev. 2.2 Mar. ’03  
- 9 -  
K4H560438D  
DDR SDRAM  
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on  
VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise  
coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.  
2. V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to  
TT  
TT  
VREF, and must track variations in the DC level of VREF  
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.  
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in  
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.  
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.  
DDR SDRAM IDD spec table  
(VDD=2.7V, T = 10°C)  
64Mx4  
Symbol  
Unit  
Notes  
K4H560438D-GC(L)B3  
(DDR333)  
K4H560438D-GC(L)A2,B0  
(DDR266A/B)  
IDD0  
IDD1  
90  
110  
3
80  
100  
3
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2F  
IDD2Q  
IDD3P  
IDD3N  
IDD4R  
IDD4W  
IDD5  
25  
20  
20  
18  
35  
30  
55  
45  
150  
160  
180  
3
120  
135  
165  
3
IDD6  
Normal  
Low power  
1.5  
290  
1.5  
250  
Optional  
IDD7A  
AC Operating Conditions  
Max  
Parameter/Condition  
Symbol  
Min  
Unit  
Note  
Input High (Logic 1) Voltage, DQ, DQS and DM signals  
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.  
Input Differential Voltage, CK and CK inputs  
VIH(AC)  
VIL(AC)  
VID(AC)  
VREF + 0.31  
V
V
V
V
3
3
1
2
VREF - 0.31  
VDDQ+0.6  
0.7  
Input Crossing Point Voltage, CK and CK inputs  
VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2  
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.  
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.  
IX  
DDQ  
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu  
lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.  
Overshoot/Undershoot specification  
Specification  
Parameter  
Address &  
Control pins  
Data pins  
Maximum peak amplitude allowed for overshoot  
1.6 V  
1.6 V  
1.2V  
1.2V  
Maximum peak amplitude allowed for undershoot  
The area between the overshoot signal and VDD must be less than or equal to  
The area between the undershoot signal and GND must be less than or equal to  
4.5 V-ns  
4.5 V-ns  
2.5 V-ns  
2.5 V-ns  
Rev. 2.2 Mar. ’03  
- 10 -  
K4H560438D  
DDR SDRAM  
AC Timming Parameters & Specifications  
B3  
(DDR333)  
A2  
B0  
(DDR266B)  
(DDR266A)  
Parameter  
Symbol  
Unit  
Note  
Min  
Max  
Min  
Max  
Min  
Max  
Row cycle time  
tRC  
tRFC  
tRAS  
tRCD  
tRP  
60  
72  
65  
75  
65  
75  
ns  
ns  
Refresh row cycle time  
Row active time  
42  
70K  
45  
120K  
45  
120K  
ns  
RAS to CAS delay  
18  
20  
20  
ns  
Row precharge time  
18  
20  
20  
ns  
Row active to Row active delay  
Write recovery time  
tRRD  
tWR  
12  
15  
15  
ns  
15  
15  
15  
ns  
Last data in to Read command  
Col. address to Col. address delay  
tWTR  
tCCD  
1
1
1
tCK  
tCK  
ns  
1
1
1
CL=2.0  
CL=2.5  
7.5  
6
12  
12  
7.5  
7.5  
0.45  
0.45  
-0.75  
-0.75  
-
12  
12  
10  
12  
12  
5
5
Clock cycle time  
tCK  
7.5  
0.45  
0.45  
-0.75  
-0.75  
-
ns  
Clock high level width  
tCH  
tCL  
0.45  
0.45  
-0.6  
-0.7  
-
0.55  
0.55  
+0.6  
+0.7  
0.4  
0.55  
0.55  
+0.75  
+0.75  
0.5  
0.55  
0.55  
+0.75  
+0.75  
0.5  
tCK  
tCK  
ns  
Clock low level width  
DQS-out access time from CK/CK  
tDQSCK  
tAC  
Output data access time from CK/CK  
Data strobe edge to ouput data edge  
Read Preamble  
ns  
tDQSQ  
tRPRE  
tRPST  
tDQSS  
tWPRES  
tWPRE  
tDSS  
tDSH  
tDQSH  
tDQSL  
tDSC  
tIS  
ns  
5
2
0.9  
0.4  
0.75  
0
1.1  
0.9  
0.4  
0.75  
0
1.1  
0.9  
0.4  
0.75  
0
1.1  
tCK  
tCK  
tCK  
ns  
Read Postamble  
0.6  
0.6  
0.6  
CK to valid DQS-in  
1.25  
1.25  
1.25  
DQS-in setup time  
DQS-in hold time  
0.25  
0.2  
0.2  
0.35  
0.35  
0.9  
0.75  
0.75  
0.8  
0.8  
-0.7  
-0.7  
0.5  
0.5  
1.0  
0.67  
0.25  
0.2  
0.2  
0.35  
0.35  
0.9  
0.9  
0.9  
1.0  
1.0  
-0.75  
-0.75  
0.5  
0.5  
1.0  
0.67  
0.25  
0.2  
0.2  
0.35  
0.35  
0.9  
0.9  
0.9  
1.0  
1.0  
-0.75  
-0.75  
0.5  
0.5  
1.0  
0.67  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
DQS falling edge to CK rising-setup time  
DQS falling edge from CK rising-hold time  
DQS-in high level width  
DQS-in low level width  
DQS-in cycle time  
1.1  
1.1  
1.1  
Address and Control Input setup time(fast)  
Address and Control Input hold time(fast)  
Address and Control Input setup time(slow)  
Address and Control Input hold time(slow)  
Data-out high impedence time from CK/CK  
Data-out low impedence time from CK/CK  
Input Slew Rate(for input only pins)  
Input Slew Rate(for I/O pins)  
Output Slew Rate(x4,x8)  
6
6
6
6
tIH  
ns  
tIS  
ns  
tIH  
ns  
tHZ  
+0.7  
+0.7  
+0.75  
+0.75  
+0.75  
+0.75  
ns  
tLZ  
ns  
tSL(I)  
tSL(IO)  
tSL(O)  
V/ns  
V/ns  
V/ns  
6
7
4.5  
1.5  
4.5  
1.5  
4.5  
1.5  
10  
Output Slew Rate Matching Ratio(rise to fall) tSLMR  
Rev. 2.2 Mar. ’03  
- 11 -  
K4H560438D  
DDR SDRAM  
-GC(L)B3  
(DDR333)  
-GC(L)A2  
(DDR266A)  
-GC(L)B0  
(DDR266B)  
Parameter  
Symbol  
Unit Note  
Min  
Max  
Min  
Max  
Min Max  
Mode register set cycle time  
DQ & DM setup time to DQS  
DQ & DM hold time to DQS  
tMRD  
tDS  
12  
15  
15  
ns  
0.45  
0.5  
0.5  
ns  
ns  
7,8,9  
7,8,9  
tDH  
0.45  
0.5  
0.5  
Control & Address input pulse width  
DQ & DM input pulse width  
Power down exit time  
tIPW  
2.2  
1.75  
6
2.2  
1.75  
7.5  
2.2  
1.75  
7.5  
ns  
ns  
tDIPW  
tPDEX  
tXSNR  
tXSRD  
tREFI  
ns  
Exit self refresh to non-Read command  
Exit self refresh to read command  
Refresh interval time  
75  
75  
75  
ns  
4
200  
7.8  
200  
7.8  
200  
7.8  
tCK  
us  
1
5
tHP  
-tQHS  
tHP  
-tQHS  
tHP  
-tQHS  
Output DQS valid window  
Clock half period  
tQH  
tHP  
-
-
-
-
-
-
ns  
ns  
tCLmin  
or tCHmin  
tCLmin  
or tCHmin  
tCLmin  
or tCHmin  
Data hold skew factor  
tQHS  
0.5  
0.6  
0.75  
0.6  
0.75  
0.6  
ns  
DQS write postamble time  
tWPST  
0.4  
18  
0.4  
20  
0.4  
20  
tCK  
3
Active to Read with Auto precharge  
command  
tRAP  
Autoprecharge write recovery +  
Precharge time  
(tWR/tCK)  
+
(tWR/tCK)  
+
(tWR/tCK)  
+
tDAL  
tCK  
11  
(tRP/tCK)  
(tRP/tCK)  
(tRP/tCK)  
1. Maximum burst refresh cycle : 8  
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from  
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,  
DQS could be High at this time, depending on tDQSS.  
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,  
but system performance (bus turnaround) will degrade accordingly.  
4. A write command can be applied with tRCD satisfied after this command.  
5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period  
jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.  
6. Input Setup/Hold Slew Rate Derating  
Input Setup/Hold Slew Rate  
∆tIS  
(ps)  
0
∆tIH  
(ps)  
0
(V/ns)  
0.5  
0.4  
+50  
+100  
+50  
+100  
0.3  
This derating table is used to increase t /t in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate  
IS IH  
based on the lesser of AC-AC slew rate and DC-DC slew rate.  
7. I/O Setup/Hold Slew Rate Derating  
I/O Setup/Hold Slew Rate  
∆tDS  
(ps)  
0
∆tDH  
(ps)  
0
(V/ns)  
0.5  
0.4  
+75  
+150  
+75  
+150  
0.3  
This derating table is used to increase t /t in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate  
DS DH  
based on the lesser of AC-AC slew rate and DC-DC slew rate.  
Rev. 2.2 Mar. ’03  
- 12 -  
K4H560438D  
DDR SDRAM  
8. I/O Setup/Hold Plateau Derating  
I/O Input Level  
(mV)  
∆tDS  
(ps)  
∆tDH  
(ps)  
± 280  
+50  
+50  
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of  
up to 2ns.  
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating  
Delta Rise/Fall Rate  
∆tDS  
(ps)  
0
∆tDH  
(ps)  
0
(ns/V)  
0
±0.25  
±0.5  
+50  
+100  
+50  
+100  
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate  
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall  
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.  
10. This parameter is fir system simulation purpose. It is guranteed by design.  
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.  
<Reference>  
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.  
CK slew rate  
∆tIH/tIS  
∆tDSS/tDSH  
∆tAC/tDQSCK  
∆tLZ(min)  
∆tHZ(max)  
(Single ended)  
(ps)  
(ps)  
(ps)  
(ps)  
(ps)  
1.0V/ns  
0.75V/ns  
0.5V/ns  
0
0
0
0
0
+50  
+100  
+50  
+100  
+50  
+100  
-50  
-100  
+50  
+100  
Rev. 2.2 Mar. ’03  
- 13 -  
K4H560438D  
DDR SDRAM  
(VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)  
AC Operating Test Conditions  
Parameter  
Input reference voltage for Clock  
Input signal maximum peak swing  
Input signal minimum slew rate (for imput only)  
Input slew rate (I/O pins)  
Value  
Unit  
V
Note  
0.5 * VDDQ  
1.5  
V
0.5  
V/ns  
V/ns  
V
0.5  
VREF+0.31/VREF-0.31  
VREF  
Input Levels(VIH/VIL)  
Input timing measurement reference level  
Output timing measurement reference level  
Output load condition  
V
Vtt  
V
See Load Circuit  
Vtt=0.5*VDDQ  
RT=50Ω  
Output  
Z0=50Ω  
CLOAD=30pF  
VREF  
=0.5*VDDQ  
Output Load Circuit (SSTL_2)  
Input/Output Capacitance  
(VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz)  
Parameter  
Symbol  
Min  
Max  
Delta Cap(max)  
Unit  
Input capacitance  
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)  
CIN1  
1.5  
3.5  
0.5  
pF  
Input capacitance( CK, CK )  
Data & DQS input/output capacitance  
Input capacitance(DM)  
CIN2  
COUT  
CIN3  
1.5  
3.5  
3.5  
3.5  
5.5  
5.5  
0.25  
0.5  
pF  
pF  
pF  
Rev. 2.2 Mar. ’03  
- 14 -  
K4H560838D  
DDR SDRAM  
8M x 8Bit x 4 Banks Double Data Rate SDRAM  
GENERAL DESCRIPTION  
The K4H560838D is 268,435,456 bits of double data rate synchronous DRAM organized as 4 x 8,388,608 words by 8 bits, fabricated  
with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up  
to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length  
and programmable latencies allow the device to be useful for a variety of high performance memory system applications.  
Absolute Maximum Rating  
Parameter  
Voltage on any pin relative to VSS  
Voltage on VDD & VDDQ supply relative to VSS  
Storage temperature  
Symbol  
VIN, VOUT  
VDD, VDDQ  
TSTG  
Value  
-0.5 ~ 3.6  
-1.0 ~ 3.6  
-55 ~ +150  
1.5  
Unit  
V
V
°C  
W
Power dissipation  
PD  
Short circuit current  
IOS  
50  
mA  
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.  
Functional operation should be restricted to recommend operation condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability  
DC Operating Conditions  
Recommended operating conditions(Voltage referenced to VSS=0V, TA= 0 to 70°C)  
Parameter  
Supply voltage(for device with a nominal VDD of 2.5V)  
I/O Supply voltage  
Symbol  
VDD  
Min  
2.3  
Max  
2.7  
Unit  
Note  
VDDQ  
VREF  
2.3  
2.7  
V
V
I/O Reference voltage  
VDDQ/2-50mV VDDQ/2+50mV  
1
2
4
4
I/O Termination voltage(system)  
Input logic high voltage  
V
VREF-0.04  
VREF+0.04  
VDDQ+0.3  
VREF-0.15  
VDDQ+0.3  
VDDQ+0.6  
1.35  
V
TT  
VIH(DC)  
VIL(DC)  
VIN(DC)  
VID(DC)  
VIX(DC)  
II  
VREF+0.15  
-0.3  
V
Input logic low voltage  
V
Input Voltage Level, CK and CK inputs  
Input Differential Voltage, CK and CK inputs  
Input crossing point voltage, CK and CK inputs  
Input leakage current  
-0.3  
V
0.3  
V
3
5
1.15  
-2  
V
2
uA  
uA  
Output leakage current  
IOZ  
-5  
5
Output High Current(Normal strengh driver)  
IOH  
IOL  
IOH  
IOL  
-16.8  
16.8  
-9  
mA  
mA  
mA  
mA  
;V  
= V + 0.84V  
OUT  
TT  
Output High Current(Normal strengh driver)  
;V = V - 0.84V  
OUT  
TT  
Output High Current(Half strengh driver)  
;V = V + 0.45V  
OUT  
TT  
Output High Current(Half strengh driver)  
;V = V - 0.45V  
9
OUT  
TT  
Rev. 2.2 Mar. ’03  
- 15 -  
K4H560838D  
DDR SDRAM  
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on  
VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise  
coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.  
2. V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to  
TT  
TT  
VREF, and must track variations in the DC level of VREF  
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.  
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in  
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.  
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.  
(VDD=2.7V, T = 10°C)  
DDR SDRAM IDD spec table  
32Mx8  
Symbol  
Unit  
Notes  
K4H560838D-GC(L)B3  
(DDR333)  
K4H560838D-GC(L)A2, B0  
(DDR266A/B)  
IDD0  
IDD1  
90  
120  
3
80  
110  
3
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2F  
IDD2Q  
IDD3P  
IDD3N  
IDD4R  
IDD4W  
IDD5  
25  
20  
20  
18  
35  
30  
55  
45  
170  
170  
180  
3
140  
140  
165  
3
IDD6  
Normal  
Low power  
IDD7A  
1.5  
325  
1.5  
280  
Optional  
AC Operating Conditions  
Max  
Parameter/Condition  
Symbol  
Min  
Unit  
Note  
Input High (Logic 1) Voltage, DQ, DQS and DM signals  
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.  
Input Differential Voltage, CK and CK inputs  
VIH(AC)  
VIL(AC)  
VID(AC)  
VREF + 0.31  
V
V
V
V
3
3
1
2
VREF - 0.31  
VDDQ+0.6  
0.7  
Input Crossing Point Voltage, CK and CK inputs  
VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2  
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.  
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.  
IX  
DDQ  
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu  
lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.  
Overshoot/Undershoot specification  
Specification  
Parameter  
Address &  
Control pins  
Data pins  
Maximum peak amplitude allowed for overshoot  
1.6 V  
1.6 V  
1.2V  
1.2V  
Maximum peak amplitude allowed for undershoot  
The area between the overshoot signal and VDD must be less than or equal to  
The area between the undershoot signal and GND must be less than or equal to  
4.5 V-ns  
4.5 V-ns  
2.5 V-ns  
2.5 V-ns  
Rev. 2.2 Mar. ’03  
- 16 -  
K4H560838D  
DDR SDRAM  
AC Timming Parameters & Specifications  
B3  
(DDR333)  
A2  
B0  
(DDR266B)  
(DDR266A)  
Parameter  
Symbol  
Unit Note  
Min  
Max  
Min  
Max  
Min Max  
Row cycle time  
tRC  
tRFC  
tRAS  
tRCD  
tRP  
60  
72  
65  
75  
65  
75  
ns  
ns  
Refresh row cycle time  
Row active time  
42  
70K  
45  
120K  
45  
120K  
ns  
RAS to CAS delay  
18  
20  
20  
ns  
Row precharge time  
18  
20  
20  
ns  
Row active to Row active delay  
Write recovery time  
tRRD  
tWR  
12  
15  
15  
ns  
15  
15  
15  
ns  
Last data in to Read command  
Col. address to Col. address delay  
tWTR  
tCCD  
1
1
1
tCK  
tCK  
1
1
1
CL=2.0  
CL=2.5  
7.5  
6
12  
12  
7.5  
7.5  
0.45  
0.45  
-0.75  
-0.75  
-
12  
12  
10  
12  
12  
ns  
ns  
5
5
Clock cycle time  
tCK  
7.5  
0.45  
0.45  
-0.75  
-0.75  
-
Clock high level width  
tCH  
tCL  
0.45  
0.45  
-0.6  
-0.7  
-
0.55  
0.55  
+0.6  
+0.7  
0.4  
0.55  
0.55  
+0.75  
+0.75  
0.5  
0.55  
0.55  
+0.75  
+0.75  
0.5  
tCK  
tCK  
ns  
Clock low level width  
DQS-out access time from CK/CK  
Output data access time from CK/CK  
Data strobe edge to ouput data edge  
Read Preamble  
tDQSCK  
tAC  
ns  
tDQSQ  
tRPRE  
tRPST  
tDQSS  
tWPRES  
tWPRE  
tDSS  
tDSH  
tDQSH  
tDQSL  
tDSC  
tIS  
ns  
5
2
0.9  
0.4  
0.75  
0
1.1  
0.9  
0.4  
0.75  
0
1.1  
0.9  
0.4  
0.75  
0
1.1  
tCK  
tCK  
tCK  
ns  
Read Postamble  
0.6  
0.6  
0.6  
CK to valid DQS-in  
1.25  
1.25  
1.25  
DQS-in setup time  
DQS-in hold time  
0.25  
0.2  
0.2  
0.35  
0.35  
0.9  
0.75  
0.75  
0.8  
0.8  
-0.7  
-0.7  
0.5  
0.5  
1.0  
0.67  
0.25  
0.2  
0.2  
0.35  
0.35  
0.9  
0.9  
0.9  
1.0  
1.0  
-0.75  
-0.75  
0.5  
0.5  
1.0  
0.67  
0.25  
0.2  
0.2  
0.35  
0.35  
0.9  
0.9  
0.9  
1.0  
1.0  
-0.75  
-0.75  
0.5  
0.5  
1.0  
0.67  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
DQS falling edge to CK rising-setup time  
DQS falling edge from CK rising-hold time  
DQS-in high level width  
DQS-in low level width  
DQS-in cycle time  
1.1  
1.1  
1.1  
Address and Control Input setup time(fast)  
Address and Control Input hold time(fast)  
Address and Control Input setup time(slow)  
Address and Control Input hold time(slow)  
Data-out high impedence time from CK/CK  
Data-out low impedence time from CK/CK  
Input Slew Rate(for input only pins)  
Input Slew Rate(for I/O pins)  
6
6
6
6
tIH  
ns  
tIS  
ns  
tIH  
ns  
tHZ  
+0.7  
+0.7  
+0.75  
+0.75  
+0.75  
+0.75  
ns  
tLZ  
ns  
tSL(I)  
tSL(IO)  
tSL(O)  
tSLMR  
V/ns  
V/ns  
V/ns  
6
7
Output Slew Rate(x4,x8)  
4.5  
1.5  
4.5  
1.5  
4.5  
1.5  
10  
Output Slew Rate Matching Ratio(rise to fall)  
Rev. 2.2 Mar. ’03  
- 17 -  
K4H560838D  
DDR SDRAM  
B3  
(DDR333)  
A2  
B0  
(DDR266B)  
(DDR266A)  
Parameter  
Symbol  
Unit  
Note  
Min  
Max  
Min  
Max  
Min  
Max  
Mode register set cycle time  
DQ & DM setup time to DQS  
DQ & DM hold time to DQS  
tMRD  
tDS  
12  
15  
15  
ns  
ns  
ns  
0.45  
0.5  
0.5  
7,8,9  
7,8,9  
tDH  
0.45  
0.5  
0.5  
Control & Address input pulse width  
DQ & DM input pulse width  
Power down exit time  
tIPW  
tDIPW  
tPDEX  
2.2  
1.75  
6
2.2  
1.75  
7.5  
75  
2.2  
1.75  
7.5  
75  
ns  
ns  
ns  
Exit self refresh to non-Read command tXSNR  
75  
ns  
4
Exit self refresh to read command  
Refresh interval time  
tXSRD  
tREFI  
200  
7.8  
200  
7.8  
200  
7.8  
tCK  
us  
1
5
tHP  
-tQHS  
tHP  
-tQHS  
tHP  
-tQHS  
Output DQS valid window  
Clock half period  
tQH  
tHP  
-
-
-
-
-
-
ns  
ns  
tCLmin  
or tCHmin  
tCLmin  
or tCHmin  
tCLmin  
or tCHmin  
Data hold skew factor  
tQHS  
0.5  
0.6  
0.75  
0.6  
0.75  
0.6  
ns  
DQS write postamble time  
tWPST  
0.4  
18  
0.4  
20  
0.4  
20  
tCK  
3
Active to Read with Auto precharge  
command  
tRAP  
Autoprecharge write recovery +  
Precharge time  
(tWR/tCK)  
+
(tWR/tCK)  
+
(tWR/tCK)  
+
tDAL  
tCK  
11  
(tRP/tCK)  
(tRP/tCK)  
(tRP/tCK)  
1. Maximum burst refresh cycle : 8  
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from  
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,  
DQS could be High at this time, depending on tDQSS.  
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,  
but system performance (bus turnaround) will degrade accordingly.  
4. A write command can be applied with tRCD satisfied after this command.  
5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period  
jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.  
6. Input Setup/Hold Slew Rate Derating  
Input Setup/Hold Slew Rate  
∆tIS  
(ps)  
0
∆tIH  
(ps)  
0
(V/ns)  
0.5  
0.4  
+50  
+100  
+50  
+100  
0.3  
This derating table is used to increase t /t in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate  
IS IH  
based on the lesser of AC-AC slew rate and DC-DC slew rate.  
7. I/O Setup/Hold Slew Rate Derating  
I/O Setup/Hold Slew Rate  
∆tDS  
(ps)  
0
∆tDH  
(ps)  
0
(V/ns)  
0.5  
0.4  
+75  
+150  
+75  
+150  
0.3  
This derating table is used to increase t /t in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate  
DS DH  
based on the lesser of AC-AC slew rate and DC-DC slew rate.  
Rev. 2.2 Mar. ’03  
- 18 -  
K4H560838D  
DDR SDRAM  
8. I/O Setup/Hold Plateau Derating  
I/O Input Level  
(mV)  
∆tDS  
(ps)  
∆tDH  
(ps)  
± 280  
+50  
+50  
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of  
up to 2ns.  
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating  
Delta Rise/Fall Rate  
∆tDS  
(ps)  
0
∆tDH  
(ps)  
0
(ns/V)  
0
±0.25  
±0.5  
+50  
+100  
+50  
+100  
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate  
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall  
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.  
10. This parameter is fir system simulation purpose. It is guranteed by design.  
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.  
<Reference>  
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.  
CK slew rate  
∆tIH/tIS  
∆tDSS/tDSH  
∆tAC/tDQSCK  
∆tLZ(min)  
∆tHZ(max)  
(Single ended)  
(ps)  
(ps)  
(ps)  
(ps)  
(ps)  
1.0V/ns  
0.75V/ns  
0.5V/ns  
0
0
0
0
0
+50  
+100  
+50  
+100  
+50  
+100  
-50  
-100  
+50  
+100  
Rev. 2.2 Mar. ’03  
- 19 -  
K4H560838D  
DDR SDRAM  
AC Operating Test Conditions  
(VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)  
Parameter  
Input reference voltage for Clock  
Input signal maximum peak swing  
Input signal minimum slew rate (for imput only)  
Input slew rate (I/O pins)  
Value  
Unit  
V
Note  
0.5 * VDDQ  
1.5  
V
0.5  
V/ns  
V/ns  
V
0.5  
VREF+0.31/VREF-0.31  
VREF  
Input Levels(VIH/VIL)  
Input timing measurement reference level  
Output timing measurement reference level  
Output load condition  
V
Vtt  
V
See Load Circuit  
Vtt=0.5*VDDQ  
RT=50Ω  
Output  
Z0=50Ω  
CLOAD=30pF  
VREF  
=0.5*VDDQ  
Output Load Circuit (SSTL_2)  
Input/Output Capacitance  
(VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz)  
Parameter  
Symbol  
Min  
Max  
Delta Cap(max)  
Unit  
Input capacitance  
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)  
CIN1  
1.5  
3.5  
0.5  
pF  
Input capacitance( CK, CK )  
Data & DQS input/output capacitance  
Input capacitance(DM)  
CIN2  
COUT  
CIN3  
1.5  
3.5  
3.5  
3.5  
5.5  
5.5  
0.25  
0.5  
pF  
pF  
pF  
Rev. 2.2 Mar. ’03  
- 20 -  
K4H561638D  
DDR SDRAM  
4M x 16Bit x 4 Banks Double Data Rate SDRAM  
GENERAL DESCRIPTION  
The K4H561638D is 268,435,456 bits of double data rate synchronous DRAM organized as 4 x 4,194,304 words by 16 bits, fabricated  
with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to  
333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and  
programmable latencies allow the device to be useful for a variety of high performance memory system applications.  
Absolute Maximum Rating  
Parameter  
Voltage on any pin relative to VSS  
Voltage on VDD & VDDQ supply relative to VSS  
Storage temperature  
Symbol  
VIN, VOUT  
VDD, VDDQ  
TSTG  
Value  
-0.5 ~ 3.6  
-1.0 ~ 3.6  
-55 ~ +150  
1.5  
Unit  
V
V
°C  
W
Power dissipation  
PD  
Short circuit current  
IOS  
50  
mA  
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.  
Functional operation should be restricted to recommend operation condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability  
DC Operating Conditions  
Recommended operating conditions(Voltage referenced to VSS=0V, TA= 0 to 70°C)  
Parameter  
Supply voltage(for device with a nominal VDD of 2.5V)  
I/O Supply voltage  
Symbol  
VDD  
Min  
2.3  
Max  
2.7  
Unit  
Note  
VDDQ  
VREF  
2.3  
2.7  
V
V
I/O Reference voltage  
VDDQ/2-50mV VDDQ/2+50mV  
1
2
4
4
I/O Termination voltage(system)  
Input logic high voltage  
V
VREF-0.04  
VREF+0.04  
VDDQ+0.3  
VREF-0.15  
VDDQ+0.3  
VDDQ+0.6  
1.35  
V
TT  
VIH(DC)  
VIL(DC)  
VIN(DC)  
VID(DC)  
VIX(DC)  
II  
VREF+0.15  
-0.3  
V
Input logic low voltage  
V
Input Voltage Level, CK and CK inputs  
Input Differential Voltage, CK and CK inputs  
Input crossing point voltage, CK and CK inputs  
Input leakage current  
-0.3  
V
0.3  
V
3
5
1.15  
-2  
V
2
uA  
uA  
Output leakage current  
IOZ  
-5  
5
Output High Current(Normal strengh driver)  
IOH  
IOL  
IOH  
IOL  
-16.8  
16.8  
-9  
mA  
mA  
mA  
mA  
;V  
= V + 0.84V  
OUT  
TT  
Output High Current(Normal strengh driver)  
;V = V - 0.84V  
OUT  
TT  
Output High Current(Half strengh driver)  
;V = V + 0.45V  
OUT  
TT  
Output High Current(Half strengh driver)  
;V = V - 0.45V  
9
OUT  
TT  
Rev. 2.2 Mar. ’03  
- 21 -  
K4H561638D  
DDR SDRAM  
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on  
VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise  
coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.  
2. V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to  
TT  
TT  
VREF, and must track variations in the DC level of VREF  
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.  
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in  
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.  
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.  
DDR SDRAM IDD spec table  
(VDD=2.7V, T = 10°C)  
16Mx16  
Symbol  
Unit  
Notes  
K4H560838D-GC(L)B3  
(DDR333)  
K4H560838D-GC(L)A2, B0  
(DDR266A/B)  
IDD0  
IDD1  
90  
125  
3
80  
115  
3
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2F  
IDD2Q  
IDD3P  
IDD3N  
IDD4R  
IDD4W  
IDD5  
25  
20  
20  
18  
35  
30  
55  
45  
200  
190  
180  
3
170  
155  
165  
3
IDD6  
Normal  
Low power  
IDD7A  
1.5  
350  
1.5  
300  
Optional  
AC Operating Conditions  
Max  
Parameter/Condition  
Symbol  
Min  
Unit  
Note  
Input High (Logic 1) Voltage, DQ, DQS and DM signals  
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.  
Input Differential Voltage, CK and CK inputs  
VIH(AC)  
VIL(AC)  
VID(AC)  
VREF + 0.31  
V
V
V
V
3
3
1
2
VREF - 0.31  
VDDQ+0.6  
0.7  
Input Crossing Point Voltage, CK and CK inputs  
VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2  
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.  
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.  
IX  
DDQ  
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu  
lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.  
Overshoot/Undershoot specification  
Specification  
Parameter  
Address &  
Control pins  
Data pins  
Maximum peak amplitude allowed for overshoot  
1.6 V  
1.6 V  
1.2V  
1.2V  
Maximum peak amplitude allowed for undershoot  
The area between the overshoot signal and VDD must be less than or equal to  
The area between the undershoot signal and GND must be less than or equal to  
4.5 V-ns  
4.5 V-ns  
2.5 V-ns  
2.5 V-ns  
Rev. 2.2 Mar. ’03  
- 22 -  
K4H561638D  
DDR SDRAM  
AC Timming Parameters & Specifications  
B3  
(DDR333)  
A2  
B0  
(DDR266B)  
(DDR266A)  
Parameter  
Symbol  
Unit Note  
Min  
Max  
Min  
Max  
Min Max  
Row cycle time  
tRC  
tRFC  
tRAS  
tRCD  
tRP  
60  
72  
65  
75  
65  
75  
ns  
ns  
Refresh row cycle time  
Row active time  
42  
70K  
45  
120K  
45  
120K  
ns  
RAS to CAS delay  
18  
20  
20  
ns  
Row precharge time  
18  
20  
20  
ns  
Row active to Row active delay  
Write recovery time  
tRRD  
tWR  
12  
15  
15  
ns  
15  
15  
15  
ns  
Last data in to Read command  
Col. address to Col. address delay  
tWTR  
tCCD  
1
1
1
tCK  
tCK  
1
1
1
CL=2.0  
CL=2.5  
7.5  
6
12  
12  
7.5  
7.5  
0.45  
0.45  
-0.75  
-0.75  
-
12  
12  
10  
12  
12  
ns  
ns  
5
5
Clock cycle time  
tCK  
7.5  
0.45  
0.45  
-0.75  
-0.75  
-
Clock high level width  
tCH  
tCL  
0.45  
0.45  
-0.6  
-0.7  
-
0.55  
0.55  
+0.6  
+0.7  
0.4  
0.55  
0.55  
+0.75  
+0.75  
0.5  
0.55  
0.55  
+0.75  
+0.75  
0.5  
tCK  
tCK  
ns  
Clock low level width  
DQS-out access time from CK/CK  
Output data access time from CK/CK  
Data strobe edge to ouput data edge  
Read Preamble  
tDQSCK  
tAC  
ns  
tDQSQ  
tRPRE  
tRPST  
tDQSS  
tWPRES  
tWPRE  
tDSS  
tDSH  
tDQSH  
tDQSL  
tDSC  
tIS  
ns  
5
2
0.9  
0.4  
0.75  
0
1.1  
0.9  
0.4  
0.75  
0
1.1  
0.9  
0.4  
0.75  
0
1.1  
tCK  
tCK  
tCK  
ns  
Read Postamble  
0.6  
0.6  
0.6  
CK to valid DQS-in  
1.25  
1.25  
1.25  
DQS-in setup time  
DQS-in hold time  
0.25  
0.2  
0.2  
0.35  
0.35  
0.9  
0.75  
0.75  
0.8  
0.8  
-0.7  
-0.7  
0.5  
0.5  
1.0  
0.67  
0.25  
0.2  
0.2  
0.35  
0.35  
0.9  
0.9  
0.9  
1.0  
1.0  
-0.75  
-0.75  
0.5  
0.5  
1.0  
0.67  
0.25  
0.2  
0.2  
0.35  
0.35  
0.9  
0.9  
0.9  
1.0  
1.0  
-0.75  
-0.75  
0.5  
0.5  
1.0  
0.67  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
DQS falling edge to CK rising-setup time  
DQS falling edge from CK rising-hold time  
DQS-in high level width  
DQS-in low level width  
DQS-in cycle time  
1.1  
1.1  
1.1  
Address and Control Input setup time(fast)  
Address and Control Input hold time(fast)  
Address and Control Input setup time(slow)  
Address and Control Input hold time(slow)  
Data-out high impedence time from CK/CK  
Data-out low impedence time from CK/CK  
Input Slew Rate(for input only pins)  
Input Slew Rate(for I/O pins)  
6
6
6
6
tIH  
ns  
tIS  
ns  
tIH  
ns  
tHZ  
+0.7  
+0.7  
+0.75  
+0.75  
+0.75  
+0.75  
ns  
tLZ  
ns  
tSL(I)  
tSL(IO)  
tSL(O)  
tSLMR  
V/ns  
V/ns  
V/ns  
6
7
Output Slew Rate(x4,x8)  
4.5  
1.5  
4.5  
1.5  
4.5  
1.5  
10  
Output Slew Rate Matching Ratio(rise to fall)  
Rev. 2.2 Mar. ’03  
- 23 -  
K4H561638D  
DDR SDRAM  
B3  
(DDR333)  
A2  
B0  
(DDR266B)  
(DDR266A)  
Parameter  
Symbol  
Unit Note  
Min  
Max  
Min  
Max  
Min Max  
Mode register set cycle time  
DQ & DM setup time to DQS  
DQ & DM hold time to DQS  
tMRD  
tDS  
12  
15  
15  
ns  
0.45  
0.5  
0.5  
ns  
ns  
7,8,9  
7,8,9  
tDH  
0.45  
0.5  
0.5  
Control & Address input pulse width  
DQ & DM input pulse width  
Power down exit time  
tIPW  
tDIPW  
tPDEX  
tXSNR  
tXSRD  
tREFI  
2.2  
1.75  
6
2.2  
1.75  
7.5  
2.2  
1.75  
7.5  
ns  
ns  
ns  
Exit self refresh to non-Read command  
Exit self refresh to read command  
Refresh interval time  
75  
75  
75  
ns  
4
200  
7.8  
200  
7.8  
200  
7.8  
tCK  
us  
1
5
tHP  
-tQHS  
tHP  
-tQHS  
tHP  
-tQHS  
Output DQS valid window  
Clock half period  
tQH  
tHP  
-
-
-
-
-
-
ns  
ns  
tCLmin  
or tCHmin  
tCLmin  
or tCHmin  
tCLmin  
or tCHmin  
Data hold skew factor  
tQHS  
0.5  
0.6  
0.75  
0.6  
0.75  
0.6  
ns  
DQS write postamble time  
tWPST  
0.4  
18  
0.4  
20  
0.4  
20  
tCK  
3
Active to Read with Auto precharge  
command  
tRAP  
Autoprecharge write recovery +  
Precharge time  
(tWR/tCK)  
+
(tWR/tCK)  
+
(tWR/tCK)  
+
tDAL  
tCK  
11  
(tRP/tCK)  
(tRP/tCK)  
(tRP/tCK)  
1. Maximum burst refresh cycle : 8  
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from  
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,  
DQS could be High at this time, depending on tDQSS.  
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,  
but system performance (bus turnaround) will degrade accordingly.  
4. A write command can be applied with tRCD satisfied after this command.  
5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period  
jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.  
6. Input Setup/Hold Slew Rate Derating  
Input Setup/Hold Slew Rate  
∆tIS  
(ps)  
0
∆tIH  
(ps)  
0
(V/ns)  
0.5  
0.4  
+50  
+100  
+50  
+100  
0.3  
This derating table is used to increase t /t in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate  
IS IH  
based on the lesser of AC-AC slew rate and DC-DC slew rate.  
7. I/O Setup/Hold Slew Rate Derating  
I/O Setup/Hold Slew Rate  
∆tDS  
(ps)  
0
∆tDH  
(ps)  
0
(V/ns)  
0.5  
0.4  
+75  
+150  
+75  
+150  
0.3  
This derating table is used to increase t /t in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate  
DS DH  
based on the lesser of AC-AC slew rate and DC-DC slew rate.  
Rev. 2.2 Mar. ’03  
- 24 -  
K4H561638D  
DDR SDRAM  
8. I/O Setup/Hold Plateau Derating  
I/O Input Level  
(mV)  
∆tDS  
(ps)  
∆tDH  
(ps)  
± 280  
+50  
+50  
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of  
up to 2ns.  
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating  
Delta Rise/Fall Rate  
∆tDS  
(ps)  
0
∆tDH  
(ps)  
0
(ns/V)  
0
±0.25  
±0.5  
+50  
+100  
+50  
+100  
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate  
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall  
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.  
10. This parameter is fir system simulation purpose. It is guranteed by design.  
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.  
<Reference>  
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.  
CK slew rate  
∆tIH/tIS  
∆tDSS/tDSH  
∆tAC/tDQSCK  
∆tLZ(min)  
∆tHZ(max)  
(Single ended)  
(ps)  
(ps)  
(ps)  
(ps)  
(ps)  
1.0V/ns  
0.75V/ns  
0.5V/ns  
0
0
0
0
0
+50  
+100  
+50  
+100  
+50  
+100  
-50  
-100  
+50  
+100  
Rev. 2.2 Mar. ’03  
- 25 -  
K4H561638D  
DDR SDRAM  
AC Operating Test Conditions  
(VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)  
Parameter  
Input reference voltage for Clock  
Input signal maximum peak swing  
Input signal minimum slew rate (for imput only)  
Input slew rate (I/O pins)  
Value  
Unit  
V
Note  
0.5 * VDDQ  
1.5  
V
0.5  
V/ns  
V/ns  
V
0.5  
VREF+0.31/VREF-0.31  
VREF  
Input Levels(VIH/VIL)  
Input timing measurement reference level  
Output timing measurement reference level  
Output load condition  
V
Vtt  
V
See Load Circuit  
Vtt=0.5*VDDQ  
RT=50Ω  
Output  
Z0=50Ω  
CLOAD=30pF  
VREF  
=0.5*VDDQ  
Output Load Circuit (SSTL_2)  
Input/Output Capacitance  
(VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz)  
Parameter  
Symbol  
Min  
Max  
Delta Cap(max)  
Unit  
Input capacitance  
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)  
CIN1  
1.5  
3.5  
0.5  
pF  
Input capacitance( CK, CK )  
Data & DQS input/output capacitance  
Input capacitance(DM)  
CIN2  
COUT  
CIN3  
1.5  
3.5  
3.5  
3.5  
5.5  
5.5  
0.25  
0.5  
pF  
pF  
pF  
Rev. 2.2 Mar. ’03  
- 26 -  

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