K4H641638N-FCCC0 [SAMSUNG]
DDR DRAM, 4MX16, 0.65ns, CMOS, PBGA60, ROHS COMPLIANT AND HALOGEN FREE, FBGA-60;
| 型号： | K4H641638N-FCCC0 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 4MX16, 0.65ns, CMOS, PBGA60, ROHS COMPLIANT AND HALOGEN FREE, FBGA-60 动态存储器 双倍数据速率 |
| 文件： | 总30页 (文件大小：390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDR SDRAM
K4H641638N
64Mb N-die DDR SDRAM Specification
66 TSOP-II & 60 FBGA
with Lead-Free and Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 August 2009
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DDR SDRAM
K4H641638N
Table of Contents
1.0 Key Features ...............................................................................................................................4
2.0 Ordering Information ..................................................................................................................4
3.0 Operating Frequencies ...............................................................................................................4
4.0 Pin Description ........................................................................................................................... 5
5.0 Package Physical Dimension ....................................................................................................7
6.0 Block Diagram (1Mb x 16 I/O x4 Banks) ....................................................................................9
7.0 Input/Output Function Description ......................................................................................... 10
8.0 Command Truth Table ..............................................................................................................11
9.0 General Description ..................................................................................................................12
10.0 Absolute Maximum Rating .....................................................................................................12
11.0 DC Operating Conditions .......................................................................................................13
12.0 DDR SDRAM Spec Items & Test Conditions ........................................................................14
13.0 Input/Output Capacitance ......................................................................................................14
14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................15
15.0 DDR SDRAM IDD spec table ..................................................................................................16
16.0 AC Operating Conditions .......................................................................................................17
17.0 AC Overshoot/Undershoot specification for Address and Control Pins ...........................17
18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins ..............................18
19.0 AC Timming Parameters & Specifications ...........................................................................19
20.0 System Characteristics for DDR SDRAM .............................................................................20
21.0 Component Notes ...................................................................................................................21
22.0 System Notes ..........................................................................................................................23
23.0 Output Drive Strength and Extended Mode Register Set for 64Mb DDR ............................24
24.0 IBIS : I/V Characteristics for Input and Output Buffers .......................................................25
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DDR SDRAM
K4H641638N
Revision History
Revision
Month
Year
History
1.0
September
2007
- Release 1.0 version SPEC
- Corrected typo of package demension
1.1
October
2007
- Revised IBIS SPEC from target value to real value
- Revised typo of package dimension
- Added Package pin out lead width
- Corrected typo
1.2
1.21
1.22
November
March
August
2007
2008
2008
- Deleted 333(-B3)Mbps speed
1.3
1.4
February
August
2009
2009
- Corrected matched drive strength SPEC.
- Deleted B3(DDR333@CL2.5) speed bin.
- Corrected typo
Rev. 1.4 August 2009
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DDR SDRAM
K4H641638N
1.0 Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for 400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 15.6us refresh interval(4K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II Lead-Free and Halogen-Free package
• 60ball FBGA Lead-Free and Halogen-Free package
• RoHS compliant
2.0 Ordering Information
Part No.
Org.
Max Freq.
Interface
Package
Note
66pin TSOP II
Lead-Free & Halogen-Free
K4H641638N-LC/LCC
4M x 16
SSTL2
1
CC(DDR400@CL=3)
60ball FBGA
Lead-Free & Halogen-Free
K4H641638N-FC/LCC
4M x 16
SSTL2
1
CC(DDR400@CL=3)
Note :
1. “L” and "F" of Part number(12th digit) stands for RoHS compliant and Halogen-Free product.
3.0 Operating Frequencies
CC(DDR400@CL=3)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
-
166MHz
200MHz
3-3-3
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DDR SDRAM
K4H641638N
4.0 Pin / Ball Description
66pin TSOP - II
16Mb x 16
V
SS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1
V
DD
DQ15
2
DQ
0
VSSQ
3
VDDQ
DQ14
DQ13
4
DQ
1
2
5
DQ
VDDQ
6
VSSQ
DQ12
DQ11
7
DQ
3
4
8
DQ
VSSQ
9
VDDQ
DQ10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
DQ
5
6
66Pin TSOPII
(400mil x 875mil)
(0.65mm Pin Pitch)
DQ
9
DQ
VDDQ
VSSQ
DQ
8
DQ
7
NC
NC
Bank Address
BA0~BA1
VSSQ
VDDQ
UDQS
NC
LDQS
NC
Auto Precharge
A10
VREF
VDD
VSS
NC
LDM
WE
UDM
CK
CK
CAS
RAS
CS
CKE
NC
24
25
26
27
28
29
30
31
32
33
NC
NC
A
A
A
A
A
A
A
11
BA
0
9
BA
1
8
AP/A10
7
A
A
A
A
0
1
2
3
6
5
4
VSS
VDD
64Mb TSOP-II Package Pinout
Organization
Row Address
Column Address
4Mx16
A0~A11
A0-A7
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
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DDR SDRAM
K4H641638N
60ball FBGA (Top View)
4M x 16
9
8
7
VDDQ
DQ1
VSSQ
DQ2
B
DQ3
VDDQ
DQ4
C
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQS
E
NC
VDD
LDM
F
DQ0
VDD
CAS
WE
CS
BA0 A10/AP
A1
A2
A3
RAS
BA1
A0
VDD
A
D
G
H
J
K
L
M
3
2
1
VSS
DQ13 DQ11
DQ9
UDQS UDM
CK
CKE
A9
A7
A5
VSS
DQ15 VDDQ
VSSQ
VDDQ
VSSQ
DQ8
VSS
CK
NC
A11
A8
A6
A4
VSSQ DQ14 DQ12 DQ10
VREF
64Mb FBGA Package ballout
Organization
Row Address
Column Address
4Mx16
A0~A11
A0-A7
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
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DDR SDRAM
K4H641638N
5.0 Package Physical Dimension
Unit : mm
#66
#34
#1
#33
(1.50)
+0.075
- 0.035
0.125
22.22 ± 0.10
(10°)
0.10 MAX
[
(10°)
0.65TYP
0.075 MAX
[
(0.71)
[0.65 ± 0.08]
Detail A
Detail B
Detail B
0.25TYP
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASS’Y OUT QUALITY
Detail A
(0° ∼ 8°)
± 0.08
± 0.08
0.30
0.25
66Pin TSOP(II) Package Dimension
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DDR SDRAM
K4H641638N
Units : Millimeters
8.00 ± 0.10
A
#A1 MARK
0.80 x 8 = 6.40
0.80
8.0 0 ± 0.10
1.60
#A1
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
(Datum B)
G
H
J
K
L
M
0.32 ± 0.05
1.10 ± 0.10
60 - ∅ 0.45 SOLDER BALL
(Datum A)
(Post Reflow 0.50 ± 0.05)
M
A B
∅0.20
TOP VIEW
BOTTOM VIEW
60Ball FBGA 64Mb Package Dimension
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DDR SDRAM
K4H641638N
6.0 Block Diagram (1Mb x16 I/O x4 Banks)
LWE
x4/8/16
CK, CK
Data Input Register
Serial to parallel
LUDM (x16)
Bank Select
x8/16/32
0.5Mx32
0.5Mx32
0.5Mx32
0.5Mx32
32
16
16
DQi
CK, CK
ADD
Column Decoder
Latency & Burst Length
Data Strobe
Programming Register
LWCBR
LCKE
LRAS LCBR
LWE
LUDM (x16)
LCAS
CK, CK
DM Input Register
LUDM (x16)
Timing Register
CK, CK
CKE
CS
RAS
CAS
WE
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DDR SDRAM
K4H641638N
7.0 Input/Output Function Description
SYMBOL
TYPE
DESCRIPTION
Clock : CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/CK.
CK, CK
Input
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE Low provides PRECHARGE POWER-
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughput READ and WRITE accesses. Input buffers, excluding CK,
CK and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are disabled
during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS Low level after
VDD is applied upon 1st power up, After VREF has become stable during the power on and ini-
CKE
Input
tialization sequence, it must be maintained for proper operation of the CKE receiver. For
proper SELF-REFRESH entry and exit, VREF must be maintained to this input.
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
CS
Input
Input
RAS, CAS, WE
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading. For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data
on DQ8~DQ15. DM may be driven high, low, or floating during READs.
LDM,(UDM)
BA0, BA1
Input
Input
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-
CHARGE command is being applied.
Address Inputs : Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-
mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).
A [0 : 11]
Input
DQ
I/O
I/O
Data Input/Output : Data bus
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on
DQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15.
LDQS,(U)DQS
LDQS is NC on x4 and x8.
NC
-
No Connect : No internal electrical connection is present.
DQ Power Supply : +2.5V ± 0.2V.
DQ Ground.
VDDQ
Supply
Supply
Supply
Supply
Input
VSSQ
VDD
Power Supply : +2.5V ± 0.2V.
Ground.
VSS
VREF
SSTL_2 reference voltage.
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DDR SDRAM
K4H641638N
8.0 Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
A0 ~ A9,
COMMAND
CKEn-1 CKEn CS RAS CAS
WE BA0,1 A10/AP
Note
A11 ~ A12
Register
Register
Extended MRS
Mode Register Set
Auto Refresh
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
3
3
H
L
L
L
H
X
Entry
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
Exit
L
H
H
H
X
X
X
3
Bank Active & Row Addr.
Read &
Column Address
V
V
Row Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
4
4, 6
7
Column
Address
L
H
L
H
Write &
Column Address
Column
Address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
H
X
5
H
L
X
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
DM(UDM/LDM for x16 only)
No operation (NOP) : Not defined
Note :
X
X
8
9
9
H
L
X
H
X
H
1. OP Code : Operand Code. A0 ~ A12& BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges
(Write UDM/LDM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
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DDR SDRAM
K4H641638N
1M x 16Bit x 4 Banks Double Data Rate SDRAM
9.0 General Description
The K4H641638N is 67,108,864 bits of double data rate synchronous DRAM organized as 4x 1,048,576 words by 16bits, fabricated with
SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to
400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and
programmable latencies allow the device to be useful for a variety of high performance memory system applications.
10.0 Absolute Maximum Rating
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
Storage temperature
VDD, VDDQ
TSTG
PD
1.0 ~ 3.6
V
°C
W
-55 ~ +150
Power dissipation
1
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
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DDR SDRAM
K4H641638N
11.0 DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
VDD
Min
2.3
Max
2.7
Unit
V
Note
Supply voltage
VDDQ
VREF
VTT
I/O Supply voltage
2.3
2.7
V
0.49*VDDQ
VREF-0.04
VREF+0.15
0.51*VDDQ
VREF+0.04
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
V
1
2
V
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VI(Ratio)
II
V
-0.3
-0.3
0.36
0.71
-2
V
Input Voltage Level, CK and CK inputs
V
Input Differential Voltage, CK and CK inputs
V-I Matching: Pull-up to Pull-down Current Ratio
Input leakage current
V
3
4
1.4
2
-
uA
uA
mA
mA
mA
mA
mA
mA
Output leakage current
IOZ
-5
5
Output High Current(Full strengh driver) ; VOUT=VDDQ-0.388V
Output LowCurrent(Full strengh driver) ; VOUT=0.388V
Output High Current(Week strengh driver) ; VOUT=VDDQ-0.538V
Output Low Current(Week strengh driver) ; VOUT=0.538V
Output High Current(Mached strengh driver) ; VOUT=VDDQ-0.6505V
Output Low Current(Mached strengh driver) ; VOUT=0.6505V
Note :
IOH
-13.8
16.5
-18.2
20.2
-15.5
17
-16.1
19.2
-21.8
24.5
-18.9
21.3
IOL
IOH
IOL
IOH
IOL
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may
not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track vari-
ations in the DC level of VREF,
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the Pull-up current to the Pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage
range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between Pull-up and Pull-down
drivers due to process variation. The full variation in the ratio of the maximum to minimum Pull-up and Pull-down current will not exceed 1.7 for device
drain to source voltages from 0.1 to 1.0.
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DDR SDRAM
K4H641638N
12.0 DDR SDRAM Spec Items & Test Conditions
Conditions
Symbol
IDD0
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK=5ns for DDR400;
DQ,DM and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating current - One bank operation ; One bank open, BL=4, Reads
IDD1
- Refer to the following page for detailed test condition
Precharge power-down standby current; All banks idle; power - down mode;
CKE = <VIL(max); tCK=5ns for DDR400;
IDD2P
VIN = VREF for DQ,DQS and DM.
Precharge Floating standby current; CS > =VIH(min);All banks idle; CKE > = VIH(min); tCK=5ns for DDR400;
IDD2F
IDD2Q
Address and other control inputs changing once per clock cycle; VIN = VREF for DQ,DQS and DM
Precharge Quiet standby current; CS > = VIH(min); All banks idle;
CKE > = VIH(min); tCK=5ns for DDR400
; Address and other control inputs stable at >= VIH(min) or =<VIL(max); VIN = VREF for DQ ,DQS and DM
Active power - down standby current ; one bank active; power-down mode;
CKE=< VIL (max); tCK=5ns for DDR400;
IDD3P
VIN = VREF for DQ,DQS and DM
Active standby current; CS >= VIH(min); CKE>=VIH(min);
IDD3N
IDD4R
IDD4W
one bank active; active - precharge; tRC=tRASmax; tCK=5ns for DDR400; DQ, DQS and DM inputs changing twice
per clock cycle; address and other control inputs changing once per clock cycle
Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control
inputs changing once per clock cycle; CL=2 at tCK=5ns for DDR400; 50% of data changing on every transfer; lout
= 0 m A
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle; tCK=5ns for DDR400; DQ, DM and
DQS inputs changing twice per clock cycle, 50% of input data changing at every burst
Auto refresh current; tRC = tRFC(min) which is 14*tCK for DDR400 at tCK=5ns; distributed refresh
Self refresh current; CKE =< 0.2V; External clock on; tCK=5ns for DDR400.
IDD5
IDD6
Operating current - Four bank operation ; Four bank interleaving with BL=4
IDD7A
-Refer to the following page for detailed test condition
13.0 Input/Output Capacitance
( TA= 25°C, f=100MHz)
Parameter
Symbol
Min
Max
DeltaCap(max)
Unit
Note
Input capacitance
CIN1
1
4
0.5
pF
4
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
Input capacitance( CK, CK )
CIN2
COUT
CIN3
1
1
1
5
0.25
pF
pF
pF
4
Data & DQS input/output capacitance
Input capacitance(DM for x4/8, UDM/LDM for x16)
Note :
6.5
6.5
1,2,3,4
1,2,3,4
0.5
1.These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.
This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameteer is sampled. VDDQ = +2.5V +0.2V, VDD = +2.5V+0.2V. For all devices, f=100MHz, tA=25°C, VOUT(DC) = VDDQ/2,
VOUT(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the
board level).
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DDR SDRAM
K4H641638N
14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A
IDD1 : Operating current: One bank operation
1. Typical Case: VDD= 2.5V, T=25°C
Worst Case : VDD = 2.7V, T= 10°C
2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
3. Timing patterns
- CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT
IDD7A : Operating current: Four bank operation
1. Typical Case: VDD = 2.5V, T=25°C
Worst Case : VDD = 2.7V, T= 10°C
2. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
3. Timing patterns
- CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT
Rev. 1.4 August 2009
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DDR SDRAM
K4H641638N
15.0 DDR SDRAM IDD Spec Table
4Mx16 (K4H641638N)
CC(DDR400@CL=3)
Symbol
IDD0
IDD1
90
125
4
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
30
25
40
60
160
160
150
3
Normal
IDD6
Low power
1.5
220
IDD7A
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DDR SDRAM
K4H641638N
16.0 AC Operating Conditions
Parameter/Condition
Symbol
VIH(AC)
Min
VREF + 0.31
Max
Unit
V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
I/O Reference Voltage
VIL(AC)
VID(AC)
VIX(AC)
VREF(AC)
VREF - 0.31
VDDQ+0.6
V
0.7
V
1
2
3
0.5*VDDQ-0.2
0.45 x VDDQ
0.5*VDDQ+0.2
0.55 x VDDQ
V
V
Note :
1. V is the magnitude of the difference between the input level on CK and the input level on CK.
ID
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
3. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same.
Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC
error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor.
17.0 AC Overshoot/Undershoot specification for Address and Control Pins
Specification
Parameter
DDR400
1.5 V
DDR333
1.5 V
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
1.5 V
1.5 V
The area between the overshoot signal and VDD must be less than or equal to
4.5 V-ns
4.5 V-ns
4.5 V-ns
4.5 V-ns
The area between the undershoot signal and GND must be less than or equal to
V
DD
Overshoot
Area
5
4
Maximum Amplitude = 1.5V
3
2
1
0
-1
-2
-3
-4
-5
Maximum Amplitude = 1.5V
GND
0
0.6875
0.5 1.0
1.5
2.5
3.5
4.5
5.5
6.3125
6.0 6.5
undershoot
7.0
2.0
3.0
4.0
5.0
Tims(ns)
AC overshoot/Undershoot Definition
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DDR SDRAM
K4H641638N
18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins
Specification
Parameter
DDR400
1.2 V
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
1.2 V
The area between the overshoot signal and VDD must be less than or equal to
2.4 V-ns
2.4 V-ns
The area between the undershoot signal and GND must be less than or equal to
V
DDQ
Overshoot
5
4
Maximum Amplitude = 1.2V
3
2
Area
1
0
-1
-2
-3
-4
-5
Maximum Amplitude = 1.2V
GND
0
0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0
Tims(ns)
undershoot
DQ/DM/DQS AC overshoot/Undershoot Definition
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DDR SDRAM
K4H641638N
19.0 AC Timing Parameters & Specifications
CC
(DDR400@CL=3.0)
Parameter
Symbol
Unit
Note
Min
55
70
40
15
Max
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
70K
15
Row active to Row active delay
Write recovery time
Last data in to Read command
tRRD
tWR
tWTR
10
15
2
-
6
5
CL=2.0
CL=2.5
CL=3.0
-
12
10
Clock cycle time
tCK
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
tCH
tCL
tDQSCK
tAC
0.45
0.45
-0.55
-0.65
-
0.55
0.55
+0.55
+0.65
0.4
tCK
tCK
ns
ns
ns
TSOP
FBGA
22
22
Data strobe edge to ouput data edge
tDQSQ
-
0.4
ns
Read Preamble
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tIS
tIH
tIS
tIH
tHZ
tLZ
tMRD
tDS
0.9
0.4
0.72
0
1.1
0.6
1.28
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
13
0.25
0.2
0.2
0.35
0.35
0.6
0.6
0.7
0.7
-0.65
-0.65
10
DQS-in low level width
15, 17~19
15, 17~19
16~19
16~19
11
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
+0.65
+0.65
11
DQ & DM setup time to DQS
0.4
j, k
j, k
ns
DQ & DM hold time to DQS
tDH
0.4
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
tIPW
tDIPW
tXSNR
tXSRD
tREFI
2.2
1.75
75
ns
ns
ns
tCK
us
18
18
200
15.6
14
21
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
ns
ns
tCLmin
or tCHmin
-
20, 21
TSOP
FBGA
tQHS
tQHS
tWPST
0.5
0.5
0.6
ns
ns
tCK
21
21
12
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
0.4
15
tRAP
(tWR/tCK)
+
(tRP/tCK)
Autoprecharge write recovery +
Precharge time
tDAL
tCK
tCK
23
Power Down Exit
tPDEX
1
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DDR SDRAM
K4H641638N
20.0 System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR400 and DDR333 devices to ensure proper system perfor-
mance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
DDR400
DDR333
PARAMETER
DQ/DM/DQS input slew rate measured between
V (DC), V (DC) and V (DC), V (DC)
SYMBOL
MIN
MAX
MIN
MAX
Units
Notes
DCSLEW
0.5
4.0
0.5
4.0
V/ns
a, l
IH
IL
IL
IH
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
∆tIS
∆tIH
Units
Notes
0.5 V/ns
0
0
0
0
ps
i
i
i
0.4 V/ns
+50
+100
ps
0.3 V/ns
ps
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
∆tDS
∆tDH
Units
Notes
0.5 V/ns
0
0
ps
k
k
k
0.4 V/ns
+75
+150
+75
+150
ps
0.3 V/ns
ps
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
∆tDS
∆tDH
Units
Notes
+/- 0.0 V/ns
0
0
ps
j
j
j
+/- 0.25 V/ns
+/- 0.5 V/ns
+50
+100
+50
+100
ps
ps
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Typical Range
Minimum
Maximum
Slew Rate Characteristic
Notes
(V/ns)
(V/ns)
(V/ns)
Pull-up Slew Rate
Pull-down slew
1.2 ~ 2.5
1.2 ~ 2.5
1.0
1.0
4.5
4.5
a,c,d,f,g,h
b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Typical Range
Minimum
Maximum
Slew Rate Characteristic
Notes
(V/ns)
(V/ns)
(V/ns)
Pull-up Slew Rate
Pull-down slew
1.2 ~ 2.5
1.2 ~ 2.5
0.7
0.7
5.0
5.0
a,c,d,f,g,h
b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS
DDR400
DDR333
PARAMETER
Output Slew Rate Matching Ratio (Pull-up to Pull-down)
MIN
0.67
MAX
1.5
MIN
0.67
MAX
1.5
Notes
e, l
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DDR SDRAM
K4H641638N
21.0 Component Notes
1. All voltages referenced to VSS
.
2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels,
but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be
either a precise representation of the typical system environment nor a depiction of the actual load presented by a production
tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment.
Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester elec-
tronics).
VTT
50Ω
Output
(Vout)
30pF
Figure 1 : Timing Reference Load
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to
VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under nor-
mal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(AC) and VIH(AC).
5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result
of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc
input LOW (HIGH) level.
6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ is
recognized as LOW.
7. Enables on.chip refresh and address counters.
8. IDD specifications are tested after the device is properly initialized.
9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level
for signals other than CK/CK, is VREF
.
10. The output timing reference voltage level is VTT
.
11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to
a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys
tem performance (bus turnaround) will degrade accordingly.
13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ
ously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
15. For command/address input slew rate ≥ 1.0 V/ns
16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
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DDR SDRAM
K4H641638N
Component Notes
17. For CK & CK slew rate ≥ 1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
19. Slew Rate is measured between VOH(AC) and VOL(AC).
20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
21. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
22. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
23. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR400 at CL=3 and
tCK=5ns tDAL = (15 ns / 5 ns) + (15 ns/ 5ns) = (3) + (3)
tDAL = 6 clocks
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DDR SDRAM
K4H641638N
22.0 System Notes
a. Pull-up slew rate is characteristized under the test conditions as shown in Figure 2
Test point
Output
50Ω
VSSQ
Figure 2 : Pull-up slew rate test load
b. Pull-down slew rate is measured under the test conditions shown in Figure 3
VDDQ
50Ω
Output
Test point
Figure 3 : Pull-down slew rate test load
c. Pull-up slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pull-down slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pull-up and Pull-down slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process
e. The ratio of Pull-up slew rate to Pull-down slew rate is specified for the same temperature and voltage, over the entire temperature
and voltage range. For a given output, it represents the maximum difference between Pull-up and Pull-down drivers due to process
variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 400 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions.
l. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotonic.
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DDR SDRAM
K4H641638N
23.0 Output Drive Strength and Extended Mode Register Set for 64Mb DDR
The 100%, 60%, and 30% or matched impedance drive strength options are required and are defined in External Mode Register
(EMRS). The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength. The default
value of the extended mode register is not defined, therefore must be written after power up0 for proper operation. The extended mode
register is written by asserting low on CS, RAS, CAS, and WE. The state of A0, A2 ~ A5, A7 ~ A11and BA1 is written in the mode register
in the same cycle as CS, RAS, CAS, and WE going low. The DDR SDRAM should be in all bank precharge with CKE already high prior
to writing into the extended mode register. A1 and A6 are used for setting driver strength to 100%, 60%, or 30%. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable.
"High" on BA0 is used for EMRS. Refer to the table for specific codes.
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
RFU must be set to "0"
DS1
RFU must be set to "0"
DS0
DLL
BA1 Mode
A6 A1 Drive Strength Strength
Comment
A0
0
1
DLL
Enable
Disable
0
1
MRS
EMRS
0
0
1
0
Full
weak
RFU
100%
60%
0
1
RFU
Do not use
Matched
impedance
Output driver
matches impedance
1
1
30%
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DDR SDRAM
K4H641638N
24.0 IBIS : I/V Characteristics for Input and Output Buffers
DDR SDRAM Output Driver V-I Characteristics
DDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1.
Figures 4, 5 and 6 show the driver characteristics graphically, and tables 8, 9 and 10 show the same data in tabular format suitable for
input into simulation tools. The driver characteristcs evaluation conditions are:
Typical
Minimum
Maximum
25×C
70×C
0×C
VDD/VDDQ = 2.5V, typical process
VDD/VDDQ = 2.3V, slow-slow process
VDD/VDDQ = 2.7V, fast-fast process
Output Driver Characteristic Curves Notes:
1. The full variation in driver current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines
the of the V-I curve of Figures 4, 5 and 6.
2. It is recommended that the "typical" IBIS V-I curve lie within the inner bounding lines of the V-I curves of Figures 4, 5 and 6.
3. The full variation in the ratio of the "typical" IBIS Pull-up to "typical" IBIS Pull-down current should be unity +/- 10%, for device drain to
source voltages from 0.1 to1.0. This specification is a design objective only. It is not guaranteed.
160
Maximum
140
120
100
80
Typical High
Typical Low
Minimum
60
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
Vout(V)
Pull-down Characteristics for Full Strength Output Driver
0.0
1.0
2.0
0
-20
-40
Minumum
-60
-80
Typical Low
-100
-120
-140
-160
-180
-200
-220
Typical High
Maximum
Vout(V)
Pull-up Characteristics for Full Strength Output Driver
Figure 4 : I/V characteristics for input/output buffers : Pull-down(above) and Pull-up(below)
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DDR SDRAM
K4H641638N
Table 8 : Full Strength Driver Characteristics
Pull-down Current (mA)
Pull-up Current (mA)
Voltage
(V)
Typical
Low
Typical
High
Typical
Low
Typical
High
Minimum
Maximum
Minimum
Maximum
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
6.0
6.8
13.5
20.1
26.6
33.0
39.1
44.2
49.8
55.2
60.3
65.2
69.9
74.2
78.4
82.3
85.9
89.1
92.2
95.3
97.2
99.1
100.9
101.9
102.8
103.8
104.6
105.4
4.6
9.2
9.6
18.2
26.0
33.9
41.8
49.4
56.8
63.2
69.9
76.3
82.5
88.3
93.8
99.1
103.8
108.4
112.1
115.9
119.6
123.3
126.5
129.5
132.4
135.0
137.3
139.2
140.8
-6.1
-7.6
-14.5
-21.2
-27.7
-34.1
-40.5
-46.9
-53.1
-59.4
-65.5
-71.6
-77.6
-83.6
-89.7
-95.5
-101.3
-107.1
-112.4
-118.7
-124.0
-129.3
-134.6
-139.9
-145.2
-150.5
-155.3
-160.1
-4.6
-9.2
-10.0
-20.0
-29.8
-38.8
-46.8
-54.4
-61.8
-69.5
-77.3
12.2
18.1
24.1
29.8
34.6
39.4
43.7
47.5
51.3
54.1
56.2
57.9
59.3
60.1
60.5
61.0
61.5
62.0
62.5
62.9
63.3
63.8
64.1
64.6
64.8
65.0
-12.2
-18.1
-24.0
-29.8
-34.3
-38.1
-41.1
-41.8
-46.0
-47.8
-49.2
-50.0
-50.5
-50.7
-51.0
-51.1
-51.3
-51.5
-51.6
-51.8
-52.0
-52.2
-52.3
-52.5
-52.7
-52.8
13.8
18.4
23.0
27.7
32.2
36.8
39.6
42.6
44.8
46.2
47.1
47.4
47.7
48.0
48.4
48.9
49.1
49.4
49.6
49.8
49.9
50.0
50.2
50.4
50.5
-13.8
-18.4
-23.0
-27.7
-32.2
-36.0
-38.2
-38.7
-39.0
-39.2
-39.4
-39.6
-39.9
-40.1
-40.2
-40.3
-40.4
-40.5
-40.6
-40.7
-40.8
-40.9
-41.0
-41.1
-41.2
-85.2
-93.0
-100.6
-108.1
-115.5
-123.0
-130.4
-136.7
-144.2
-150.5
-156.9
-163.2
-169.6
-176.0
-181.3
-187.6
-192.9
-198.2
Rev. 1.4 August 2009
26 of 30
DDR SDRAM
K4H641638N
90
80
70
60
50
40
30
20
10
Maximum
Typical High
Typical Low
Minimum
0
0.0
1.0
2.0
Vout(V)
Pull-down Characteristics for Weak Output Driver
0.0
1.0
2.0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
Minumum
Typical Low
Typical High
Maximum
Vout(V)
Pull-up Characteristics for Weak Output Driver
Figure 5 : I/V characteristics for input/output buffers : Pull-down(above) and Pull-up(below)
Rev. 1.4 August 2009
27 of 30
DDR SDRAM
K4H641638N
Table 9 : Weak Driver Characteristics
Pull-down Current (mA)
Pull-up Current (mA)
Voltage
(V)
Typical
Low
Typical
High
Typical
Low
Typical
High
Minimum
Maximum
Minimum
Maximum
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3.4
6.9
3.8
7.6
2.6
5.2
7.8
5.0
9.9
-3.5
-6.9
-4.3
-8.2
-2.6
-5.2
-7.8
-5.0
-9.9
10.3
13.6
16.9
19.6
22.3
24.7
26.9
29.0
30.6
31.8
32.8
33.5
34.0
34.3
34.5
34.8
35.1
35.4
35.6
35.8
36.1
36.3
36.5
36.7
36.8
11.4
15.1
18.7
22.1
25.0
28.2
31.3
34.1
36.9
39.5
42.0
44.4
46.6
48.6
50.5
52.2
53.9
55.0
56.1
57.1
57.7
58.2
58.7
59.2
59.6
14.6
19.2
23.6
28.0
32.2
35.8
39.5
43.2
46.7
50.0
53.1
56.1
58.7
61.4
63.5
65.6
67.7
69.8
71.6
73.3
74.9
76.4
77.7
78.8
79.7
-10.3
-13.6
-16.9
-19.4
-21.5
-23.3
-24.8
-26.0
-27.1
-27.8
-28.3
-28.6
-28.7
-28.9
-28.9
-29.0
-29.2
-29.2
-29.3
-29.5
-29.5
-29.6
-29.7
-29.8
-29.9
-12.0
-15.7
-19.3
-22.9
-26.5
-30.1
-33.6
-37.1
-40.3
-43.1
-45.8
-48.4
-50.7
-52.9
-55.0
-56.8
-58.7
-60.0
-61.2
-62.4
-63.1
-63.8
-64.4
-65.1
-65.8
-14.6
-19.2
-23.6
-28.0
-32.2
-35.8
-39.5
-43.2
-46.7
-50.0
-53.1
-56.1
-58.7
-61.4
-63.5
-65.6
-67.7
-69.8
-71.6
-73.3
-74.9
-76.4
-77.7
-78.8
-79.7
10.4
13.0
15.7
18.2
20.8
22.4
24.1
25.4
26.2
26.6
26.8
27.0
27.2
27.4
27.7
27.8
28.0
28.1
28.2
28.3
28.3
28.4
28.5
28.6
-10.4
-13.0
-15.7
-18.2
-20.4
-21.6
-21.9
-22.1
-22.2
-22.3
-22.4
-22.6
-22.7
-22.7
-22.8
-22.9
-22.9
-23.0
-23.0
-23.1
-23.2
-23.2
-23.3
-23.3
Rev. 1.4 August 2009
28 of 30
DDR SDRAM
K4H641638N
70
60
50
40
30
20
10
Maximum
Minimum
0
0.0
1.0
2.0
Vout(V)
Pull-down Characteristics for Matched Output Driver
0.0
0
1.0
2.0
-10
-20
-30
-40
-50
-60
-70
Minumum
Maximum
Vout(V)
Pull-up Characteristics for Matched Output Driver
Figure 6 : I/V characteristics for input/output buffers:Pull-down(above) and Pull-up(below)
Rev. 1.4 August 2009
29 of 30
DDR SDRAM
K4H641638N
Table 10 : Matched Driver Characteristics
Pull-down Current(mA)
pull-up Current (mA)
Voltage
(V)
Minimum
Maximum
Minimum
Maximum
0
0.0
3.6
7.3
0.0
7.8
0.0
-4.4
-8.8
0.0
-8.8
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
15.8
23.1
29.4
35.5
41.0
46.1
50.5
53.8
57.3
60.1
-15.7
-23.0
-29.4
-35.4
-41.0
-46.0
-50.3
-53.8
-57.2
-60.1
11.0
14.6
16.8
18.3
18.8
19.0
19.6
19.7
19.8
-13.3
-17.3
-18.6
-18.9
-19.0
-19.3
-19.5
-19.6
-19.7
Rev. 1.4 August 2009
30 of 30
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