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K4M28163PH-RE [SAMSUNG]

2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA; 2米x 16Bit的×4银行移动SDRAM的54FBGA
K4M28163PH-RE
型号： K4M28163PH-RE
厂家： SAMSUNG    SAMSUNG
描述：

2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
2米x 16Bit的×4银行移动SDRAM的54FBGA

动态存储器
文件： 总12页 (文件大小：116K)
中文：  中文翻译
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K4M28163PH - R(B)E/G/C/F  
Mobile SDRAM  
2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA  
FEATURES  
GENERAL DESCRIPTION  
• 1.8V power supply.  
The K4M28163PH is 134,217,728 bits synchronous high data  
rate Dynamic RAM organized as 4 x 2,098,152 words by 16 bits,  
fabricated with SAMSUNG’s high performance CMOS technol-  
ogy. Synchronous design allows precise cycle control with the  
use of system clock and I/O transactions are possible on every  
clock cycle. Range of operating frequencies, programmable  
burst lengths and programmable latencies allow the same  
device to be useful for a variety of high bandwidth and high per-  
formance memory system applications.  
• LVCMOS compatible with multiplexed address.  
• Four banks operation.  
• MRS cycle with address key programs.  
-. CAS latency (1, 2 & 3).  
-. Burst length (1, 2, 4, 8 & Full page).  
-. Burst type (Sequential & Interleave).  
• EMRS cycle with address key programs.  
• All inputs are sampled at the positive going edge of the system  
clock.  
• Burst read single-bit write operation.  
• Special Function Support.  
-. PASR (Partial Array Self Refresh).  
-. Internal TCSR (Temperature Compensated Self Refresh)  
-. DS (Driver Strength)  
-. DPD (Deep Power Down)  
• DQM for masking.  
• Auto refresh.  
• 64ms refresh period (4K cycle).  
• Commercial Temperature Operation (-25°C ~ 70°C).  
• Extended Temperature Operation (-25°C ~ 85°C).  
• 54Balls FBGA ( -RXXX -Pb, -BXXX -Pb Free).  
ORDERING INFORMATION  
Part No.  
Max Freq.  
Interface  
Package  
K4M28163PH-R(B)E/G/C/F75  
K4M28163PH-R(B)E/G/C/F90  
K4M28163PH-R(B)E/G/C/F1L  
133MHz(CL3), 83MHz(CL2)  
111MHz(CL3), 83MHz(CL2)  
54 FBGA Pb  
(Pb Free)  
LVCMOS  
111MHz(CL3)*1, 66MHz(CL2)  
- R(B)E/G : Normal/Low Power, Extended Temperature(-25°C ~ 85°C)  
- R(B)C/F : Normal/Low Power, Commercial Temperature(-25°C ~ 70°C)  
Notes :  
1. In case of 40MHz Frequency, CL1 can be supported.  
Address configuration  
Organization  
Bank  
Row  
A0 - A11  
Column Address  
8M x 16  
BA0, BA1  
A0 - A8  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.  
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,  
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PRO-  
VIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.  
1. For updates or additional information about Samsung products, contact your nearest Samsung office.  
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could  
result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or pro-  
visions may apply.  
1
March 2006  
K4M28163PH - R(B)E/G/C/F  
Mobile SDRAM  
FUNCTIONAL BLOCK DIAGRAM  
LWE  
Data Input Register  
LDQM  
Bank Select  
2M x 16  
2M x 16  
2M x 16  
2M x 16  
DQi  
CLK  
ADD  
Column Decoder  
Latency & Burst Length  
LCKE  
Programming Register  
LWCBR  
LRAS  
LCBR  
LWE  
LCAS  
LDQM  
Timing Register  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
L(U)DQM  
2
March 2006  
K4M28163PH - R(B)E/G/C/F  
Mobile SDRAM  
Package Dimension and Pin Configuration  
< Bottom View*1 >  
< Top View*2 >  
E1  
9
8
7
6
5
4
3
2
1
54Ball(6x9) FBGA  
A
B
C
D
E
F
1
2
3
7
8
9
A
B
C
D
E
F
VSS  
DQ15 VSSQ VDDQ DQ0  
VDD  
DQ1  
DQ3  
DQ5  
DQ14 DQ13 VDDQ VSSQ DQ2  
DQ12 DQ11 VSSQ VDDQ DQ4  
DQ10  
DQ8  
DQ9 VDDQ VSSQ DQ6  
NC  
VSS  
CKE  
A9  
VDD LDQM DQ7  
UDQM CLK  
CAS  
BA0  
A0  
RAS  
BA1  
A1  
WE  
CS  
G
H
J
G
H
J
NC  
A8  
A11  
A7  
A6  
A10  
VDD  
VSS  
A5  
A4  
A3  
A2  
E
Pin Name  
CLK  
Pin Function  
System Clock  
Chip Select  
Clock Enable  
Address  
*2: Top View  
CS  
CKE  
A
0
~ A11  
~ BA  
A
BA  
0
1
Bank Select Address  
Row Address Strobe  
Column Address Strobe  
Write Enable  
A1  
RAS  
CAS  
WE  
z
b
*1: Bottom View  
L(U)DQM  
DQ  
Data Input/Output Mask  
Data Input/Output  
< Top View*2 >  
0
~ 15  
V
DD/VSS  
Power Supply/Ground  
Data Output Power/Ground  
V
DDQ/VSSQ  
#A1 Ball Origin Indicator  
[Unit:mm]  
Symbol  
Min  
Typ  
-
Max  
1.00  
-
A
A1  
E
-
0.25  
-
7.90  
8.00  
6.40  
8.00  
6.40  
0.80  
0.50  
-
8.10  
-
E1  
D
-
7.90  
8.10  
-
D1  
e
-
-
0.45  
-
-
b
0.55  
0.10  
z
3
March 2006  
K4M28163PH - R(B)E/G/C/F  
Mobile SDRAM  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
Value  
-1.0 ~ 2.6  
-1.0 ~ 2.6  
-55 ~ +150  
1.0  
Unit  
V
Voltage on any pin relative to Vss  
Voltage on VDD supply relative to Vss  
Storage temperature  
V
IN, VOUT  
V
DD, VDDQ  
V
T
STG  
°C  
W
Power dissipation  
P
D
Short circuit current  
I
OS  
50  
mA  
NOTES:  
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.  
Functional operation should be restricted to recommended operating condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.  
DC OPERATING CONDITIONS  
Recommended operating conditions (Voltage referenced to VSS = 0V, T = -25°C ~ 85°C for Extended, -25°C ~ 70°C for Commercial)  
A
Parameter  
Symbol  
Min  
1.7  
Typ  
1.8  
1.8  
1.8  
0
Max  
1.95  
1.95  
DDQ + 0.3  
0.3  
Unit  
V
Note  
V
DD  
DDQ  
IH  
1
Supply voltage  
V
1.7  
V
1
Input logic high voltage  
Input logic low voltage  
Output logic high voltage  
Output logic low voltage  
Input leakage current  
NOTES :  
V
0.8 x VDDQ  
-0.3  
V
V
2
V
IL  
V
3
V
OH  
V
DDQ -0.2  
-
-
V
I
OH = -0.1mA  
V
OL  
LI  
-
-
0.2  
V
I
OL = 0.1mA  
4
I
-2  
-
2
uA  
1. Under all conditions, VDDQ must be less than or equal to VDD.  
2. VIH (max) = 2.2V AC.The overshoot voltage duration is ≤ 3ns.  
3. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns.  
4. Any input 0V ≤ VIN ≤ VDDQ.  
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.  
5. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.  
CAPACITANCE (VDD = 1.8V, T = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)  
A
Pin  
Symbol  
Min  
1.5  
1.5  
1.5  
2.0  
Max  
3.5  
3.0  
3.0  
4.5  
Unit  
Note  
Clock  
C
CLK  
IN  
pF  
pF  
pF  
pF  
RAS, CAS, WE, CS, CKE, DQM  
Address  
C
C
ADD  
OUT  
DQ0 ~ DQ15  
C
4
March 2006  
K4M28163PH - R(B)E/G/C/F  
Mobile SDRAM  
DC CHARACTERISTICS  
Recommended operating conditions (Voltage referenced to VSS = 0V, T  
A
= -25°C ~ 85°C for Extended, -25°C ~ 70°C for Commercial)  
Version  
Parameter  
Symbol  
Test Condition  
Unit Note  
-75  
-90  
-1L  
Burst length = 1  
Operating Current  
(One Bank Active)  
I
CC1  
40  
35  
35  
mA  
mA  
1
t
I
RC ≥ tRC(min)  
= 0 mA  
O
I
CC2  
P
CKE ≤ VIL(max), tCC = 10ns  
0.3  
0.3  
Precharge Standby Current in  
power-down mode  
I
CC2PS CKE & CLK ≤ VIL(max), tCC = ∞  
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns  
I
CC2  
N
10  
1
Input signals are changed one time during 20ns  
Precharge Standby Current  
in non power-down mode  
mA  
mA  
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞  
Input signals are stable  
I
CC2NS  
I
CC3  
P
CKE ≤ VIL(max), tCC = 10ns  
5
1
Active Standby Current  
in power-down mode  
I
CC3PS CKE & CLK ≤ VIL(max), tCC = ∞  
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns  
I
CC3  
N
20  
10  
mA  
mA  
Active Standby Current  
in non power-down mode  
(One Bank Active)  
Input signals are changed one time during 20ns  
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞  
Input signals are stable  
I
CC3NS  
IO = 0 mA  
Operating Current  
(Burst Mode)  
Page burst  
4Banks Activated  
I
I
CC  
CC  
4
5
50  
90  
45  
85  
45  
85  
mA  
1
t
CCD = 2CLKs  
Refresh Current  
t
ARFC ≥ tARFC(min)  
mA  
2
3
45 *4  
85/70  
Internal TCSR  
Full Array  
°C  
150  
140  
135  
100  
90  
250  
210  
190  
200  
160  
140  
-E/C  
5
1/2 of Full  
1/4 of Full  
Full Array  
1/2 of Full  
1/4 of Full  
Self Refresh Current  
I
I
CC  
6
8
CKE ≤ 0.2V  
uA  
uA  
-G/F  
6
85  
Deep Power Down Current  
CC  
CKE ≤ 0.2V  
10  
7
NOTES:  
1. Measured with outputs open.  
2. Refresh period is 64ms.  
3. Internal TCSR can be supported.  
In comercial Temp : 45°C/Max 70°C. In extended Temp : 45°C/Max 85°C.  
4. It has +/-5 °C tolerance.  
5. K4M28163PH-S(D)E/C**  
6. K4M28163PH-S(D)G/F**  
7. DPD(Deep Power Down) function is an optional feature and it will be enabled upon request.  
Please contact Samsung for more information.  
8. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).  
5
March 2006  
K4M28163PH - R(B)E/G/C/F  
Mobile SDRAM  
AC OPERATING TEST CONDITIONS(VDD = 1.7V ∼ 1.95V, T  
A
= -25 ~ 85°C for Extended, -25 ~ 70°C for Commercial)  
Parameter  
Value  
0.9 x VDDQ / 0.2  
Unit  
V
AC input levels (Vih/Vil)  
Input timing measurement reference level  
Input rise and fall time  
0.5 x VDDQ  
tr/tf = 1/1  
V
ns  
V
Output timing measurement reference level  
Output load condition  
0.5 x VDDQ  
See Figure 2  
1.8V  
13.9KΩ  
Vtt=0.5 x VDDQ  
VOH (DC) = VDDQ - 0.2V, IOH = -0.1mA  
VOL (DC) = 0.2V, IOL = 0.1mA  
20pF  
Output  
50Ω  
10.6KΩ  
Output  
Z0=50Ω  
20pF  
Figure 1. DC Output Load Circuit  
Figure 2. AC Output Load Circuit  
6
March 2006  
K4M28163PH - R(B)E/G/C/F  
Mobile SDRAM  
OPERATING AC PARAMETER  
(AC operating conditions unless otherwise noted)  
Version  
Parameter  
Symbol  
Unit  
Note  
-75  
15  
-90  
-1L  
18  
27  
27  
50  
Row active to row active delay  
RAS to CAS delay  
t
t
RRD(min)  
RCD(min)  
18  
ns  
ns  
1
1
1
1
22.5  
22.5  
50  
24  
Row precharge time  
t
RP(min)  
RAS(min)  
RAS(max)  
RC(min)  
RDL(min)  
24  
ns  
t
50  
ns  
Row active time  
t
100  
us  
Row cycle time  
t
72.5  
74  
77  
ns  
1
2
Last data in to row precharge  
Last data in to Active delay  
Last data in to new col. address delay  
Last data in to burst stop  
t
15  
ns  
t
DAL(min)  
CDL(min)  
BDL(min)  
tRDL + tRP  
-
t
t
1
1
CLK  
CLK  
ns  
2
2
3
Auto refresh cycle time  
t
ARFC(min)  
SRFX(min)  
80  
120  
1
Exit self refresh to active command  
Col. address to col. address delay  
Number of valid output data  
Number of valid output data  
Number of valid output data  
t
ns  
t
CCD(min)  
CLK  
4
5
CAS latency=3  
CAS latency=2  
CAS latency=1  
2
ea  
1
-
0
NOTES:  
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next  
higher integer.  
2. Minimum delay is required to complete write.  
3. Maximum burst refresh cycle : 8  
4. All parts allow every cycle column address change.  
5. In case of row precharge interrupt, auto precharge and read burst stop.  
7
March 2006  
K4M28163PH - R(B)E/G/C/F  
Mobile SDRAM  
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)  
-75  
-90  
-1L  
Parameter  
Symbol  
Unit  
Note  
Min  
7.5  
12  
-
Max  
Min  
9
Max  
Min  
9
Max  
CAS latency=3  
CAS latency=2  
CAS latency=1  
CAS latency=3  
CAS latency=2  
CAS latency=1  
CAS latency=3  
CAS latency=2  
CAS latency=1  
t
t
t
CC  
CC  
CC  
CLK cycle time  
1000  
1000  
1000  
ns  
1
12  
-
15  
25  
t
t
t
SAC  
SAC  
SAC  
6
9
-
7
9
-
7
CLK to valid output delay  
Output data hold time  
ns  
ns  
1,2  
2
10  
20  
t
OH  
OH  
OH  
2.5  
2.5  
-
2.5  
2.5  
-
2.5  
2.5  
2.5  
3.0  
3.0  
2.0  
1
t
t
CLK high pulse width  
CLK low pulse width  
Input setup time  
t
CH  
CL  
SS  
SH  
SLZ  
2.5  
2.5  
2.0  
1
3.0  
3.0  
2.0  
1
ns  
ns  
ns  
ns  
ns  
3
3
3
3
2
t
t
Input hold time  
t
CLK to output in Low-Z  
t
1
1
1
CAS latency=3  
CAS latency=2  
CAS latency=1  
6
9
-
7
9
-
7
CLK to output in Hi-Z  
t
SHZ  
ns  
10  
20  
NOTES :  
1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.  
3. Assumed input rise and fall time (tr & tf) = 1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered,  
i.e., [(tr + tf)/2-1]ns should be added to the parameter.  
8
March 2006  
K4M28163PH - R(B)E/G/C/F  
Mobile SDRAM  
SIMPLIFIED TRUTH TABLE  
A11,  
Note  
COMMAND  
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP  
A9 ~ A0  
Register  
Refresh  
Mode Register Set  
Auto Refresh  
H
H
X
H
L
L
L
L
L
L
L
L
X
X
OP CODE  
X
1, 2  
3
H
Entry  
3
Self  
L
H
L
H
X
L
H
X
H
H
X
H
3
Refresh  
Exit  
L
H
H
H
X
X
X
X
X
X
3
Bank Active & Row Addr.  
V
V
Row Address  
Read &  
Column Address  
Auto Precharge Disable  
Auto Precharge Enable  
L
Column  
4
L
L
H
H
L
L
H
L
Address  
(A0~A8)  
H
4, 5  
Write &  
Column Address  
Auto Precharge Disable  
Auto Precharge Enable  
L
Column  
Address  
(A0~A8)  
4
H
X
X
V
H
4, 5  
Entry  
H
L
L
H
X
L
H
L
H
X
H
H
X
H
L
X
L
X
X
X
Deep Power Down  
Burst Stop  
X
X
Exit  
H
6
Bank Selection  
All Banks  
V
X
L
Precharge  
H
X
L
L
H
L
X
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry  
Exit  
H
L
L
H
L
X
X
X
Clock Suspend or  
Active Power Down  
X
X
X
H
L
Entry  
H
Precharge Power Down  
Mode  
H
L
Exit  
L
H
H
H
X
X
V
X
DQM  
X
X
7
H
L
X
H
X
H
No Operation Command  
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)  
NOTES :  
1. OP Code : Operand Code  
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)  
2. MRS can be issued only at all banks precharge state.  
A new command can be issued after 2 CLK cycles of MRS.  
3. Auto refresh functions are the same as CBR refresh of DRAM.  
The automatical precharge without row precharge command is meant by "Auto".  
Auto/self refresh can be issued only at all banks precharge state.  
Partial self refresh can be issued only after setting partial self refresh mode of EMRS.  
4. BA0 ~ BA1 : Bank select addresses.  
5. During burst read or write with auto precharge, new read/write command can not be issued.  
Another bank read/write command can be issued after the end of burst.  
New row active of the associated bank can be issued at tRP after the end of burst.  
6. Burst stop command is valid at every burst length.  
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency  
is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).  
9
March 2006  
K4M28163PH - R(B)E/G/C/F  
Mobile SDRAM  
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES  
Register Programmed with Normal MRS  
A9*2  
BA0 ~ BA1  
Address  
A11 ~ A10/AP  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
"0" Setting for  
Normal MRS  
Function  
RFU  
W.B.L  
Test Mode  
CAS Latency  
BT  
Burst Length  
Normal MRS Mode  
Test Mode  
CAS Latency  
Burst Type  
Type  
Burst Length  
A8 A7  
Type  
Mode Register Set  
Reserved  
A6 A5 A4  
Latency  
Reserved  
1
A3  
0
A2  
A1  
0
A0  
0
BT=0  
BT=1  
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sequential  
Interleave  
0
0
0
0
1
1
1
1
1
2
4
8
1
2
4
8
1
0
1
Reserved  
2
Mode Select  
1
0
Reserved  
3
BA1 BA0  
Mode  
1
1
Write Burst Length  
Length  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
Reserved Reserved  
Reserved Reserved  
Reserved Reserved  
Full Page Reserved  
Setting  
for Nor-  
mal MRS  
A9  
0
0
1
0
0
Burst  
1
0
1
Single Bit  
1
1
Register Programmed with Extended MRS  
Address  
BA1  
BA0  
A11 ~ A10/AP  
A9  
RFU*1  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
RFU*1  
Function  
Mode Select  
DS  
PASR  
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)  
Mode Select  
Mode  
Driver Strength  
PASR  
BA1  
BA0  
A6  
0
A5  
0
Driver Strength  
A2 A1 A0  
Size of Refreshed Array  
Full Array  
0
0
1
1
0
1
0
1
Normal MRS  
Reserved  
Full  
1/2  
1/4  
1/8  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1/2 of Full Array  
1/4 of Full Array  
Reserved  
EMRS for Mobile SDRAM  
Reserved  
1
0
1
1
Reserved Address  
Reserved  
A11~A10/AP  
0
A9  
0
A8  
0
A7  
0
A4  
0
A3  
0
Reserved  
Reserved  
Reserved  
NOTES:  
1.RFU(Reserved for future use) should stay "0" during MRS cycle.  
2.If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.  
10  
March 2006  
K4M28163PH - R(B)E/G/C/F  
Mobile SDRAM  
Partial Array Self Refresh  
1. In order to save power consumption, Mobile SDRAM has PASR option.  
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : full array, 1/2 of full array, 1/4 of full array.  
BA1=0  
BA0=0  
BA1=0  
BA0=1  
BA1=0  
BA0=0  
BA1=0  
BA0=1  
BA1=0  
BA0=0  
BA1=0  
BA0=1  
BA1=1  
BA0=0  
BA1=1  
BA0=1  
BA1=1  
BA0=0  
BA1=1  
BA0=1  
BA1=1  
BA0=0  
BA1=1  
BA0=1  
- 1/4 Array  
- Full Array  
- 1/2 Array  
Partial Self Refresh Area  
Internal Temperature Compensated Self Refresh (TCSR)  
Note :  
1. In order to save power consumption, Mobile-SDRAM includes the internal temperature sensor and control units to control the  
self refresh cycle automatically according to the two temperature range ; 45 °C and 85 °C(for Extended) / 70 °C(for Commercial).  
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.  
3. It has +/- 5 °C tolerance.  
Self Refresh Current (IDD6)  
Temperature Range  
- E / C  
1/2 Array  
140  
- G / F  
1/2 Array  
90  
Unit  
Full Array  
150  
1/4 Array  
135  
Full Array  
100  
1/4 Array  
85  
45 °C*3  
uA  
85/70 °C  
250  
210  
190  
200  
160  
140  
B. POWER UP SEQUENCE  
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.  
- Apply VDD before or at the same time as VDDQ.  
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.  
3. Issue precharge commands for all banks of the devices.  
4. Issue 2 or more auto-refresh commands.  
5. Issue a mode register set command to initialize the mode register.  
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.  
For operating with DS or PASR , set DS or PASR mode in EMRS setting stage.  
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not  
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.  
11  
March 2006  
K4M28163PH - R(B)E/G/C/F  
Mobile SDRAM  
C. BURST SEQUENCE  
1. BURST LENGTH = 4  
Initial Address  
Sequential  
Interleave  
A1  
0
A0  
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
2. BURST LENGTH = 8  
Initial Address  
Sequential  
Interleave  
A2  
0
A1  
0
A0  
0
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
0
0
1
6
7
0
1
2
3
4
0
3
2
5
4
7
6
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
12  
March 2006  

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