K4N56163QF-ZC2A0 [SAMSUNG]
DDR DRAM, 16MX16, 0.45ns, CMOS, PBGA84, LEAD FREE, FBGA-84;
| 型号： | K4N56163QF-ZC2A0 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 16MX16, 0.45ns, CMOS, PBGA84, LEAD FREE, FBGA-84 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总64页 (文件大小：1424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256M gDDR2 SDRAM
K4N56163QF-GC
256Mbit gDDR2 SDRAM
Revision 2.0
October 2005
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 2.0 Oct. 2005
- 1 -
256M gDDR2 SDRAM
K4N56163QF-GC
Revision History
Revision
Month
Year
History
- Target Spec
- Defined Target Specification
0.0
April
2004
- DC spec defined.
1.0
1.1
1.2
October
December
December
2004
2004
2004
- Changed VDD&VDDQ of K4N56163QF-GC20/22 from 1.8V+0.1V to 2.0V+0.1V
- Changed ICC2P and ICC6 to 10mA
- Changed the DC characteristics table
- Added 50 ohm at the EMRS(1) programming table.
1.3
1.4
1.5
1.6
1.7
January
February
March
April
2005
2005
2005
2005
2005
- Typo corrected
- Added Lead-Free part number in the datasheet.
- Removed K4N56163QF-GC20/22 from the datasheet.
- Modified Power-up and Initialization Sequence on page 22.
- Corrected typo.
April
- Changed speed bin organization.
(K4N56163QF-GC2A/K4N56163QF-GC33/K4N56163QF-GC36)
- 533 Speed bin changed into 550 speed bin.
- 600 speed bin is added.
- 667 speed bin changed into 700 speed bin.
- Seperated device operation and timing diagram
- Corrected typo.
1.8
May
2005
1.9
2.0
July
2005
2005
- Corrected typo.
- Corrected typo.
- Merged Device operation and Timing diagram
October
Rev. 2.0 Oct. 2005
- 2 -
256M gDDR2 SDRAM
K4N56163QF-GC
4M x 16Bit x 4 Banks graphic DDR2 Synchronous DRAM
with Differential Data Strobe
1.0 FEATURES
• 1.8V + 0.1V power supply for device operation
• 1.8V + 0.1V power supply for I/O interface
• 4 Banks operation
• Bi-directional Differential Data-Strobe
(Single-ended data-strobe is an optional feature)
• Off-chip Driver (OCD) Impedance Adjustment
• On Die Termination
• Posted CAS
• Programmable CAS Letency : 4,5,6 and 7
• Programmable Additive Latency : 0, 1, 2, 3. 4 and 5
• Write Latency (WL) = Read Latency (RL) -1
• Burst Legth : 4 and 8 (Interleave/nibble sequential)
• Programmable Sequential/ Interleave Burst Mode
• Refresh and Self Refresh
Average Refesh Period 7.8us at lower then TCASE 85×C,
3.9us at 85×C < TCASE < 95 ×C
• 84 ball FBGA
2.0 ORDERING INFORMATION
Part NO.
Max Freq.
Max Data Rate
800Mbps/pin
700Mbps/pin
600Mbps/pin
550Mbps/pin
Interface
Package
K4N56163QF-GC25
400MHz
350MHz
300MHz
275MHz
K4N56163QF-GC2A*
K4N56163QF-GC33
K4N56163QF-GC36*
SSTL
84 Ball FBGA
* K4N56163QF-GC2A/36 can fully cover previous K4N56163QF-GC30/37(667/533Mbps) product.
* K4N56163QF-ZC is the Lead-Free part number.
3.0 GENERAL DESCRIPTION
FOR 4M x 16Bit x 4 Bank gDDR2 SDRAM
The 256Mb gDDR2 SDRAM chip is organized as 4Mbit x 16 I/O x 4banks banks device. This synchronous device achieve high speed
graphic double-data-rate transfer rates of up to 1000Mb/sec/pin for general applications. The chip is designed to comply with the follow-
ing key gDDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD)
impedance adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a
source synchronous fashion. A thirteen bit address bus is used to convey row, column, and bank address information in a RAS/CAS
multiplexing style. For example, 256Mb(x16) device receive 13/9/2 addressing. The 256Mb gDDR2 devices operate with a single
1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The 256Mb gDDR2 devices are available in 84ball FBGAs(x16).
Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
Rev. 2.0 Oct. 2005
- 3 -
256M gDDR2 SDRAM
K4N56163QF-GC
4.0 PIN CONFIGURATION
Normal Package (Top View)
1
2
3
7
8
9
A
VSSQ
UDQS
VDDQ
UDQ2
VSSQ
UDQS
VSSQ
VDDQ
VDD
NC
VSS
UDM
UDQ6
VSSQ
UDQ1
B
C
UDQ7
VDDQ
VDDQ
UDQ3
VSS
VDDQ
UDQ4
VDD
UDQ0
D
E
F
VSSQ
LDQS
VSSQ
UDQ5
VDDQ
VSSQ
NC
LDQ6
VSSQ
LDQ1
LDM
LDQS
VDDQ
LDQ2
LDQ7
VDDQ
LDQ4
VDDQ
LDQ3
LDQ0
VSSQ
CK
VDDQ
G
H
J
VSSQ
VREF
CKE
LDQ5
VDDL
VSS
WE
VSSDL
RAS
VDD
ODT
K
CK
NC
L
BA0
A10
A3
BA1
A1
CAS
A2
CS
A0
A4
A8
M
N
P
VDD
VSS
VSS
A5
A6
A7
A9
A11
R
VDD
A12
NC
NC
NC
Note : VDDL and VSSDL are power and ground for the DLL. lt is recommended that
they are isolated on the device from VDD, VDDQ, VSS, and VSSQ.
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
Ball Locations
: Populated Ball
: Depopulated Ball
+
G
H
J
Top View
(See the balls through the Package)
K
L
+
+
+
+
+
+
M
N
P
R
Rev. 2.0 Oct. 2005
- 4 -
256M gDDR2 SDRAM
K4N56163QF-GC
5.0 PACKAGE DIMENSIONS (84 Ball FBGA)
11.00 ± 0.10
# A1 INDEX MARK (OPTIONAL)
6.40
0.80
1.60
4
9
8
7
6
5
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
3.20
(6.15)
(0.90)
(1.80)
84-∅0.45±0.05
∅0.2 M
A B
11.00 ± 0.10
#A1
0.35±0.05
MAX.1.20
Unit : mm
Rev. 2.0 Oct. 2005
- 5 -
256M gDDR2 SDRAM
K4N56163QF-GC
6.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the posi-
CK, CK
Input tive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
(both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input
buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation
(all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry
CKE
Input
and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-
down. Input buffers, excluding CKE, are disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selec-
CS
Input
tion on systems with multiple banks. CS is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the gDDR2
SDRAM. When enabled, ODT is only applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM
ODT
Input
signal for x16 configurations. The ODT pin will be ignored if the Extended Mode Register (EMRS) is pro-
grammed to disable ODT.
RAS, CAS, WE
(L)UDM
Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled
Input HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
Bank Address Inputs: BA0 and BA1 define to which bank an Actove, Read, Write or Precharge command
Input is being applied. BA0 also determines if the mode register or extended mode register is to be accessed dur-
ing a MRS or EMRS cycle.
BA0 - BA1
Address Inputs: Provided the row address for Active commands and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective bank.
Input A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during Mode Register Set commands.
A0 - A12
DQ
Input/
Data Input/ Output: Bi-directional data bus.
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write
data. LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. The data
Input/
LDQS,(LDQS)
UDQS,(UDQS)
strobes LDQS and UDQS may be used in single ended mode or paired with optional complementary sig-
Output
nals LDQS and UDQS to provide differential pair signaling to the system during both reads and writes. An
EMRS(1) control bit enables or disables all complementary data strobe signals.
No Connect: No internal electrical connection is present.
Supply DQ Power Supply: 1.8V ± 0.1V
NC/RFU
VDDQ
VSSQ
VDDL
VSSL
VDD
Supply DQ Ground
Supply DLL Power Supply: 1.8V ± 0.1V
Supply DLL Ground
Supply Power Supply: 1.8V ± 0.1V
Supply Ground
VSS
VREF
Supply Reference voltage
Rev. 2.0 Oct. 2005
- 6 -
256M gDDR2 SDRAM
K4N56163QF-GC
7.0 ABSOLUTE MAXIMUM DC RATINGS
Symbol
Parameter
Rating
Units
Notes
VDD
Voltage on VDD pin relative to Vss
- 1.0 V ~ 2.3 V
V
1
VDDQ
VDDL
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
V
V
1
1
V
IN, VOUT
V
1
TSTG
°C
1, 2
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-
2 standard.
8.0 AC & DC OPERATING CONDITIONS
8.1 Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
1.7
Typ.
1.8
Max.
1.9
VDD
Supply Voltage
V
V
VDDL
VDDQ
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
1.7
1.8
1.9
V
VREF
VTT
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1,2
3
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or
equal to VDD
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about
.
0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
8.2 Operating Temperature Condition
Symbol
Parameter
Rating
Units
Note
TOPER
Operating Temperature
0 to 95
°C
1, 2, 3
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51.2 standard.
2. At 0 - 85 °C, operation temperature range are the temperature which all DRAM specification will be supported.
3. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
8.3 Input DC & AC Logic Level
Input DC Logic Level
Symbol
Parameter
Min.
Max.
Units
Note
VIH(DC)
DC input logic high
DC input logic low
VREF + 0.125
VDDQ - 0.3
VDDQ + 0.3
VREF - 0.125
V
V
VIL(DC)
Input AC Logic Level
Symbol
Parameter
Min.
Max.
Units
Note
VIH(AC)
AC input logic high
-
V
VREF + 0.250
-
VIL(AC)
AC input logic low
VREF - 0.250
V
Rev. 2.0 Oct. 2005
- 7 -
256M gDDR2 SDRAM
K4N56163QF-GC
8.4 AC Input Test Conditions
Symbol
Condition
Input reference voltage
Value
0.5 * VDDQ
Units
V
Note
1
VREF
VSWING(MAX)
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
1.0
V
1
SLEW
Note :
V/ns
2, 3
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative
transitions.
V
V
V
V
DDQ
(AC) min
IH
IH
(DC) min
V
SWING(MAX)
REF
V (DC) max
IL
V (AC) max
IL
V
SS
delta TF
V
delta TR
Rising Slew =
V
(AC) min - V
delta TR
- V (AC) max
IL
IH
REF
REF
Falling Slew =
delta TF
< AC Input Test Signal Waveform >
8.5 Differential input AC logic Level
Symbol
Parameter
Min.
Max.
Units
Note
VID(AC)
AC differential input voltage
VDDQ + 0.6
V
1
0.5
VIX(AC)
AC differential cross point voltage
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
Note :
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or
UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to VIH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ .
VIX(AC) indicates the voltage at which differential input signals must cross.
VDDQ
VTR
Crossing point
VID
VIX or VOX
VCP
VSSQ
< Differential signal levels >
8.6 Differential AC output parameters
Symbol
Parameter
Min.
Max.
Units
Note
VOX(AC)
AC differential cross point voltage
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
Note :
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ .
VOX(AC) indicates the voltage at which differential output signals must cross.
Rev. 2.0 Oct. 2005
- 8 -
256M gDDR2 SDRAM
K4N56163QF-GC
8.7 OCD default characteristics
Description
Output impedance
Output impedance step size for OCD calibration
Pull-up and pull-down mismatch
Output slew rate
Parameter
Min
12.6
0
0
1.5
Nom
18
Max
23.4
1.5
4
Unit
ohms
ohms
ohms
V/ns
Note
1,2
6
1,2,3
Sout
5
1,4,5,6,7,8
Notes:
1. Absolute Specifications (0°C ≤ TCASE ≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for
values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV;
VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from VIL(AC) to VIH(AC).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaran-
teed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty.
Output slew rate load :
VTT
25 ohms
Output
(VOUT)
Reference
Point
7. DRAM output slew rate specification applies to 533Mb/sec/pin, 667Mb/sec/pin, 800Mb/sec/pin, 900Mbps/sec/pin and 1000Mbps/sec/pin speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.
8.8 DC characteristics
(Recommended operating conditions unless otherwise noted, 0°C ≤ Tc ≤85°C )
Version
Parameter
Symbol
Test Condition
Unit
-25
-2A
-33
-36
Burst Length=4 tRC ≥ tRC(min). IOL=0mA, tCC= tCC(min).
DQ,DM,DQS inputs changing twice per clock cycle. Address
and control inputs changing once per clock cycle
Operating Current
(One Bank Active)
ICC1
150
130
125
120
mA
Precharge Standby Current
in Power-down mode
ICC2P CKE ≤ VIL(max), tCC= tCC(min)
10
mA
mA
mA
Precharge Standby Current
in Non Power-down mode
CKE ≥ VIH(min), CS ≥ VIH(min),tCC= tCC(min)
ICC2N
45
50
45
50
40
45
40
45
Address and control inputs changing once per clock cycle
Active Standby Current
power-down mode
ICC3P CKE ≤ VIL(max), tCC= tCC(min)
CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) DQ,DM,DQS
ICC3N inputs changing twice per clock cycle. Address and control
inputs changing once per clock cycle
Active Standby Current in
in Non Power-down mode
85
85
80
80
mA
mA
IOL=0mA ,tCC= tCC(min),
Operating Current
( Burst Mode)
Page Burst, All Banks activated. DQ,DM,DQS inputs chang-
ICC4
300
190
290
180
270
170
260
160
ing twice per clock cycle. Address and control inputs changing
once per clock.
Refresh Current
ICC5
ICC6
tRC≥ tRFC
CKE ≤ 0.2V
mA
mA
Self Refresh Current
10
Burst Length=4 tRC ≥ tRC(min). IOL=0mA, tCC= tCC(min).
DQ,DM,DQS inputs changing twice per clock cycle. Address
and control inputs changing once per clock cycle
Operating Current
(4Bank interleaving)
ICC7
430
410
370
350
mA
Note :
1. Measured with outputs open and ODT off
Rev. 2.0 Oct. 2005
- 9 -
256M gDDR2 SDRAM
K4N56163QF-GC
8.9 Input/Output capacitance
- 2A
-33
- 36
- 25
Parameter
Symbol
Units
Min
1.0
x
1.0
x
Max
2.0
0.25
2.0
0.25
4.0
0.5
Min
1.0
x
1.0
x
Max
2.0
0.25
2.0
0.25
4.0
0.5
Min
1.0
x
1.0
x
Max
2.0
0.25
2.0
0.25
3.5
0.5
Input capacitance, CK and CK
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
Input/output capacitance delta, DQ, DM, DQS, DQS
CCK
CDCK
CI
CDI
CIO
pF
pF
pF
pF
pF
pF
2.5
x
2.5
x
2.5
x
CDIO
9.0 Electrical Characteristics & AC Timing for - 25/2A/33/36
(0 °C < TCASE < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
9.1 Refresh Parameters by Device Density
Parameter
Refresh to active/Refresh command time
Symbol
tRFC
256Mb
75
Units
ns
0 °C ≤ TCASE ≤ 85°C
7.8
µs
Average periodic refresh interval
tREFI
85 °C < TCASE ≤ 95°C
3.9
µs
9.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS
SPEED
Bin (CL-tRCD-tRP)
Parameter
CAS LATENCY
tCK
- 25
6-6-6
min
6
2.5
6
- 2A
5-5-5
min
5
2.86
5
-33
5-5-5
min
5
3.3
5
5
18
13
- 36
Units
4-5-5
min
4
3.6
5
5
16
11
tCK
ns
tCK
tCK
tCK
tCK
tRCD
tRP
6
5
tRC
22
18
tRAS
16
13
Rev. 2.0 Oct. 2005
- 10 -
256M gDDR2 SDRAM
K4N56163QF-GC
9.3 Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
- 25
max
-400 +400
- 2A
min max
-450 +450 -470 +470
- 33
- 36
min max
-500 +500
-450 +450
Parameter
Symbol
Units Notes
min
min
max
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
ps
ps
tDQSCK -350 +350 -400 +400 -420 +420
tCH
tCL
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
CK low-level width
min
(tCL,
tCH)
min
(tCL,
tCH)
min
(tCL,
tCH)
min
(tCL,
tCH)
CK half period
tHP
x
x
x
x
ps
20,21
24
15,16,
17
Clock cycle time, CL= x
tCK
tDH
2.5
8.0
x
2.86
8.0
x
3.3
8.0
x
3.6
8.0
x
ns
ps
DQ and DM input hold time
175
175
195
225
15,16,
17
DQ and DM input setup time
tDS
tIPW
tDIPW
tHZ
50
0.6
0.35
x
x
x
x
50
0.6
0.35
x
x
x
x
70
0.6
0.35
x
x
x
x
100
0.6
0.35
x
x
x
x
ps
tCK
tCK
ps
Control & Address input pulse width for
each input
DQ and DM input pulse width for each
input
Data-out high-impedance time from CK/
CK
tAC
max
tAC
max
tAC
max
tAC
max
tLZ
tAC
min
tAC
tAC
min
tAC
tAC
min
tAC
tAC
min
tAC
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
ps
27
27
(DQS)
max
max
max
max
2*tAC tAC 2*tAC tAC 2*tAC tAC 2* tAC tAC
min
tLZ(DQ)
ps
max
280
380
x
min
max
310
410
x
min
max
320
420
x
min
max
340
440
x
DQS-DQ skew for DQS and associated
DQ signals
DQ hold skew factor
tDQSQ
tQHS
tQH
x
x
x
x
ps
ps
ps
22
21
x
x
x
x
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
DQ/DQS output hold time from DQS
Write command to first DQS latching tran-
sition
WL
WL
WL
WL
WL
WL
WL
WL
tDQSS
tCK
-0.25 +0.25 -0.25 +0.25 -0.25 +0.25 -0.25 +0.25
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
tDSH
tMRD
0.35
0.35
0.2
0.2
2
x
x
x
x
x
0.35
0.35
0.2
0.2
2
x
x
x
x
x
0.35
0.35
0.2
0.2
2
x
x
x
x
x
0.35
0.35
0.2
0.2
2
x
x
x
x
x
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tWPST
tWPRE
0.4
0.35
0.6
x
0.4
0.35
0.6
x
0.4
0.35
0.6
x
0.4
0.35
0.6
x
19
Write preamble
14,16,
18
14,16,
18
Address and control input hold time
Address and control input setup time
tIH
tIS
250
175
x
x
325
200
x
x
345
220
x
x
375
250
x
x
ps
ps
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
tCK
tCK
28
28
Active to active command period for 1KB
page size products
Active to active command period for 2KB
page size products
tRRD
tRRD
7.5
10
x
x
7.5
10
x
x
7.5
10
x
x
7.5
10
x
x
ns
ns
12
12
Rev. 2.0 Oct. 2005
- 11 -
256M gDDR2 SDRAM
K4N56163QF-GC
- 25
max
- 2A
max
-33
- 36
max
Parameter
Symbol
Units Notes
min
2
6
min
2
5
min
2
5
max
min
2
4
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Internal read to precharge command delay tRTP
tCCD
tWR
tCK
tCK
x
x
x
x
x
x
tWR
+tRP
tWR
+tRP
tWR
tWR
+tRP
tDAL
x
x
x
tCK
23
11
+tRP
tWTR
3
3
x
3
3
x
3
3
2
2
x
tCK
tCK
tRFC +
10
200
tRFC +
10
200
tRFC +
10
200
tRFC +
10
200
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-
read command
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
tXSNR
tXSRD
tXP
ns
tCK
tCK
tCK
tCK
2
x
x
2
x
x
2
x
x
2
x
tXARD
2
2
2
2
x
9
tXARDS 6 - AL
6 - AL
6 - AL
6 - AL
9, 10
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
tCKE
3
3
3
2
3
2
3
2
tCK
tCK
tAOND
3
2
2
2
tAC
(max)+
0.7
tAC
(max)+
0.7
tAC
(max)+
0.7
tAC
(max)+
1
tAC
(min)
tAC
(min)
tAC
(min)
tAC
(min)
ODT turn-on
tAON
ns
13, 25
2tCK+
tAC(ma
x)+1
2tCK+
tAC(ma
x)+1
2tCK+
tAC(ma
x)+1
2tCK+t
AC(ma
x)+1
tAC
tAC
tAC
tAC
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAONPD
tAOFD
tAOF
ns
tCK
ns
(min)+2
(min)+2
(min)+2
(min)+2
3.5
3.5
2.5
2.5
2.5
2.5
2.5
2.5
tAC
(max)+
0.6
tAC
(max)+
0.6
tAC
(max)+
0.6
tAC
(max)+
0.6
tAC
(min)
tAC
(min)
tAC
(min)
tAC
(min)
ODT turn-off
26
2.5tCK
+
2.5tCK
+tAC(m
ax)+1
2.5tCK
+tAC(m
ax)+1
2.5tCK
+tAC(m
ax)+1
tAC(mi
n)+2
tAC(mi
n)+2
tAC(mi
n)+2
tAC(mi
ODT turn-off (Power-Down mode)
tAOFPD
ns
n)+2 tAC(ma
x)+1
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
3
8
0
3
8
0
tCK
tCK
ns
12
12
12
12
Minimum time clocks remains ON after
CKE asynchronously drops LOW
tIS+tC
K +tIH
tIS+tC
K +tIH
tIS+tC
K +tIH
tIS+tC
K +tIH
tDelay
ns
24
Note : General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals
(e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by
design, but is not necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to VREF + 250 mV for rising edges and from VREF
+ 125 mV and VREF - 250 mV for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250
mV to CK - CK = +500 mV (250mV to -500 mV for falling egdes).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential
strobe.
Rev. 2.0 Oct. 2005
- 12 -
256M gDDR2 SDRAM
K4N56163QF-GC
2. gDDR2 SDRAM AC timing reference load
Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise
representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (gen-
erally a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ
DQS
DQS
Output
DUT
VTT = VDDQ/2
Timing
reference
point
25Ω
<AC Timing Reference Load>
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig-
nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
3. gDDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in the following figure.
VDDQ
DUT
DQ
Output
DQS, DQS
VTT = VDDQ/2
25Ω
<Slew Rate Test Load>
Test point
4. Differential data strobe
gDDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode
bit; timing advantages of differential mode are realized in system design. The method by which the gDDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by
design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally
to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
t
t
DQSL
DQSH
DQS
DQS
DQS/
DQS
t
t
WPST
WPRE
VIH(dc)
VIL(dc)
VIH(ac)
DQ
DM
D
D
D
D
t
VIL(ac)
t
t
DH
DH
DS
t
DS
VIH(ac)
VIH(dc)
DMin
DMin
DMin
DMin
VIL(ac)
VIL(dc)
<Data input (write) timing>
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
t
QH
QH
<Data output (read) timing>
Rev. 2.0 Oct. 2005
- 13 -
256M gDDR2 SDRAM
K4N56163QF-GC
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
: Specific Notes for dedicated AC parameters
9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing.
tXARDS is expected to be used for slow active power down exit timing.
10. AL = Additive Latency
11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied.
12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency
13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns.
14. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or
tester correlation.
15. Timings are guaranteed with data, mask, and (DQS in singled ended mode) input slew rate of 1.0 V/ns.
16. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns
in differential strobe mode and a slew rate of 1V/ns in single ended mode.
17. tDS and tDH (data setup and hold) derating
1) Input waveform timing is referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to
the device under test.
2) Input waveform timing is referenced from the input signal crossing at the VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to
the device under test.
∆tDS, ∆tDH Derating Values (ALL units in ‘ps’, Note 1 applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
125
45
21
0
-
125
45
125
83
0
45
21
0
-
95
12
1
-
33
12
-2
-19
-42
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
83
0
-
83
21
-
-
-
-
0
0
24
13
-1
-19
-43
-
24
10
-7
-30
-59
-
-
-
-
-
-
-
-
-
-
DQ
Slew
rate
-11
-14
-11
-25
-
-14
-31
-
25
11
-7
-31
-74
-
22
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-13
-31
-
23
5
17
-6
-35
-77
-
-
-
-
-
-
-18
-47
-89
-
17
-7
-50
6
-
-
V/ns
-
-
-
-
-19
-62
-23
-65
5
-11
-53
-
-
-
-
-
-
-38
-
-
-
-
-
-
-
-
-127 -140 -115 -128 -103 -116
For all input signals the total tDS (setup time) and tDH(hold time) required is calculated by adding the datasheet tDS(base) and tDH(base) value to the
delta tDS and delta tDH derating value respectively. Example : tDS (total setup time) = tDS(base) + delta tDS.
Rev. 2.0 Oct. 2005
- 14 -
256M gDDR2 SDRAM
K4N56163QF-GC
18. tIS and tIH (input setup and hold) derating
1) Input waveform timing is referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to
the device under test.
2) Input waveform timing is referenced from the input signal crossing at the VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to
the device under test.
tIS, tIH Derating Values for DDR2 550
CK,CK Differential Slew Rate
Units
Notes
2.0 V/ns
1.5 V/ns
1.0 V/ns
∆tIS
+187
+179
+167
+150
+125
+83
0
∆tIH
+94
+89
+83
+75
+45
+21
0
∆tIS
+217
+209
+197
+180
+155
+113
+30
∆tIH
+124
+119
+113
+105
+75
+51
+30
+16
-1
∆tIS
+247
+239
+227
+210
+185
+143
+60
∆tIH
+154
+149
+143
+135
+105
+81
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+60
-11
-14
+19
+49
+46
Command
/Adress Slew
rate(V/ns)
-25
-31
+5
+35
+29
-43
-54
-13
-24
+17
+6
-67
-83
-37
-53
-7
-23
-110
-175
-285
-350
-525
-800
-125
-188
-292
-375
-500
-708
-80
-95
-50
-65
-145
-255
-320
-495
-770
-158
-262
-345
-470
-678
-115
-225
-290
-465
-740
-128
-232
-315
-440
-648
∆tIS and ∆tIH Derating Values for DDR2-600 DDR2-700, DDR2-800
CK,CK Differential Slew Rate
Units
Notes
2.0 V/ns
1.5 V/ns
1.0 V/ns
∆tIS
+150
+143
+133
+120
+100
+67
0
∆tIH
+94
+89
+83
+75
+45
+21
0
∆tIS
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
∆tIH
+124
+119
+113
+105
+75
∆tIS
+210
+203
+193
+180
+160
+127
+60
∆tIH
+154
+149
+143
+135
+105
+81
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+51
+30
+60
-5
-14
+16
+55
+46
Command
/Adress Slew
rate(V/ns)
-13
-31
-1
+47
29
-22
-54
-24
+38
+6
-34
-83
-4
-53
+26
-23
-60
-125
-188
-292
-375
-500
-708
-1125
-30
-95
0
-65
-100
-168
-200
-325
-517
-1000
-70
-158
-262
-345
-470
-678
-1095
-40
-128
-232
-315
-440
-648
-1065
-138
-170
-295
-487
-970
-108
-140
-265
-457
-940
Rev. 2.0 Oct. 2005
- 15 -
256M gDDR2 SDRAM
K4N56163QF-GC
19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater
than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the
clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.
21. tQH = tHP – tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately,
due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
22. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate
mismatch between DQS / DQS and associated DQ in any given cycle.
23. tDAL = (nWR) + ( tRP/tCK) :
For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period. nWR refers to the
tWR parameter stored in the MRS.
Example: For gDDR550 at t CK = 3.6 ns with tWR programmed to 4 clocks. tDAL = 4 + (18 ns / 3.6 ns) clocks =4 +(5)clocks=9clocks.
24. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency change during pre-
charge power-down, a specific procedure is required as described in gDDR2 device operation
25. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
26. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
27. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which
specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . Following figure shows a method to calculate the point when
device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are
not critical as long as the calculation is consistent.
28. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST),
or begins driving (tRPRE). Following figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving
(tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consis-
tent. These notes are referenced to the “Timing parameters by speed grade” tables for gDDR2-550/700 and gDDR2-800.
VTT + 2x mV
VTT + x mV
VOH + x mV
VOH + 2x mV
tLZ
tHZ
tRPRE begin point
tRPST end point
VTT - x mV
VTT - 2x mV
VOL + 2x mV
VOL + x mV
T1
T2
T2
T1
tHZ,tRPST end point = 2*T1-T2
tLZ,tRPRE begin point = 2*T1-T2
<Test method for tLZ, tHZ, tRPRE and tRPST>
Rev. 2.0 Oct. 2005
- 16 -
256M gDDR2 SDRAM
K4N56163QF-GC
29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the differ-
ential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a
falling signal applied to the device under test.
30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(dc) level to the differ-
ential data strobe crosspoint for a rising signal and VIL(dc) to the differential data strobe crosspoint for a falling signal applied to the device under
test.
Differential Input waveform timing
DQS
DQS
tDS
tDS
tDH
tDH
VDDQ
VIH(AC) min
V
IH(DC) min
VREF
VIL(DC) max
VIL(AC) max
VSS
<Data setup/hold timing>
31. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the
device under test.
32. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the
device under test.
CK
CK
tIS
tIS
tIH
tIH
VDDQ
VIH(AC) min
V
IH(DC) min
VREF
VIL(DC) max
VIL(AC) max
VSS
<Input setup/hold timing>
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the sin-
gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registeration. Thus, after any cKE transition, CKE may not transitioin from its valid level during the time period
of tIS + 2*tCK + tIH.
Rev. 2.0 Oct. 2005
- 17 -
256M gDDR2 SDRAM
K4N56163QF-GC
Device Operation &
Timing Diagram
Rev. 2.0 Oct. 2005
- 18 -
256M gDDR2 SDRAM
K4N56163QF-GC
Functional Description
Simplified State Diagram
Initialization
Sequence
CKEL
OCD
calibration
Self
Refreshing
SRF
CKEH
PR
(E)MRS
Idle
Setting
MRS
REF
All banks
Refreshing
precharged
EMRS
CKEL
CKEH
ACT
CKEL
Precharge
Power
Down
Activating
CKEL
CKEL
CKEL
Automatic Sequence
Command Sequence
Active
Power
Down
CKEH
CKEL
Write
Bank
Active
Read
Write
Read
WRA
RDA
Read
Reading
Writing
Write
RDA
WRA
RDA
WRA
PR, PRA
Writing
with
Reading
with
PR, PRA
PR, PRA
Autoprecharge
Autoprecharge
CKEL = CKE low, enter Power Down
CKEH = CKE high, exit Power Down, exit Self Refresh
Precharging
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
PR(A) = Precharge (All)
(E)MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Refresh
Note : Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and the commands to control
them, not all details. In particular situations involving more than one bank, enabling/disabling on-die termination, Power Down entry/
exit - among other things - are not captured in full detail.
Rev. 2.0 Oct. 2005
- 19 -
256M gDDR2 SDRAM
K4N56163QF-GC
Basic Functionality
Read and write accesses to the gDDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst
length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by
a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command
are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued.
Prior to normal operation, the gDDR2 SDRAM must be initialized. The following sections provide detailed information covering device
initialization, register definition, command descriptions and device operation.
Power up and Initialization
gDDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may
result in undefined operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT*1 at a low state (all other inputs may be undefined.) The
power voltage ramps are without any slope reversal, ramp time must be no greater than 20mS; and during the ramp,
VDD>VDDL>VDDQ and VDD-VDDQ<0.3 volts.
- VDD*2, VDDL*2 and VDDQ are driven from a single power converter output, AND
- VTT is limited to 0.95 V max, AND
- Vref tracks VDDQ/2.
or
- Apply VDD*2 before or at the same time as VDDL.
- Apply VDDL*2 before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & VREF
.
at least one of these two sets of conditions must be met.
2. Start clock and maintain stable condition.
3. For the minimum of 200µs after stable power and clock(CK, CK), then apply NOP or deselect & take CKE high.
4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period.
5. Issue EMRS(2) command. (To issue EMRS(2) command, provide “Low” to BA0, “High” to BA1.)
6. Issue EMRS(3) command. (To issue EMRS(3) command, provide “High” to BA0 and BA1.)
7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1 and A12.)
8. Issue a Mode Register Set command for “DLL reset”*2.
(To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1)
9. Issue precharge all command.
10. Issue 2 or more auto-refresh commands.
11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating parameters without
resetting the DLL.
12. At least 200 clocks after step 8, execute OCD Calibration ( Off Chip Driver impedance adjustment ).
If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Calibration Mode Exit com-
mand (A9=A8=A7=0) must be issued with other operating parameters of EMRS.
13. The gDDR2 SDRAM is now ready for normal operation.
*1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
*2) If DC voltage level of VDDL or VDD is intentionally changed during normal operation, (for example, for the purpose of VDD corner test, or power
saving) “DLL Reset” must be executed.
Rev. 2.0 Oct. 2005
- 20 -
256M gDDR2 SDRAM
K4N56163QF-GC
Initialization Sequence after Power Up
tCHtCL
CK
/CK
tIS
VIH(ac)
CKE
ODT
ANY
PRE
ALL
PRE
ALL
NOP
EMRS
MRS
REF
MRS
EMRS
REF
Command
EMRS
OCD
CMD
tRFC
tRP
tMRD
tRFC
tMRD
tMRD
400ns
tRP
Follow OCD
Flowchart
tOIT
min. 200 Cycle
DLL
RESET
DLL
OCD
ENABLE
Default
CAL. MODE
EXIT
Programming the Mode Register
For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR) are user defined variables
and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive
CAS latency, ODT(On Die Termination), single-ended strobe, and OCD(off chip driver impedance adjustment) are also user defined
variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register(MR) or
Extended Mode Registers(EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the user chooses to modify only
a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued.
MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed any time after
power-up without affecting array contents.
Rev. 2.0 Oct. 2005
- 21 -
256M gDDR2 SDRAM
K4N56163QF-GC
gDDR2 SDRAM Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of gDDR2 SDRAM. It controls CAS latency, burst length,
burst sequence, test mode, DLL reset, tWR and various vendor specific options to make gDDR2 SDRAM useful for various applications.
The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation.
The mode register is written by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~
A15. The gDDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. The mode reg-
ister set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can
be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge
state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and
8 bit burst lengths. The burst length decodes are compatible with gDDR SDRAM. Burst address sequence type is defined by A3, CAS
latency is defined by A4 ~ A6. The gDDR2 doesn’t support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset.
A7 must be set to low for normal MRS operation. Write recovery time tWR is defined by A9 ~ A11. Refer to the table for specific codes.
BA1
0
BA0
0
A12
PD
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
tWR*1
DLL
TM
CAS Latency
BT
Burst Length
Mode Register
Test Mode
Burst Type
A3
Active Power
A7
0
mode
Normal
Test
Type
A12
Down exit time
Fast exit (use tXARD)
Slow exit (use tXARDS)
0
1
Sequential
Interleave
0
1
1
BA1
BA0
MRS Mode
MRS
EMRS (1)
Burst Length
0
0
1
1
0
1
0
1
DLL
A8
0
A2
0
A1
1
A0 Burst Length
0
1
DLL Reset
No
4
8
EMRS (2) : Reserved
EMRS (3) : Reserved
0
1
1
Yes
CAS Latency
A6 A5 A4 Latency
Write Recovery for Auto Precharge
A11
0
A10 A9
MRS Select
Reserved
Reserved
3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
Reserved
0
4
4
5
6
7
1
5
1
1
1
Reserved
Reserved
Reserved
*1 : WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock cycles
is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to the next integer
(WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is also used with tRP to determine tDAL.
Rev. 2.0 Oct. 2005
- 22 -
256M gDDR2 SDRAM
K4N56163QF-GC
gDDR2 SDRAM Extended Mode Register Set
EMRS(1)
The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and addi-
tive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after
power-up for proper operation. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0, while
controlling the states of address pins A0 ~ A12. The gDDR2 SDRAM should be in all bank precharge with CKE already high prior to writ-
ing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write opera-
tion to the extended mode register. Mode register contents can be changed using the same command and clock cycle requirements
during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a
half strength data-output driver. A3~A5 determines the additive latency, A2 and A6 are used for ODT value selection, A7~A9 are used
for OCD control, A10 is used for DQS# disable.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal oper-
ation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically re-
enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a
Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchro-
nization to occur may result in a violation of the tAC or tDQSCK parameters.
EMRS(2)
The extended mode register(2) controls refresh related features. The default value of the extended mode register(2) is not defined,
therefore the extended mode register(2) must be written after power-up for proper operation. The extended mode register(2) is written
by asserting low on CS, RAS, CAS, WE, high on BA1 and low on BA0, while controlling the ststes of address pins A0 ~ A15. The gDDR2
SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register(2). The mode register set
command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register(2). Mode register contents
can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the pre-
charge state.
Rev. 2.0 Oct. 2005
- 23 -
256M gDDR2 SDRAM
K4N56163QF-GC
EMRS (1) Programming
BA1
0
BA0
1
A12
Qoff
A11
0
A10
A9
A8
A7
A6
Rtt
A5
A4
A3
A2
Rtt
A1
A0
DQS
OCD Program
Additive Latency
D.I.C
DLL
A0
0
1
DLL Enable
Enable
Disable
BA1 BA0
MRS mode
MRS
EMRS(1)
A10
0
1
DQS
Enable
Disable
A6
0
0
1
1
A2
0
1
0
1
Rtt (NOMINAL)
ODT Disabled
75 ohm
0
0
1
1
0
1
0
1
EMRS(2): Reserved
EMRS(3): Reserved
150 ohm
50 ohm
Strobe Function
Matrix
Output Driver
Driver
A10
A1
Impedance Control
Normal
Size
100%
60%
(DQS Enable)
DQS
DQS
DQS
DQS
DQS
Hi-z
0
1
0 (Enable)
1 (Disable)
Weak
Qoff (Optional)a
Output buffer enabled
Output buffer disabled
A12
A9 A8 A7 OCD Calibration Program
A5
0
0
0
0
A4
0
0
1
1
A3
0
1
0
1
Additive Latency
OCD Calibration mode exit;
0
1
2
3
4
0
1
0
0
0
maintain setting
Drive(1)
0
0
1
0
1
0
1
0
0
a. Outputs disabled - DQs, DQSs, DQSs .
This feature is used in conjunction with
dimm IDD meaurements when IDDQ is
not desired to be included.
Drive(0)
Adjust modea
1
1
0
0
0
1
OCD Calibration default b
1
1
1
5a
a: When Adjust mode is issued, AL from previously
set value must be applied.
b: After setting to default, OCD mode needs to be
exited by setting A9-A7 to 000. Refer to the follow-
ing 3.2.2.3 section for detailed information.
1
1
1
1
0
1
Reserved
Reserved
a. AL 5 option is available only for 256Mb gDDR2.
Rev. 2.0 Oct. 2005
- 24 -
256M gDDR2 SDRAM
K4N56163QF-GC
EMRS (2) Programming
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0*1
0*1
0*1
PSAR*2
SRF
1
Extended Mode Register(2)
BA1 BA0
MRS mode
MRS
EMRS(1)
A7
1
0
High Temperature Self-Refresh Rate Enable
0
0
1
1
0
1
0
1
Enable
Disable
EMRS(2)
EMRS(3): Reserved
A2 A1 A0 Partial Array Self Refresh for 4 Banks
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full array
Half Array(BA[1:0]=00&01)
Quarter Array(BA[1:0]=00)
Not defined
3/4 array(BA[1:0]=01, 10&11)
Half array(BA[1:0]=10&11)
Quarter array(BA[1:0]=11)
Not defined
*1 : The rest bits in EMRS(2) is reserved for future use and all bits except A0, A1, A2, A7and BA0, BA1, must be programmed
to 0 when setting the mode register during initialization.
.
*2 : If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be
loast if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command
is issued. PASR is supported from the device of 90nm technology(512Mb C-die).
EMRS (3) Programming : Reserved*1
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
0*1
A5
A4
A3
A2
A1
A0
Address Field
1
1
Extended Mode Register(3)
*1 : All bits in EMRS(3) except BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the
mode register during initialization.
Rev. 2.0 Oct. 2005
- 25 -
256M gDDR2 SDRAM
K4N56163QF-GC
Off-Chip Driver (OCD) Impedance Adjustment
gDDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence. Every calibration mode com-
mand should be followed by “OCD calibration mode exit” before any other command being issued. MRS should be set before entering
OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depending on system environment.
MRS shoud be set before entering OCD impedance adjustment and ODT should be
carefully controlled depending on system environment
Start
EMRS: OCD calibration mode exit
EMRS: Drive(1)
EMRS: Drive(0)
DQ & DQS High; DQS Low
DQ & DQS Low; DQS High
ALL OK
ALL OK
Test
Test
Need Calibration
Need Calibration
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS :
EMRS :
Enter Adjust Mode
Enter Adjust Mode
BL=4 code input to all DQs
Inc, Dec, or NOP
BL=4 code input to all DQs
Inc, Dec, or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
Rev. 2.0 Oct. 2005
- 26 -
256M gDDR2 SDRAM
K4N56163QF-GC
Extended Mode Register Set for OCD impedance adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by gDDR2 SDRAM
and drive of DQS is dependent on EMRS bit enabling DQS operation. In Drive(1) mode, all DQ, DQS signals are driven high and all DQS
signals are driven low. In drive(0) mode, all DQ, DQS signals are driven low and all DQS signals are driven high. In adjust mode, BL = 4
of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value
of 18 ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are specified in
section 6. OCD applies only to normal full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default output
driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not
applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS commands not intended to adjust
OCD characteristics must specify A9-A7 as '000' in order to maintain the default or calibrated value.
Off- Chip-Driver program
A9
0
A8
0
A7
0
Operation
OCD calibration mode exit
0
0
1
0
1
0
1
0
0
Drive(1) DQ, DQS high and DQS low
Drive(0) DQ, DQS low and DQS high
Adjust mode
1
1
1
OCD calibration default
OCD impedance adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code to gDDR2
SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and
controllers must drive this burst code to all DQs at the same time. DT0 in the following table means all DQ bits at bit time 0, DT1 at bit
time 1, and so forth. The driver output impedance is adjusted for all gDDR2 SDRAM DQs simultaneously and after OCD calibration, all
DQs of a given gDDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and
when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the 16 step
range. When Adjust mode command is issued, AL from previously set value must be applied.
Off- Chip-Driver program
4bit burst code inputs to all DQs
Operation
DT0
DT1
DT2
DT3
Pull-up driver strength
Pull-down driver strength
0
0
0
0
1
0
0
1
1
0
0
0
1
0
1
1
0
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
NOP (No operation)
Increase by 1 step
Decrease by 1 step
NOP
NOP (No operation)
NOP
NOP
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Increase by 1 step
Decrease by 1 step
Decrease by 1 step
NOP
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Decrease by 1 step
Other Combinations
Reserved
For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the following timing diagram. For
input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by MRS addressing mode (ie. sequential or interleave).
Rev. 2.0 Oct. 2005
- 27 -
256M gDDR2 SDRAM
K4N56163QF-GC
OCD adjust mode
OCD calibration mode exit
NOP
EMRS
NOP
CMD
EMRS
NOP
NOP
NOP
NOP
CK
CK
WL
WR
DQS
DQS_in
tDS tDH
V
(AC)
IH
V
(DC)
IH
DQ_in
DM
DT0 DT1 DT2 DT3
V
(AC)
IL
V
(DC)
IL
Drive Mode
Drive mode, both Drive(1) and Drive(0), is used for controllers to measure gDDR2 SDRAM Driver impedance. In this mode, all outputs
are driven out tOIT after “enter drive mode” command and all output drivers are turned-off tOIT after “OCD calibration mode exit” com-
mand as the following timing diagram.
OCD calibration mode exit
Enter Drive mode
CMD
EMRS
NOP
NOP
NOP
EMRS
CK
CK
Hi-Z
Hi-Z
DQS
DQS
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive(0)
DQs high for Drive(1)
DQs low for Drive(0)
DQ
tOIT
tOIT
Rev. 2.0 Oct. 2005
- 28 -
256M gDDR2 SDRAM
K4N56163QF-GC
ODT (On Die Termination)
On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance. For x16 configuration ODT is applied to
each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal via the ODT control pin. The ODT feature is designed to improve signal
integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM
devices. The ODT function is supported for ACTIVE and STANDBY modes, and turned off and not supported in SELF REFRESH mode.
Functional Representation of ODT
VDDQ
VDDQ
sw1
VDDQ
Switch (sw1, sw2, sw3) is enabled by ODT pin.
Selection among sw1, sw2 and sw3 is determined by “Rtt (nominal)” in EMRS
Termination included on all DQs, DM, DQS, DQS, RDQS, and RDQS pins.
sw3
Rval3
sw2
Rval2
Rval1
DRAM
Input
Buffer
Input
Pin
Rval3
Rval1
sw1
Rval2
sw3
VSSQ
sw2
VSSQ
VSSQ
ODT DC Electrical Characteristics
Parameter/Condition
Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm
Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm
Rtt mismatch tolerance between any pull-up/pull-down pair
Note 1: Test condition for Rtt measurements
Symbol
Rtt1(eff)
Rtt2(eff)
Rtt(mis)
Min
60
120
-3.75
Nom
75
150
Max
90
180
Units Notes
ohm
ohm
%
1
1
1
+3.75
Measurement Definition for Rtt(eff): Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH (AC)) and I( VIL (AC)) respec-
tively. VIH (AC), VIL (AC), and VDDQ values defined in SSTL_18
2 x Vm
VDDQ
V
(AC) - V (AC)
IL
IH
- 1
x 100%
delta VM =
Rtt(eff) =
I(V (AC)) - I(V (AC))
IH
IL
Measurement Definition for VM : Measure voltage (VM) at test pin (midpoint) with no load.
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
ODT timing for active/standby mode
T0
CK
T1
T2
T3
T4
T5
T6
CK
CKE
t
IS
t
IS
V
(AC)
IH
ODT
V
(AC)
IL
t
AOFD
t
AOND
Internal
RTT
t
AON,max
Term Res.
t
AOF,min
AON,min
t
t
AOF,max
ODT timing for powerdown mode
T0
CK
T1
T2
T3
T4
T5
T6
CK
CKE
t
t
IS
IS
V
(AC)
IH
ODT
V (AC)
IL
t
AOFPD,max
t
AOFPD,min
Internal
RTT
Term Res.
t
AONPD,min
t
AONPD,max
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
ODT timing mode switch at entering power down mode
T-5
T-4
T-3
T-2
T-1
T0
T1
T2
T3
T4
CK
CK
t
ANPD
t
IS
CKE
Entering Slow Exit Active Power Down Mode
or Precharge Power Down Mode.
t
IS
ODT
VIL(AC)
Active & Standby mode
timings to be applied.
t
AOFD
RTT
Internal
Term Res.
t
IS
ODT
VIL(AC)
Power Down mode tim-
ings to be applied.
t
AOFPDmax
Internal
Term Res.
RTT
t
IS
VIH(AC)
ODT
t
AOND
Active & Standby mode
timings to be applied.
Internal
Term Res.
RTT
t
IS
VIH(AC)
ODT
Power Down mode tim-
ings to be applied.
t
AONPDmax
Internal
Term Res.
RTT
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
ODT timing mode switch at exiting power down mode
T0
T1
T4
T5
T6
T7
T8
T9
T10
T11
CK
CK
t
IS
t
AXPD
VIH(AC)
CKE
Exiting from Slow Active Power Down Mode
or Precharge Power Down Mode.
t
IS
ODT
V
IL(AC)
Active & Standby mode
timings to be applied.
t
AOFD
Internal
Term Res.
RTT
t
IS
ODT
Power Down mode tim-
ings to be applied.
V
IL(AC)
t
AOFPDmax
Internal
Term Res.
RTT
t
IS
VIH(AC)
Active & Standby mode
timings to be applied.
ODT
t
AOND
Internal
Term Res.
RTT
t
IS
VIH(AC)
ODT
Power Down mode tim-
ings to be applied.
t
AONPDmax
Internal
Term Res.
RTT
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Bank Activate Command
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in gDDR2 SDRAM. In this
operation, the gDDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command (or
any time during the RAS-CAS-delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is
issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses
to issue a R/W command before the tRCDmin, then AL (greater than 0) must be written into the EMR(1). The Write Latency (WL) is
always defined as RL - 1 (read latency -1) where read latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL).
Read or Write operations using AL allow seamless bursts (refer to seamless operation timing diagram examples in Read burst and
Write burst section)
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
. . . . . . . . . .
CK / CK
Internal RAS-CAS delay (>= t
Bank A
)
RCDmin
Bank B
Col. Addr.
Bank A
Row Addr.
Bank A
Row Addr.
Bank B
Bank A
. . . . . . .
Bank B
Addr.
ADDRESS
Col. Addr.
Row Addr.
Addr.
CAS-CAS delay time (t
additive latency delay (
)
)
CCD
RCD =1
AL
Read Begins
RAS - RAS delay time (>= t
)
RRD
Post CAS
Read B
Post CAS
Bank B
Activate
Bank A
Activate
Bank B
Precharge
Bank A
Active
Bank A
. . . . . .
Read A
COMMAND
Precharge
Bank Active (>= t
)
Bank Precharge time (>= tRP
)
)
: “H” or “L”
RAS
RAS Cycle time (>= tRC
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock’s rising
edge. WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low).
The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a serial read or write operation on successive
clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip
has a page length of 2048 bits (defined by CA0-CA9, CA11). The page length of 2048 is divided into 512 or 256 uniquely addressable boundary segments
depending on burst length, 512 for 4 bit burst, 256 for 8 bit burst respectively. A 4-bit or 8 bit burst operation will occur entirely within one of the 512 or 256
groups beginning with the column address supplied to the device during the Read or Write Command (CA0-CA9, CA11). The second, third and fourth
access will also occur within this group segment, however, the burst order is a function of the starting address, and the burst sequence.
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL = 8 setting, two cases of interrupt
by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundry respectively. The min-
imum CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles.
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Posted CAS
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read
cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. gDDR2 SDRAM supports 4 bit
burst and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address order-
ing is nibble based for ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the
address bit 3 (A3) of the MRS, which is similar to the DDR SDRAM operation. Seamless burst read or write operations are supported.
Unlike DDR devices, interruption of a burst read or write cycle during BL = 4 mode operation is prohibited. However in case of BL = 8
mode, interruption of a burst read or write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write.
Therefore the Burst Stop command is not supported on gDDR2 SDRAM devices.
Examples of posted CAS operation
Example 1 Read followed by a write to the same bank
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
CK/CK
Write
Active
Read
A-Bank
A-Bank
CMD
A-Bank
WL = RL -1 = 4
CL = 3
AL = 2
> = tRCD
DQS/DQS
RL = AL + CL = 5
> = tRAC
Dout2 Dout3
Din0Din1Din2Din3
Dout0 Dout1
DQ
Example 2 Read followed by a write to the same bank
[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
CK/CK
AL = 0
Write
Active
Read
A-Bank
A-Bank
A-Bank
CMD
CL = 3
WL = RL -1 = 2
DQS/DQS
> = tRCD
RL = AL + CL = 3
> = tRAC
Din1 Din3
Din2
Dout2 Dout3
Din0
Dout0 Dout1
DQ
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Burst Mode Operation
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The
address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the
first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle
before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS).
Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an
additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS), similar to the existing SDR and DDR
SDRAMs. The AL is defined by the Extended Mode Register Set (1)(EMRS(1)).
gDDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the setting of the EMRS
“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the gDDR2 SDRAM
pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling
edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data
strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 Kohm
resis-tor to insure proper operation.
Burst Length and Sequence
BL = 4
Burst Length
Starting Address (A1 A0)
Sequential Addressing (decimal)
Interleave Addressing (decimal)
0 0
0 1
1 0
1 1
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
4
BL = 8
Burst Length
Starting Address (A2 A1 A0)
Sequential Addressing (decimal)
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
Interleave Addressing (decimal)
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
8
Note : Page length is a function of I/O organization and column addressin
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Burst Read Command
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The
address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to
(AL + CL -1). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle
must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for
write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or
8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the
burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (WR).
gDDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the setting of the EMRS
“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the gDDR2 SDRAM
pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling
edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data
strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10K ohm
resistor to insure proper operation.
t
t
CL
CH
CK
CK
CK
DQS
DQS
DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
t
QH
QH
Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
DQS
Posted CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
=< t
DQSCK
AL = 2
CL =3
RL = 5
DQs
DOUTA
DOUTA DOUTA DOUTA
3
0
1
2
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Burst Read Operation: RL = 3 (AL = 0 and CL = 3, BL = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
DQS
CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
=< t
DQSCK
CL =3
RL = 3
DQs
DOUT A0
DOUT A4
DOUT A1
DOUT A2
DOUT A3
DOUT A5
DOUT A6
DOUT A7
Burst Read followed by Burst Write: RL = 5, WL = (RL-1) = 4, BL = 4
T0
T1
Tn-1
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
CK/CK
CMD
DQS
Post CAS
READ A
Post CAS
WRITE A
(Read to Write turn around time)
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t
RTW
RL =5
WL = RL - 1 = 4
DQ’s
DOUT A0
DIN A0
DOUT A1
DOUT A2
DOUT A3
DIN A1
DIN A2
DIN A3
The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around-time, which is 4
clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
DQS
Post CAS
READ A4
Post CAS
READ A0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CL =3
AL = 2
RL = 5
DQs
DOUT A0
DOUT A4
DOUT A5 DOUT A6
DOUT A1 DOUT A2 DOUT A3
The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, and every 4
clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
Burst read can only be interrupted by another read with 4 bit burst boundary. Any other case of read interrupt is not allowed.
Read Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, BL=8)
CK/CK
Read B
Read A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CMD
DQS/DQS
DQs
A0
A1
A2
A3
B0
B1
B2
B3
B4
B5
B6
B7
Notes:
1. Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write command or Precharge command is prohibited.
3. Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst interrupt timings are prohibited.
4. Read burst interruption is allowed to any bank inside DRAM.
5. Read burst with Auto Precharge enabled is not allowed to interrupt.
6. Read burst interruption is allowed by another Read with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, Minimum Read to
Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt).
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Burst Write Operation
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine
the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1);and is the number of clocks of
delay that are required from the time the write command is registered to the clock edge associated to the first DQS strobe. A data strobe signal (DQS)
should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the
DQS following the preamble. The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge during write cycles.
The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When t he burst
has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time
from the completion of the burst write to bank precharge is the write recovery time (WR).
DDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the setting of the EMRS “Enable DQS” mode
bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode de-
pendent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at the specified AC/DC levels. In
differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods
is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must
be tied externally to VSS through a 20 ohm to 10K ohm resistor to insure proper operation.
tDQSH
tDQSL
DQS
DQS/
DQS
DQS
tWPRE
tWPST
VIH(ac)
VIH(dc)
DQ
DM
D
D
D
D
VIL(ac)
VIL(dc)
tDH
DMin
tDH
tDS
DMin
tDS
VIH(ac)
VIH(dc)
DMin
DMin
VIL(dc)
VIL(ac)
Burst Write Operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
Tn
CK/CK
CMD
DQS
DQs
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
< = t
NOP
NOP
NOP
Precharge
Completion of
the Burst Write
DQSS
WL = RL - 1 = 4
> = WR
DIN A
DIN A DIN A DIN A
3
0
1
2
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Burst Write Operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4
T0
CK/CK
T1
T2
T3
T4
T5
T6
T7
Tn
CAS
NOP
NOP
< = t
NOP
NOP
Completion of
NOP
Precharge
NOP
Bank A
Activate
CMD
DQS
DQs
WRITE A
DQSS
the Burst Write
WL = RL - 1 = 2
> = tRP
> = WR
DIN A0
DIN A1
DIN A2
DIN A3
Burst Write followed by Burst Read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK/CK
CMD
Write to Read = CL - 1 + BL/2 + tWTR
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
CL = 3
AL = 2
WL = RL - 1 = 4
RL =5
> = tWTR
DQ
DOUT A0
DOUT A1 DOUT A2 DOUT A3
The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 + tWTR]. This tWTR is not a
write recovery time (tWR) but the time required to transfer the 4bit write data from the input buffer into sense amplifiers in the array.
tWTR is defined in AC spec table of this data sheet.
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Seamless Burst Write Operation: RL = 5, WL = 4, BL=4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
DQS
Post CAS
WRITE A1
Post CAS
WRITE A0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WL = RL - 1 = 4
DQ’s
DIN A
DIN A DIN A DIN A
3
DIN A
DIN A DIN A DIN A
1 2 3
0
0
1
2
The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four clocks
for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
Writes intrrupted by a write
Burst write can only be interrupted by another write with 4 bit burst boundary. Any other case of write interrupt is not allowed.
Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8)
CK/CK
NOP
Write A
Write B
NOP
NOP
NOP
NOP
NOP
NOP
CMD
NOP
DQS/DQS
DQs
B6
A2
B2
B3
B4
B5
B7
A0
A1
A3
B0
B1
Notes:
1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or Precharge command is prohibited.
3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt timings are prohibited.
4. Write burst interruption is allowed to any bank inside DRAM.
5. Write burst with Auto Precharge enabled is not allowed to interrupt.
6. Write burst interruption is allowed by another Write with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, minimum Write to
Precharge timing is WL+BL/2+tWR where tWR starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end.
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Write data mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on gDDR2 SDRAMs, Consistent with the implementation on
gDDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally
loaded identically to data bits to insure matched system timing. DM of x16 bit organization is not used during read cycles.
Data Mask Timing
DQS/
DQS
DQ
VIH(ac)
VIH(ac)
VIL(ac)
VIH(dc)
V
VIL(dc)
(dc)
IH
DM
(ac) V (dc)
VIL
IL
tDS tDH
tDS tDH
Data Mask Function, WL=3, AL=0, BL = 4 shown
Case 1 : min tDQSS
CK
CK
Write
COMMAND
tWR
tDQSS
DQS/DQS
DQ
DM
Case 2 : max tDQSS
tDQSS
DQS/DQS
DQ
DM
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when
CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each
bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 for 256Mb are used to define which bank to pre-
charge when the command is issued.
Bank Selection for Precharge by Address Bits
Precharged
A10
BA1
BA0
Remarks
Bank(s)
LOW
LOW
LOW
LOW
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
All Banks
HIGH
HIGH
DON’T CARE
DON’T CARE
Burst Read Operation Followed by Precharge
Minimum Read to precharge command spacing to the same bank = AL + BL/2 clocks.
For the earliest possible precharge, the precharge command may be issued on the rising edge which is “Additive latency(AL) + BL/2
clocks” after a Read command. A new bank active (command) may be issued to the same bank after the RAS precharge time (tRP). A
precharge command cannot be issued until tRAS is satisfied.
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-
bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4 this is the time from the actual
read (AL after the Read command) to Precharge command. For BL = 8 this is the time from AL + 2 clocks after the Read to the Pre-
charge command.
Example 1: Burst Read Operation Followed by Precharge:
RL = 4, AL = 1, CL = 3, BL = 4, tRTP <= 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Bank A
Active
Post CAS
READ A
NOP
NOP
NOP
Precharge
NOP
NOP
NOP
AL + BL/2 clks
> = t
RP
CL = 3
AL = 1
RL =4
DQ’s
DOUT A0
DOUT A1 DOUT A2 DOUT A3
> = t
RAS
CL =3
> = t
RTP
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Example 2: Burst Read Operation Followed by Precharge:
RL = 4, AL = 1, CL = 3, BL = 8, tRTP <= 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
NOP
AL + BL/2 clks
CL = 3
AL = 1
RL =4
DQ’s
DOUT A4
DOUT A0
DOUT A5 DOUT A6 DOUT A8
DOUT A1 DOUT A2 DOUT A3
> = t
RTP
second 4-bit prefetch
first 4-bit prefetch
Example 3: Burst Read Operation Followed by Precharge :
RL = 5, AL = 2, CL = 3, BL = 4, tRTP <= 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Bank A
Posted CAS
READ A
Precharge A
NOP
NOP
NOP
NOP
NOP
NOP
Activate
AL + BL/2 clks
> = t
RP
AL = 2
CL =3
RL =5
> = t
DQ’s
DOUT A0
DOUT A1 DOUT A2 DOUT A3
CL =3
RAS
> = t
RTP
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Example 4: Burst Read Operation Followed by Precharge :
RL = 6, AL = 2, CL = 4, BL = 4, tRTP <= 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Bank A
Post CAS
READ A
Precharge A
NOP
NOP
NOP
NOP
NOP
NOP
Activate
AL + BL/2 Clks
> = t
RP
AL = 2
CL =4
RL = 6
> = t
DQ’s
DOUT A0
DOUT A1 DOUT A2 DOUT A3
CL =4
RAS
> = t
RTP
Example 5: Burst Read Operation Followed by Precharge :
RL = 4, AL = 0, CL = 4, BL = 8, tRTP > 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Bank A
Activate
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
AL + 2 Clks + max{tRTP;2 tCK}*
> = t
RP
CL =4
RL = 4
AL = 0
DQ’s
DOUT A0
DOUT A4
DOUT A5 DOUT A6 DOUT A8
DOUT A1 DOUT A2 DOUT A3
> = t
RAS
> = t
RTP
second 4-bit prefetch
first 4-bit prefetch
* : rounded to next integer
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Burst Write followed by Precharge
Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR For write cycles, a delay must be satisfied
from the completion of the last burst write cycle until the Precharge Command can be issued. This delay is known as a write recovery
time (tWR) referenced from the completion of the burst write to the precharge command. No Precharge command should be issued
prior to the tWR delay.
Example 1 : Burst Write followed by Precharge: WL = (RL-1) =3, BL=4
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
DQs
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
NOP
Completion of the Burst Write
> = tWR
WL = 3
DIN A0
DIN A1
DIN A2
DIN A3
Example 2 : Burst Write followed by Precharge: WL = (RL-1) = 4, BL=4
T0
T1
T2
T3
T4
T5
T6
T7
T 9
CK/CK
CMD
DQS
DQs
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
NOP
Completion of the Burst Write
> = tWR
WL = 4
DIN A0
DIN A1
DIN A2
DIN A3
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the
auto-precharge function. When a Read or a Write Command is given to the gDDR2 SDRAM, the CAS timing accepts one extra address,
column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or
write cycle. If A10 is low when the READ or WRITE Command is issued, then normal Read or Write burst operation is executed and the
bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-
precharge function is engaged. During auto-precharge, a Read Command will execute as normal with the exception that the active bank
will begin to precharge on the rising edge which is CAS latency (CL) clock cycles before the end of the read burst.
Auto-precharge also be implemented during Write commands. The precharge operation engaged by the Auto precharge command will
not begin until the last data of the burst write sequence is properly stored in the memory array.
This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS latency)
thus improving system performance for random data access. The RAS lockout circuit internally delays the Precharge operation until the
array restore operation has been completed (tRAS satisfied) so that the auto precharge command may be issued with any read or write
command.
Burst Read with Auto Precharge
If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The gDDR2 SDRAM starts an
auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than the read with AP command if tRAS(min) and tRTP are
satisfied.
If tRAS(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tRAS(min) is satisfied.
If tRTP(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tRTP(min) is satisfied.
In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next rising
clock edge after this event). So for BL = 4 the minimum time from Read_AP to the next Activate command becomes AL + (tRTP + tRP)*
(see example 2) for BL = 8 the time from Read_AP to the next Activate is AL + 2 + (tRTP + tRP)*, where “*” means: “rouded up to the
next integer”. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch.
A new bank activate (command) may be issued to the same bank if the following two conditions are satisfied simultaneously.
(1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Example 1: Burst Read Operation with Auto Precharge:
RL = 4, AL = 1, CL = 3, BL = 8, tRTP <= 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Bank A
Activate
Post CAS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ A
Autoprecharge
AL + BL/2 clks
> = t
RP
CL = 3
AL = 1
RL =4
DQ’s
DOUT A4
DOUT A0
DOUT A5 DOUT A6 DOUT A8
DOUT A1 DOUT A2 DOUT A3
> = t
RTP
second 4-bit prefetch
first 4-bit prefetch
t
Precharge begins here
RTP
Example 2: Burst Read Operation with Auto Precharge:
RL = 4, AL = 1, CL = 3, BL = 4, tRTP > 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Bank A
Activate
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Autoprecharge
> = AL + tRTP + tRP
CL = 3
AL = 1
RL =4
DQ’s
DOUT A0
DOUT A1 DOUT A2 DOUT A3
4-bit prefetch
t
t
RP
RTP
Precharge begins here
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Example 3: Burst Read with Auto Precharge Followed by an activation to the Same Bank
(tRC Limit):
RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, tRTP <= 2 clocks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
DQS
A10 = 1
Bank A
Post CAS
READ A
NOP
NOP
> = tRas(min)
NOP
NOP
NOP
NOP
NOP
Activate
Auto Precharge Begins
> = tRP
AL = 2
CL =3
RL = 5
DQ’s
DOUT A0
DOUT A1 DOUT A2 DOUT A3
CL =3
> = tRC
Example 4: Burst Read with Auto Precharge Followed by an Activation to the Same Bank
(tRP Limit):
RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, tRTP <= 2 clocks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
DQS
A10 = 1
Bank A
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Activate
> = tRas(min)
Auto Precharge Begins
> = tRP
AL = 2
CL =3
RL = 5
DQ’s
DOUT A0
DOUT A1 DOUT A2 DOUT A3
CL =3
> = tRC
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Burst Write with Auto-Precharge
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The gDDR2 SDRAM automatically
begins precharge operation after the completion of the burst write plus write recovery time (tWR). The bank undergoing auto-precharge
from the completion of the write burst may be reactivated if the following two conditions are satisfied.
(1) The data-in to bank activate delay time (WR + tRP) has been satisfied.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Burst Write with Auto-Precharge (tRC Limit): WL = 2, tWR =2, tRP=3, BL=4
T0
T1
T2
T3
T4
T5
T6
T7
Tm
CK/CK
A10 = 1
Bank A
Active
Post CAS
NOP
NOP
NOP
NOP
NOP
NOP
CMDWRA BankA
NOP
Auto Precharge Begins
Completion of the Burst Write
DQS/DQS
DQs
> = tRP
> = WR
WL =RL - 1 = 2
DIN A
DIN A DIN A DIN A
3
0
1
2
> = tRC
Burst Write with Auto-Precharge (tWR + tRP): WL = 4, tWR =2, tRP=3, BL=4
T0
T3
T4
T5
T6
T7
T8
T9
T12
CK/CK
A10 = 1
Bank A
Active
Post CAS
NOP
NOP
NOP
NOP
NOP
CMDWRA Bank A
DQS/DQS
DQs
NOP
Auto Precharge Begins
NOP
Completion of the Burst Write
> = WR
WL =RL - 1 = 4
DIN A
> = tRP
DIN A DIN A DIN A
3
0
1
2
> = tRC
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Precharge & Auto Precharge Clarification
Minimum Delay beween”From Com-
mand” to “To Command”
From Command
To Command
Unit
Note
Precharge ( to same Bank as Read w/AP)
Precharge All
Precharge ( to same Bank as Write w/AP)
Precharge All
Precharge ( to same Bank as Precharge)
Precharge All
Precharge
AL + BL/2 + tRTP - 2 * tCK
AL + BL/2 + tRTP - 2 * tCK
WL + BL/2 + WR
WL + BL/2 + WR
1 * tCK
clks
clks
clks
clks
clks
clks
clks
clks
1, 2
1, 2
2
2
2
2
2
2
Read w/AP
Write w/AP
Precharge
1 * tCK
1 * tCK
1 * tCK
Precharge All
Note :
Precharge All
1. The value of tRTP is decided by the equation : max( RU<tRTP/tCK>, 2) where RU stands for round up. This is required to cover the max tCK case,
which is 8 ns.
2. For a given bank, the precharge period of tRP should be counted from the latest precharge command issued to that bank. Similarly, the precharge
period of tRPall should be counted from the latest precharge all command ossued to the DRAM.
Refresh Command
When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Refresh mode (REF). All banks
of the gDDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Refresh command (REF) can
be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external
address bus is required once this cycle has started.
When the refresh cycle has completed, all banks of the gDDR2 SDRAM will be in the precharged (idle) state. A delay between the
Refresh command (REF) and the next Activate command or subsequent Refresh command must be greater than or equal to the
Refresh cycle time (tRFC).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided.
A maximum of eight Refresh commands can be posted to any given gDDR2 SDRAM, meaning that the maximum absolute interval
between any Refresh command and the next Refresh command is 9 * tREFI.
T0
T1
T2
T3
Tm
Tn
Tn + 1
CK/CK
High
> = t
> = t
> = t
RFC
CKE
RFC
RP
Precharge
NOP
REF
REF
NOP
ANY
NOP
CMD
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Self Refresh Operation
The gDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by hav-
ing CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh
command, by either driving ODT pin low or using EMRS command. Once the Command is registered, CKE must be held low to keep the
device in Self Refresh mode. When the gDDR2 SDRAM has entered Self Refresh mode all of the external signals except CKE, are
“don’t care”. Since CKE is an SSTL 2 input, VREF must be maintained during Self Refresh operation. The DRAM initiates a minimum of
one one Auto Refresh command internally within tCKE period once it enters Self Refresh mode. The clock is internally disabled during
Self Refresh Operation to save power. The minimum time that the gDDR2 SDRAM must remain in Self Refresh mode is tCKE. The user
may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock
must be restarted and stable before the device can exit Self Refresh operation. Once Self Refresh Exit command is registered, a delay
equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must remain high
for the entire Self Refresh exit period tXSRD for proper operation. Upon exit from Self Refresh, the gDDR2 SDRAM can be put back into
Self Refresh mode after tXSRD expires. NOP or deselect commands must be registered on each positive clock edge during the Self
Refresh exit interval. ODT should also be turned off during tXSRD. Upon exit from Self Refresh, the gDDR2 SDRAM requires a mini-
mum of one extra auto refresh command before it is put back into Self Refresh mode.
T3
T4
T5
T6
T0
T1
T2
Tm
Tn
tCK
tCH tCL
CK
CK
> = tXSNR
> = tXSRD
tRP*
VIH(AC)
CKE
ODT
VIL(AC)
tIS
tIS
tAOFD
VIL(AC)
tIS
tIH
tIS
VIH(AC)
VIL(AC)
VIH(DC)
Self
Refresh
Valid
NOP
NOP
NOP
CMD
VIL(DC)
- Device must be in the “All banks idle” state prior to entering Self Refresh mode.
- ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again when tXSRD timing is satisfied.
- tXSRD is applied for a Read or a Read with autoprecharge command.
- tXSNR is applied for any command except a Read or a Read with autoprecharge command.
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Power-Down
Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE is not allowed to go
low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low
while any of other operations such as row activation, precharge or autoprecharge, or auto-refresh is in progress, but power-down IDD
spec will not be applied until finishing those operations. Timing diagrams are shown in the following pages with details for entry into
power down.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for
proper read operation. DRAM design guarantees it’s DLL in a locked state with any CKE intensive operations as long as DRAM control-
ler complies with DRAM specifications. Following figures show two examples of CKE intensive applications. In both examples, DRAM
maintains DLL in a locked state throughout the period.
<Example of CKE instensive environment 1>
CK
CK
CKE
tCKE
tCKE
tCKE
tCKE
tCKE
DRAM guarantees all AC and DC timing & voltage specifications and proper DLL operation with intensive CKE operation
<Example of CKE Iintensive enviroment 2>
CK
CK
CKE
tXP
tXP
CMD
REF
REF
tREFI = 7.8 us
The pattern shown above can repeat over a long period of time. With this pattern, DRAM guarantees all DRAM
guarantees all AC and DC timing & voltage specifications and DLL operation with temperature and voltage drift.
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs
when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates
the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering precharge power-
down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down
mode, CKE low and a stable clock signal must be maintained at the inputs of the gDDR2 SDRAM, and ODT should be in
a valid state but all other input signals are “Don’t Care”. CKE low must be maintained until tCKE has been satisfied.
Power-down duration is limited by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command).
CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-
down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined at AC spec table of
this data sheet.
Basic Power Down Entry and Exit timing diagram
CK/CK
tIH
VIH(DC)
tIS
tIH
tIS
tIH
tIH
tIS tIH
tIS
VIH(AC)
VIH(DC)
VIH(AC)
VIH(DC)
VIH(AC)
CKE
VIL(DC)
VIL(AC)
VALID
VALID
VALID
NOP
VALID
NOP
Command
tXP, tXARD,
tXARDS
tCKE
tCKE
tCKE
Enter Power-Down mode
Don’t Care
Exit Power-Down mode
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Read to power down entry
T0
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6 Tx+7
Tx+8
Tx+9
CK
CK
Read operation starts with a read command and
CKE should be kept high until the end of burst operation.
CMD
CKE
DQ
RD
BL=4
AL + CL
Q
Q
Q
Q
DQS
DQS
T0
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6 Tx+7
Tx+8
Tx+9
CMD
CKE
RD
BL=8
CKE should be kept high until the end of burst operation.
AL + CL
DQ
Q
Q
Q
Q
Q
Q
Q
Q
DQS
DQS
Read with Autoprecharge to power down entry
T0
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6 Tx+7
Tx+8
Tx+9
CK
CK
CMD
RDA
PRE
BL=4
AL + BL/2
with tRTP = 7.5ns
CKE should be kept high
until the end of burst operation.
& tRAS min satisfied
CKE
DQ
AL + CL
Q
Q
Q
Q
DQS
DQS
T0
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6 Tx+7
Tx+8
Tx+9
Start internal precharge
CMD
RDA
PRE
AL + BL/2
BL=8
with tRTP = 7.5ns
CKE should be kept high
& tRAS min satisfied
until the end of burst operation.
CKE
DQ
AL + CL
Q
Q
Q
Q
Q
Q
Q
Q
DQS
DQS
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Write to power down entry
T0
T1
Tm
Tm+1 Tm+2 Tm+3 Tx
Tx+1
Tx+2
Ty
Ty+1
Ty+2
Ty+3
CK
CK
CMD
WR
BL=4
CKE
WL
D
D
D
D
DQ
DQS
DQS
tWTR
T0
T1
Tm
Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx
Tx+1 Tx+2
Tx+3
Tx+4
CMD
CKE
DQ
WR
BL=8
WL
D
D
D
D
D
D
D
D
tWTR
DQS
DQS
Write with Autoprecharge to power down entry
T0
T1
Tm
Tm+1 Tm+2 Tm+3 Tx
Tx+1
Tx+2
Tx+3 Tx+4
Tx+5
Tx+6
CK
CK
CMD
WRA
PRE
BL=4
CKE
DQ
WL
D
D
D
D
WR*1
DQS
DQS
T0
T1
Tm
Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx
Tx+1 Tx+2
Tx+3
Tx+4
CK
CK
CMD
WRA
PRE
BL=8
CKE
DQ
WL
D
D
D
D
D
D
D
D
*1
WR
DQS
DQS
* 1: WR is programmed through MRS
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Refresh command to power down entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
CK
CMD
REF
CKE can go to low one clock after an Auto-refresh command
CKE
Active command to power down entry
CMD
CKE
ACT
CKE can go to low one clock after an Active command
Precharge/Precharge all command to power down entry
PR or
CMD
PRA
CKE can go to low one clock after a Precharge or Precharge all command
CKE
MRS/EMRS command to power down entry
MRS or
CMD
EMRS
CKE
tMRD
Asynchronous CKE Low Event
DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this data sheet. If CKE asynchronously drops “LOW”
during any valid operation DRAM is not guaranteed to preserve the contents of array. If this event occurs, memory controller must sat-
isfy DRAM timing specification tDelay before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised
“HIGH” again. DRAM must be fully re-initialized (steps 4 thru 13) as described in initialization sequence. DRAM is ready for normal oper-
ation after the initialization sequence. See AC timing parametric table for tDelay specification.
Stable clocks
tCK
CK#
CK
tDelay
CKE
tIS
CKE asynchronously drops low
Clocks can be turned
off after this point
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256M gDDR2 SDRAM
K4N56163QF-GC
Input Clock Frequency Change during Precharge Power Down
gDDR2 SDRAM input clock frequency can be changed under following condition :
gDDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2
clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input clock frequency is allowed to change
only within minimum and maximum operating frequency specified for the particular speed grade. During input clock frequency change,
ODT and CKE must be held at stable LOW levels. Once input clock frequency is changed, stable new clocks must be provided to
DRAM before precharge power down may be exited and DLL must be RESET via EMRS after precharge power down exit. Depending
on new clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc.. During DLL re-lock
period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock frequency.
Clock Frequency Change in Precharge Power Down Mode
T0
T1
T2
T4
Tx
Tx+1
Ty
Ty+1
Ty+2 Ty+3 Ty+4
Tz
CK
CK
DLL
NOP
NOP
NOP
NOP
NOP
Valid
CMD
CKE
RESET
Frequency Change
Occurs here
200 Clocks
ODT
tRP
tAOFD
tXP
ODT is off during
DLL RESET
Stable new clock
before power down exit
Minimum 2 clocks
required before
changing frequency
No Operation Command
The No Operation Command should be used in cases when the gDDR2 SDRAM is in an idle or a wait state. The purpose of the No
Operation Command (NOP) is to prevent the gDDR2 SDRAM from registering any unwanted commands between operations. A No
Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation
Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought
high at the rising edge of the clock, the RAS, CAS, and WE signals become don’t cares.
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256M gDDR2 SDRAM
K4N56163QF-GC
Command Truth Table
CKE
BA0
BA1
Function
CS
RAS
CAS
WE
A11
A10
A9 - A0 Note
Previous Current
Cycle
Cycle
(Extended) Mode Register Set
Refresh (REF)
Self Refresh Entry
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
L
L
X
H
L
L
L
L
X
H
H
H
H
L
L
L
L
H
X
X
H
X
H
L
H
H
X
H
L
L
H
L
BA
X
X
OP Code
1,2
1
1,8
X
X
X
X
X
X
Self Refresh Exit
L
H
X
X
X
X
1,7
Single Bank Precharge
Precharge all Banks
Bank Activate
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
BA
X
X
X
L
H
X
X
1,2
1
1,2
L
L
BA
BA
BA
BA
BA
X
Row Address
Write
H
H
H
H
H
X
X
H
X
H
Column
Column
Column
Column
X
L
H
L
H
X
X
Column 1,2,3
Column 1,2,3
Column 1,2,3
Column 1,2,3
Write with Auto Precharge
Read
Read with Auto-Precharge
No Operation
L
H
H
H
X
X
H
X
H
X
X
1
1
Device Deselect
X
X
Power Down Entry
H
L
L
X
X
X
X
X
X
X
X
1,4
1,4
Power Down Exit
Note :
H
1. All gDDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.
2. Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write"
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. “X” means “H or L (but a defined logic level)”.
7. Self refresh exit is asynchronous.
8. VREF must be maintained during Self Refresh operation.
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256M gDDR2 SDRAM
K4N56163QF-GC
Clock Enable (CKE) Truth Table for Synchronous Transitions
CKE
Command (N) 3
Current State 2
Action (N) 3
Previous Cycle 1 Current Cycle 1
Note
RAS, CAS, WE, CS
(N-1)
L
L
L
L
H
H
H
(N)
L
H
L
H
L
L
X
Maintain Power-Down
Power Down Exit
Maintain Self Refresh
Self Refresh Exit
11, 13, 15
4, 8, 11,13
11, 15
Power Down
DESELECT or NOP
X
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
REFRESH
Self Refresh
Bank(s) Active
All Banks Idle
4, 5,9
Active Power Down Entry
Precharge Power Down Entry
Self Refresh Entry
4,8,10,11,13
4, 8, 10,11,13
6, 9, 11,13
7
L
H
H
Refer to the Command Truth Table
Note :
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be
issued only after tXSRD (200 clocks) is satisfied.
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.
10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or Precharge operations
are in progress. See section "Power Down" and "Self Refresh Command" for a detailed list of restrictions.
11. Minimum CKE high time is three clocks.; minimum CKE low time is three clocks.
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined.
14. CKE must be maintained high while the SDRAM is in OCD calibration mode .
15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high or low in Power Down if
the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1) ).
16. VREF must be maintained during Self Refresh operation.
DM Truth Table
Name (Functional)
Write enable
DM
-
H
DQs
Valid
X
Note
1
1
Write inhibit
Note :
1. Used to mask write data, provided coincident with the corresponding data
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256M gDDR2 SDRAM
K4N56163QF-GC
Input Signal Overshoot/Undershoot Specification
AC Overshoot/Undershoot Specification for Address and Control Pins A0-A15, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT
Specification
Parameter
- 36
0.9V
- 2A
0.9V
0.9V
0.45 V-ns
0.45 V-ns
Maximum peak amplitude allowed for overshoot area (See following figyre):
Maximum peak amplitude allowed for undershoot area (See following figure):
Maximum overshoot area above VDD (See following figure).
0.9V
0.56 V-ns
0.56 V-ns
Maximum undershoot area below VSS (See following figure).
Maximum Amplitude
Overshoot Area
Undershoot Area
VDD
Volts
(V)
VSS
Maximum Amplitude
Time (ns)
AC Overshoot and Undershoot Definition for Address and Control Pins
AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Pins DQ, DQS, DM, CK, CK
Specification
Parameter
- 36
0.9V
0.9V
0.28 V-ns
0.28 V-ns
-2A
0.9V
0.9V
0.23 V-ns
0.23 V-ns
Maximum peak amplitude allowed for overshoot area (See following figure):
Maximum peak amplitude allowed for undershoot area (See following figure):
Maximum overshoot area above VDDQ (See following figure):
Maximum undershoot area below VSSQ (See following figure):
Maximum Amplitude
Overshoot Area
VDDQ
Volts
(V)
VSSQ
Undershoot Area
Maximum Amplitude
Time (ns)
AC Overshoot and Undershoot Definition for Clock, Data, Strobe, and Mask Pins
Rev. 2.0 Oct. 2005
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256M gDDR2 SDRAM
K4N56163QF-GC
Table 1. Full Strength Default Pulldown Driver Characteristics
Pulldown Current (mA)
Nominal Default Low (18 Nominal Default High(18
Minimum
Maximum
Voltage (V)
(23.4 Ohms)
ohms)
11.3
16.5
21.2
25.0
28.3
30.9
33.0
34.5
35.5
36.1
36.6
36.9
37.1
37.4
37.6
37.7
37.9
ohms)
11.8
16.8
22.1
27.6
32.4
36.9
40.9
44.6
47.7
50.1
52.2
54.2
55.9
57.1
58.4
59.6
60.9
(12.6 Ohms)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
8.5
15.9
23.8
31.8
39.7
47.7
55.0
62.3
69.4
75.3
80.5
84.6
87.7
90.8
92.9
94.9
97.0
99.1
101.1
12.1
14.7
16.4
17.8
18.6
19.0
19.3
19.7
19.9
20.0
20.1
20.2
20.3
20.4
20.6
Figure 1. gDDR2 Default Pulldown Characteristics for Full Strength Driver
120
100
80
60
40
20
0
Maximum
Nominal
Default
High
Nominal
Default
Low
Minimum
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
VOUT to VSSQ (V)
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256M gDDR2 SDRAM
K4N56163QF-GC
Table 2. Full Strength Default Pullup Driver Characteristics
Pulldown Current (mA)
Nominal Default Low (18 Nominal Default High(18
Minimum
Maximum
Voltage (V)
(23.4 Ohms)
ohms)
-11.1
-16.0
-20.3
-24.0
-27.2
-29.8
-31.9
-33.4
-34.6
-35.5
-36.2
-36.8
-37.2
-37.7
-38.0
-38.4
-38.6
ohms)
-11.8
-17.0
-22.2
-27.5
-32.4
-36.9
-40.8
-44.5
-47.7
-50.4
-52.5
-54.2
-55.9
-57.1
-58.4
-59.6
-60.8
(12.6 Ohms)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
-8.5
-15.9
-23.8
-31.8
-39.7
-47.7
-55.0
-62.3
-69.4
-75.3
-80.5
-84.6
-87.7
-90.8
-92.9
-94.9
-97.0
-99.1
-101.1
-12.1
-14.7
-16.4
-17.8
-18.6
-19.0
-19.3
-19.7
-19.9
-20.0
-20.1
-20.2
-20.3
-20.4
-20.6
Figure 2. gDDR2 Default Pullup Characteristics for Full Strength Output Driver
0
-20
Minimum
-40
Nominal
Default
Low
-60
Nominal
Default
High
-80
-100
-120
Maximum
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
VDDQ to VOUT (V)
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256M gDDR2 SDRAM
K4N56163QF-GC
gDDR2 SDRAM Default Output Driver V–I Characteristics
gDDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS1 bits A7-A9 = ‘111’.
Figures 1 and 2 show the driver characteristics graphically, and tables 1 and 2 show the same data in tabular format suitable for input
into simulation tools. The driver characteristics evaluation conditions are:
Nominal Default 25 oC (T case), VDDQ = 1.8 V, typical process
Minimum TBD oC (T case), VDDQ = 1.7 V, slow–slow process
Maximum 0 oC (T case), VDDQ = 1.9 V, fast–fast process
Default Output Driver Characteristic Curves Notes:
1) The full variation in driver current from minimum to maximum process, temperature, and voltage will lie within the outer bounding lines
of the V–I curve of figures 1 and 2.
2) It is recommended that the ”typical” IBIS V–I curve lie within the inner bounding lines of the V–I curves of figures 1 and 2.
Table 3. Full Strength Calibrated Pulldown Driver Characteristics
Calibrated Pulldown Current (mA)
Nominal Minimum
(21 Ohms)
Nominal Low
(18.75 ohms)
Nominal
Nominal High
(17.25 ohms)
Nominal Maximum
(15 Ohms)
Voltage (V)
(18 ohms)
0.2
0.3
0.4
9.5
14.3
18.7
10.7
16.0
21.0
11.5
16.6
21.6
11.8
17.4
23.0
13.3
20.0
27.0
Table 4. Full Strength Calibrated Pullup Driver Characteristics
Calibrated Pulldown Current (mA)
Nominal Minimum
(21 Ohms)
Nominal Low
Nominal
Nominal High
Nominal Maximum
(15 Ohms)
Voltage (V)
(18.75 ohms)
-10.7
(18 ohms)
(17.25 ohms)
-11.8
0.2
0.3
0.4
-9.5
-14.3
-18.7
-11.4
-16.5
-21.2
-13.3
-20.0
-27.0
-16.0
-21.0
-17.4
-23.0
gDDR2 SDRAM Calibrated Output Driver V–I Characteristics
gDDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in
Off-Chip Driver (OCD) Impedance Adjustment. Tables 3 and 4 show the data in tabular format suitable for input into simulation tools. The
nominal points represent a device at exactly 18 ohms. The nominal low and nominal high values represent the range that can be
achieved with a maximum 1.5 ohm step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration proce-
dure, 1.5 ohm maximum step size guaranteed by specification). Real system calibration error needs to be added to these values. It
must be understood that these V-I curves as represented here or in supplier IBIS models need to be adjusted to a wider range as a
result of any system calibration error. Since this is a system specific phenomena, it cannot be quantified here. The values in the cali-
brated tables represent just the DRAM portion of uncertainty while looking at one DQ only. If the calibration procedure is used, it is pos-
sible to cause the device to operate outside the bounds of the default device characteristics tables and figures. In such a situation, the
timing parameters in the specification cannot be guaranteed. It is solely up to the system application to ensure that the device is cali-
brated between the minimum and maximum default values at all times. If this can’t be guaranteed by the system calibration procedure,
re-calibration policy, and uncertainty with DQ to DQ variation, then it is recommended that only the default values be used. The nominal
maximum and minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature
change from the nominal condition to the maximum and minimum conditions. If calibrated at an extreme condition, the amount of varia-
tion could be as much as from the nominal minimum to the nominal maximum or vice versa. The driver characteristics evaluation condi-
tions are:
Nominal 25 oC (T case), VDDQ = 1.8 V, typical process.
Nominal Low and Nominal High 25 oC (T case), VDDQ = 1.8 V, any process.
Nominal Minimum TBD oC (T case), VDDQ = 1.7 V, any process.
Nominal Maximum 0 oC (T case), VDDQ = 1.9 V, any process.
Rev. 2.0 Oct. 2005
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