K4N56163QF-ZC300_技术文档

256M gDDR2 SDRAM

K4N56163QF-GC

256Mbit gDDR2 SDRAM

4M x 16Bit x 4 Banks

gDDR2 SDRAM

with Differential Data Strobe and DLL

Revision 1.5

March 2005

Samsung Electronics reserves the right to change products or specification without notice.

- 1 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Revision History

Revision 1.5 (March 04, 2005)

• Removed K4N56163QF-GC20/22 from the datasheet

Revision 1.4 (February 5, 2005)

• Added Lead-Free part number in the datasheet.

Revision 1.3 (January 5, 2005)

• Typo corrected

Revision 1.2 (December 28, 2004)

• Changed the DC characteristics table

• Added 50 ohm at the EMRS(1) programming table.

Revision 1.1 (December 1, 2004)

• Changed ICC2P and ICC6 to 10mA

Revision 1.0 (October 20, 2004)

• DC spec defined.

• Changed VDD&VDDQ of K4N56163QF-GC20/22 from 1.8V+0.1V to 2.0V+0.1V

Revision 0.0 (April 29, 2004) - Target Spec

• Defined Target Specification

- 2 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

4M x 16Bit x 4 Banks graphic DDR2 Synchronous DRAM

with Differential Data Strobe

FEATURES

• 1.8V + 0.1V power supply for device operation

• 1.8V + 0.1V power supply for I/O interface

• 4 Banks operation

• Bi-directional Differential Data-Strobe

(Single-ended data-strobe is an optional feature)

• Off-chip Driver (OCD) Impedance Adjustment

• On Die Termination

• Posted CAS

• Programmable CAS Letency : 4, 5, 6 and 7

• Programmable Additive Latency : 0, 1, 2, 3, 4 and 5

• Write Latency (WL) = Read Latency (RL) -1

• Burst Legth : 4 and 8 (Interleave/nibble sequential)

• Programmable Sequential/ Interleave Burst Mode

• Refresh and Self Refresh

Average Refesh Period 7.8us at lower then T_CASE85×C,

3.9us at 85×C < T_CASE< 95 ×C

• 84 ball FBGA

ORDERING INFORMATION

Part NO.

Max Freq.

400MHz

333MHz

266MHz

Max Data Rate

800Mbps/pin

667Mbps/pin

533Mbps/pin

Interface

Package

K4N56163QF-GC25

K4N56163QF-GC30

K4N56163QF-GC37

SSTL

84 Ball FBGA

* K4N56163QF-ZC is the Lead-Free part number.

GENERAL DESCRIPTION

FOR 4M x 16Bit x 4 Bank gDDR2 SDRAM

The 256Mb gDDR2 SDRAM chip is organized as 4Mbit x 16 I/O x 4banks banks device. This synchronous device

achieve high speed graphic double-data-rate transfer rates of up to 1000Mb/sec/pin for general applications. The chip is

designed to comply with the following key gDDR2 SDRAM features such as posted CAS with additive latency, write latency

= read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are

latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirec-

tional strobes (DQS and DQS) in a source synchronous fashion. A thirteen bit address bus is used to convey row, column,

and bank address information in a RAS/CAS multiplexing style. For example, 256Mb(x16) device receive 13/9/2 address-

ing. The 256Mb gDDR2 devices operate with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.

The 256Mb gDDR2 devices are available in 84ball FBGAs(x16).

Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of

operation.

- 3 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

PIN CONFIGURATION

Normal Package (Top View)

1

2

3

7

8

9

A

VSSQ

UDQS

VDDQ

UDQ2

VSSQ

UDQS

VSSQ

VDDQ

VDD

NC

VSS

UDM

UDQ6

VSSQ

UDQ1

B

C

UDQ7

VDDQ

UDQ3

VSS

VDDQ

UDQ4

VDD

UDQ0

VSSQ

LDQS

VSSQ

D

UDQ5

VDDQ

VSSQ

NC

E

F

LDQ6

VSSQ

LDQ1

LDM

LDQS

VDDQ

LDQ2

LDQ7

VDDQ

LDQ4

VDDL

VDDQ

LDQ3

LDQ0

VSSQ

CK

VDDQ

G

H

J

VSSQ

VREF

LDQ5

VSS

VSSDL

VDD

ODT

K

CK

CKE

BA0

A10

A3

WE

BA1

A1

RAS

CAS

A2

NC

L

CS

A0

A4

A8

M

N

P

R

VDD

VSS

A5

A6

A9

A11

A7

VDD

A12

NC

Notes:

VDDL and VSSDL are power and ground for the DLL. lt is recommended that they are isolated on the device from VDD,

VDDQ, VSS, and VSSQ.

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

+ + +

Ball Locations

: Populated Ball

: Depopulated Ball

+

G

H

J

Top View

(See the balls through the Package)

K

L

+

M

N

P

R

- 4 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

PACKAGE DIMENSIONS (84 Ball FBGA)

11.00 ± 0.10

# A1 INDEX MARK (OPTIONAL)

6.40

0.80

1.60

4

9

8

7

6

5

3

2

1

A

B

C

D

E

F

G

H

M

J

K

N

L

P

R

3.20

(6.15)

(0.90)

(1.80)

84-∅0.45±0.05

∅0.2 M

A B

11.00 ± 0.10

#A1

0.35±0.05

MAX.1.20

Unit : mm

- 5 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

Symbol

Type

Function

Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the pos-

Input itive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK

(both directions of crossing).

CK, CK

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input

buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation

(all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down

CKE

Input

entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be main-

tained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled

during power-down. Input buffers, excluding CKE, are disabled during self refresh.

Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank

selection on systems with multiple banks. CS is considered part of the command code.

CS

Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the gDDR2

SDRAM. When enabled, ODT is only applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM

signal for x16 configurations. The ODT pin will be ignored if the Extended Mode Register (EMRS) is pro-

ODT

Input

grammed to disable ODT.

RAS, CAS, WE

(L)UDM

Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled

Input HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS.

Although DM pins are input only, the DM loading matches the DQ and DQS loading.

Bank Address Inputs: BA0 and BA1 define to which bank an Actove, Read, Write or Precharge com-

Input mand is being applied. BA0 also determines if the mode register or extended mode register is to be

accessed during a MRS or EMRS cycle.

BA0 - BA1

Address Inputs: Provided the row address for Active commands and the column address and Auto Pre-

charge bit for Read/Write commands to select one location out of the memory array in the respective

Input bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one

bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by

BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands.

A0 - A12

DQ

Input/

Data Input/ Output: Bi-directional data bus.

Output

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write

data. LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. The

data strobes LDQS and UDQS may be used in single ended mode or paired with optional complementary

signals LDQS and UDQS to provide differential pair signaling to the system during both reads and writes.

An EMRS(1) control bit enables or disables all complementary data strobe signals.

LDQS,(LDQS)

UDQS,(UDQS)

Input/

Output

NC/RFU

V_DDQ

V_SSQ

V_DDL

V_SSL

V_DD

No Connect: No internal electrical connection is present.

Supply DQ Power Supply: 1.8V ± 0.1V

Supply DQ Ground

Supply DLL Power Supply: 1.8V ± 0.1V

Supply DLL Ground

Supply Power Supply: 1.8V ± 0.1V

Supply Ground

V_SS

V_REF

Supply Reference voltage

- 6 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Absolute Maximum DC Ratings

Symbol

Parameter

Rating

Units

Notes

VDD

- 1.0 V ~ 2.3 V

V

1

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on VDDL pin relative to Vss

Voltage on any pin relative to Vss

Storage Temperature

VDDQ

VDDL

- 0.5 V ~ 2.3 V

-55 to +100

V

1

V

_IN,V_OUT

V

1

T_STG

°C

1, 2

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please

refer to JESD51-2 standard.

AC & DC Operating Conditions

Recommended DC Operating Conditions (SSTL - 1.8)

Rating

Symbol

Parameter

Supply Voltage

Units

Notes

Min.

Typ.

Max.

VDD

VDDL

VDDQ

VREF

VTT

1.7

1.8

1.9

V

1.7

1.8

1.9

4

Supply Voltage for DLL

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

1.7

1.9

V

0.49*VDDQ

VREF-0.04

0.50*VDDQ

VREF

0.51*VDDQ

VREF+0.04

mV

V

1,2

3

There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must

be less than or equal to VDD.

1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is

expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.

2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).

3. VTT of transmitting device must track VREF of receiving device.

4. AC parameters are measured with VDD, VDDQ and VDDDL tied together.

- 7 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Operating Temperature Condition

Symbol

Parameter

Rating

Units

Notes

TOPER

Operating Temperature

0 to 95

°C

1, 2, 3

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,

please refer to JESD51.2 standard.

2. At 0 - 85 °C, operation temperature range are the temperature which all DRAM specification will be supported.

3. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required,

and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.

Input DC Logic Level

Symbol

V_IH(DC)

V_IL(DC)

Parameter

Min.

Max.

Units

Notes

VREF + 0.125

VDDQ + 0.3

V

DC input logic high

DC input logic low

- 0.3

VREF - 0.125

Input AC Logic Level

Symbol

Parameter

Min.

Max.

Units

VIH(AC)

VREF + 0.250

-

V

AC input logic high

AC input logic low

VIL(AC)

-

VREF - 0.250

V

AC Input Test Conditions

Symbol

V_REF

Condition

Input reference voltage

Value

Units

0.5 * V_DDQ

V

1

V_SWING(MAX)

SLEW

Input signal maximum peak to peak swing

Input signal minimum slew rate

1.0

V/ns

2, 3

Notes:

1. Input waveform timing is referenced to the input signal crossing through the V_IH/IL(AC) level applied to the device under test.

2. The input signal minimum slew rate is to be maintained over the range from V_REFto V_IH(AC) min for rising edges and the range

from V_REFto V_IL(AC) max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from V_IL(AC) to V_IH(AC) on the positive transitions and V_IH(AC) to

V_IL(AC) on the negative transitions.

V_DDQ

V_IH(AC) min

V_IH(DC) min

V_SWING(MAX)

V_REF

V_IL(DC) max

V_IL(AC) max

V_SS

delta TF

V

delta TR

Rising Slew =

_REF- V_IL(AC) max

delta TF

V_IH(AC) min - V_REF

delta TR

Falling Slew =

< AC Input Test Signal Waveform >

- 8 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Differential input AC logic Level

Symbol

Parameter

Min.

Max.

Units

Notes

VID(AC)

0.5

VDDQ + 0.6

V

1

AC differential input voltage

AC differential cross point voltage

VIX(AC)

0.5 * VDDQ - 0.175

0.5 * VDDQ + 0.175

V

2

Notes:

1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK,

DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).

The minimum value is equal to VIH(AC) - VIL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track

variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross.

V

DDQ

V

TR

Crossing point

V

ID

V

IX or OX

V

CP

V

SSQ

< Differential signal levels >

Differential AC output parameters

Symbol

_OX(AC)

Parameter

AC differential cross point voltage

Min.

0.5 * VDDQ - 0.125

Max.

Units

Note

V

0.5 * VDDQ + 0.125

V

1

Note :

1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track varia-

tions in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross.

- 9 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

OCD default characteristics

Description

Parameter

Min

12.6

Nom

18

Max

23.4

Unit

ohms

Notes

1,2

Output impedance

Output impedance step size for

OCD calibration

0

1.5

ohms

6

Pull-up and pull-down mismatch

Output slew rate

0

4

5

ohms

V/ns

1,2,3

Sout

1.5

1,4,5,6,7,8

Notes:

1. Absolute Specifications (0°C ≤ T_CASE≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)

2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;

less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-

(VOUT-VDDQ)/Ioh must be

280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than

23.4 ohms for values of VOUT between 0V and 280mV.

3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and

voltage.

4. Slew rate measured from V_IL(AC) to V_IH(AC).

5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to

AC. This is guaranteed by design and characterization.

6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the

DRAM uncertainty.

Output slew rate load :

VTT

25 ohms

Output

(VOUT)

Reference

Point

7. DRAM output slew rate specification applies to 533Mb/sec/pin, 667Mb/sec/pin, 800Mb/sec/pin, 900Mbps/sec/pin and

1000Mbps/sec/pin speed bins.

8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS

specification.

- 10 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

DC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted, 0°C ≤ Tc ≤85°C )

Version

Unit

Parameter

Symbol

Test Condition

- 25

- 30

- 37

Burst Length=4 tRC ≥ tRC(min). IOL=0mA, tCC= tCC(min).

DQ,DM,DQS inputs changing twice per clock cycle.

Address and control inputs changing once per clock

cycle

Operating Current

(One Bank Active)

ICC1

150

135

120

mA

Precharge Standby Current

in Power-down mode

ICC2P

ICC2N

ICC3P

CKE ≤ VIL(max), tCC= tCC(min)

10

45

50

mA

CKE ≥ VIH(min), CS ≥ VIH(min),tCC= tCC(min)

Address and control inputs changing once per clock

cycle

Precharge Standby Current

in Non Power-down mode

45

50

40

50

Active Standby Current

power-down mode

CKE ≤ VIL(max), tCC= tCC(min)

CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min)

DQ,DM,DQS inputs changing twice per clock cycle.

Address and control inputs changing once per clock

cycle

Active Standby Current in

in Non Power-down mode

ICC3N

ICC4

85

80

mA

Operating Current

( Burst Mode)

IOL=0mA ,tCC= tCC(min),

Page Burst, All Banks activated. DQ,DM,DQS inputs

changing twice per clock cycle. Address and control

inputs changing once per clock.

300

190

280

260

160

Refresh Current

ICC5

ICC6

ICC7

tRC≥ tRFC

180

10

mA

CKE ≤ 0.2V

Self Refresh Current

Operating Current

(4Bank interleaving)

Burst Length=4 tRC ≥ tRC(min). IOL=0mA, tCC= tCC(min).

DQ,DM,DQS inputs changing twice per clock cycle.

Address and control inputs changing once per clock

cycle

430

400

350

mA

Note : 1. Measured with outputs open and ODT off

2. Refresh period is 32ms

- 11 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Input/Output capacitance

- 30

- 25

- 37

Parameter

Symbol

Min

1.0

x

Max

2.0

Min

1.0

x

Max

2.0

Units

pF

Input capacitance, CK and CK

CCK

Input capacitance delta, CK and CK

CDCK

CI

0.25

2.0

0.25

2.0

pF

Input capacitance, all other input-only pins

Input capacitance delta, all other input-only pins

Input/output capacitance, DQ, DM, DQS, DQS

Input/output capacitance delta, DQ, DM, DQS, DQS

1.0

x

1.0

x

pF

CDI

0.25

4.0

0.25

3.5

pF

CIO

2.5

x

2.5

x

pF

CDIO

0.5

pF

Electrical Characteristics & AC Timing for - 35/30/37

(0 °C < T_CASE< 95 °C; V_DDQ= 1.8V + 0.1V; V_DD= 1.8V + 0.1V)

Refresh Parameters by Device Density

Parameter

Symbol

256Mb

Units

Refresh to active/Refresh command time

tRFC

tREFI

75

ns

0 °C ≤ T_CASE≤ 85°C

85 °C < T_CASE≤ 95°C

7.8

µs

Average periodic refresh interval

3.9

Speed Bins and CL, tRCD, tRP, tRC and tRAS

SPEED

Bin (CL-tRCD-tRP)

- 25

6-6-6

min

6

- 30

5-5-5

min

5

- 37

Units

4-5-5

min

4

Parameter

CAS LATENCY

tCK

ns

2.5

6

3.0

5

3.75

5

tRCD

tCK

tRP

6

5

tRC

22

18

16

tRAS

16

13

11

- 12 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Timing Parameters by Speed Grade

(Refer to notes for informations related to this table at the bottom)

- 25

- 30

- 37

Symbol

Units

Notes

Parameter

min

-400

max

400

min

-450

max

+450

+400

min

-500

max

+500

DQ output access time from CK/CK

DQS output access time from CK/CK

CK high-level width

tAC

ps

tDQSCK

tCH

-350

0.45

+350

0.55

-400

0.45

-450

0.45

+450

0.55

ps

0.55

tCK

CK low-level width

tCL

min

(tCL, tCH)

min

(tCL, tCH)

min

(tCL, tCH)

CK half period

tHP

x

ps

20,21

Clock cycle time, CL=x

tCK

tDH

tDS

2.5

175

50

8.0

x

3.0

175

50

8.0

x

3.75

225

100

8.0

x

ns

ps

24

DQ and DM input hold time

DQ and DM input setup time

15,16,17

x

Control & Address input pulse width

for each input

tIPW

tDIPW

tHZ

0.6

0.35

x

0.6

0.35

x

0.6

0.35

x

tCK

ps

DQ and DM input pulse width for

each input

x

Data-out high-impedance time from

CK/CK

tAC max

DQS low-impedance time from CK/

CK

tLZ

(DQS)

tAC min

tAC max

280

tAC min

tAC max

310

tAC min

tAC max

340

ps

27

22

21

DQ low-impedance time from CK/CK

tLZ(DQ)

tDQSQ

tQHS

2*tAC min

2* tACmin

DQS-DQ skew for DQS and

associated DQ signals

x

DQ hold skew factor

380

410

440

tHP -

tQHS

tHP -

tQHS

tHP -

tQHS

DQ/DQS output hold time from DQS

tQH

x

Write command to first DQS latching

transition

WL

-0.25

WL

+0.25

WL

-0.25

WL

+0.25

WL

-0.25

WL

+0.25

tDQSS

tCK

DQS input high pulse width

DQS input low pulse width

tDQSH

tDQSL

tDSS

0.35

0.2

x

0.35

0.2

x

0.35

0.2

x

tCK

DQS falling edge to CK setup time

DQS falling edge hold time from CK

tDSH

0.2

Mode register set command cycle

time

tMRD

2

x

2

x

2

x

tCK

Write postamble

Write preamble

tWPST

tWPRE

0.4

0.6

x

0.4

0.6

x

0.4

0.6

x

tCK

19

0.35

- 13 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

- 25

- 30

- 37

Symbol

Units

Notes

Parameter

min

475

350

0.9

max

x

min

475

350

0.9

max

x

min

475

350

0.9

max

x

Address and control input hold time

Address and control input setup time

Read preamble

tIH

ps

14,16,18

28

tIS

x

tRPRE

tRPST

1.1

0.6

1.1

0.6

1.1

0.6

tCK

Read postamble

0.4

28

Active to active command period for

1KB page size products

tRRD

7.5

10

x

7.5

10

x

7.5

10

x

ns

12

Active to active command period for

2KB page size products

tRRD

tFAW

Four Activate Window for 1KB page

size products

37.5

50

37.5

50

37.5

50

Four Activate Window for 2KB page

size products

tFAW

CAS to CAS command delay

Write recovery time

tCCD

tWR

2

6

2

5

2

4

tCK

x

Auto precharge write recovery +

precharge time

tWR

+tRP

tWR

+tRP

tWR

+tRP

tDAL

tWTR

tRTP

tCK

23

11

Internal write to read command delay

3

2

Internal read to precharge command

delay

Exit self refresh to a non-read

command

tRFC +

10

tXSNR

tXSRD

tXP

tRFC + 10

ns

Exit self refresh to a read command

200

2

200

2

200

2

tCK

Exit precharge power down to any

non-read command

x

Exit active power down to read

command

tXARD

2

tCK

9

Exit active power down to read

command

tXARDS

6-AL

6 - AL

9, 10

(Slow exit, Lower power)

CKE minimum pulse width

(high and low pulse width)

^tCKE

tCK

ns

3

2

3

2

^tAOND

^tAON

ODT turn-on delay

ODT turn-on

3

2

tAC

(min)

tAC

(max)+0.7

tAC

(min)

tAC

(max)+0.7

tAC

(min)

tAC

(max)+1

13, 25

tAC

(min)

+2

3tCK+

tAC(max)

+1

2tCK+

tAC(max)

+1

tAC

(min)+2

tAC

(min)+2

2tCK+tA

C(max)+1

^tAONPD

^tAOFD

ODT turn-on(Power-Down mode)

ODT turn-off delay

ns

3.5

2.5

tCK

- 14 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

- 25

- 30

- 37

Symbol

Units

Notes

Parameter

min

max

min

max

min

max

tAC

(min)

tAC

(max)+ 0.6

tAC

(min)

tAC

(max)+ 0.6

tAC

(min)

tAC

(max)+ 0.6

^tAOF

ODT turn-off

ns

26

2.5tCK+

tAC(max)+

1

ODT turn-off (Power-Down

mode)

3.5tCK+tA

C(max)+1

2.5tCK+tA

C(max)+1

tAC(min)+

2

^tAOFPD

tANPD

tAC(min)+2

3

tAC(min)+2

3

ODT to power down entry

latency

3

tCK

ODT power down exit latency

OCD drive mode output delay

tAXPD

tOIT

8

0

8

0

8

0

tCK

ns

12

Minimum time clocks remains

ON after CKE

asynchronously drops LOW

tIS+tCK

+tIH

tIS+tCK

+tIH

tIS+tCK

+tIH

tDelay

ns

24

General notes, which may apply for all AC parameters

1. Slew Rate Measurement Levels

a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for

single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV

and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.

b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to VREF + 250 mV for rising

edges and from VREF + 125 mV and VREF - 250 mV for falling edges.

For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV

(250mV to -500 mV for falling egdes).

c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS

for differential strobe.

2. gDDR2 SDRAM AC timing reference load

Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to

be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester.

System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers

will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics).

VDDQ

DQ

DQS

Output

DUT

V

= V

/2

TT

DDQ

Timing

reference

point

25Ω

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level

for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.

- 15 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

3. gDDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as shown in the following figure.

VDDQ

DUT

DQ

Output

DQS, DQS

V

= V

/2

TT

DDQ

25Ω

Test point

4. Differential data strobe

gDDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS

“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the gDDR2 SDRAM

pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling

edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its

complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data

strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm

resisor to insure proper operation.

t

DQSL

DQSH

DQS

DQS/

DQS

t

WPST

WPRE

V_IH(dc)

V_IL(dc)

V_IH(ac)

DQ

DM

D

t

V_IL(ac)

t

DH

V_IH(dc)

DS

t

DS

V_IH(ac)

DMin

V_IL(ac)

V_IL(dc)

t

CL

CH

CK

CK/CK

DQS

DQS/DQS

DQ

t

RPRE

RPST

Q

t

DQSQmax

t

DQSQmax

t

QH

5. AC timings are for linear signal transitions.

6. These parameters guarantee device behavior, but they are not necessarily tested on each device.

They may be guaranteed by device design or tester correlation.

- 16 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

7. All voltages are referenced to VSS.

8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels,

but the related specifications and device operation are guaranteed for the full voltage range specified.

Specific Notes for dedicated AC parameters

9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power

down exit timing. tXARDS is expected to be used for slow active power down exit timing.

10. AL = Additive Latency

11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been

satisfied.

12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency

13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns.

14. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by

device design or tester correlation.

15. Timings are guaranteed with data, mask, and (DQS in singled ended mode) input slew rate of 1.0 V/ns.

16. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential

slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended mode.

17. tDS and tDH (data setup and hold) derating

1) Input waveform timing is referenced from the input signal crossing at the V_IH(AC) level for a rising signal and V_IL(AC) for a

falling signal applied to the device under test.

2) Input waveform timing is referenced from the input signal crossing at the V_IH(DC) level for a rising signal and V_IL(DC) for a

falling signal applied to the device under test.

DQS

tDS

tDH

V

DDQ

(AC) min

IH

(DC) min

IH

REF

V (DC) max

IL

V (AC) max

IL

V

SS

- 17 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

18. tIS and tIH (input setup and hold) derating

1) Input waveform timing is referenced from the input signal crossing at the V_IH(AC) level for a rising signal and V_IL(AC) for a

falling signal applied to the device under test.

2) Input waveform timing is referenced from the input signal crossing at the V_IH(DC) level for a rising

signal and V_IL(DC) for a falling signal applied to the device under test

CK

tIS

tIH

V

DDQ

(AC) min

IH

(DC) min

REF

V (DC) max

IL

V (AC) max

IL

V

SS

19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system

performance (bus turnaround) will degrade accordingly.

20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the

half period jitter ( tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.

21. tQH = tHP – tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).

tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which

are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.

22. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as

output slew rate mismatch between DQS / DQS and associated DQ in any given cycle.

23. tDAL = (nWR) + ( tRP/tCK):

For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period. nWR

refers to the tWR parameter stored in the MRS.

Example: For gDDR533 at t CK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks =4 +(4)clocks=8clocks.

- 18 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

24. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency

change during precharge power-down, a specific procedure is required as described in gDDR2 device operation

25. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

26. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

27. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific volt-

age level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . Following figure shows a method to

calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The

actual voltage measurement points are not critical as long as the calculation is consistent.

28. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no

longer driving (tRPST), or begins driving (tRPRE). Following figure shows a method to calculate these points when the device is no

longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement

points are not critical as long as the calculation is consistent.

These notes are referenced to the “Timing parameters by speed grade” tables for gDDR2-533/667 and gDDR2-800.

VTT + 2x mV

VTT + x mV

VOH + x mV

VOH + 2x mV

tLZ

tHZ

tRPRE begin point

tRPST end point

VTT - x mV

VOL + 2x mV

VOL + x mV

T1

T2

VTT - 2x mV

T2

T1

tHZ,tRPST end point = 2*T1-T2

tLZ,tRPRE begin point = 2*T1-T2

- 19 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

gDDR2 SDRAM

Device Operation & Timing Diagram

- 20 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Functional Description

Simplified State Diagram

Initialization

Sequence

CKEL

OCD

calibration

Self

Refreshing

SRF

CKEH

PR

Idle

Setting

MRS

EMRS

MRS

REF

All banks

precharged

Refreshing

CKEL

CKEH

ACT

CKEL

Precharge

Power

Down

Activating

CKEL

Automatic Sequence

Command Sequence

Active

Power

Down

CKEH

CKEL

Bank

Active

Read

Write

Read

WRA

RDA

Read

Reading

Writing

RDA

WRA

RDA

PR, PRA

Writing

with

Autoprecharge

Reading

with

Autoprecharge

PR, PRA

CKEL = CKE low, enter Power Down

Precharging

CKEH = CKE high, exit Power Down, exit Self Refresh

ACT = Activate

WR(A) = Write (with Autoprecharge)

RD(A) = Read (with Autoprecharge)

PR(A) = Precharge (All)

MRS = (Extended) Mode Register Set

SRF = Enter Self Refresh

REF = Refresh

Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions

and the commands to control them, not all details. In particular situations involving more than one bank,

enabling/disabling on-die termination, Power Down entry/exit - among other things - are not captured

in full detail.

- 21 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Basic Functionality

Read and write accesses to the gDDR2 SDRAM are burst oriented; accesses start at a selected location and continue for

a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command,

which is then followed by a Read or Write command. The address bits registered coincident with the active command are

used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits reg-

istered coincident with the Read or Write command are used to select the starting column location for the burst access

and to determine if the auto precharge command is to be issued.

Prior to normal operation, the gDDR2 SDRAM must be initialized. The following sections provide detailed information cov-

ering device initialization, register definition, command descriptions and device operation.

Power up and Initialization

gDDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation.

Power-up and Initialization Sequence

The following sequence is required for POWER UP and Initialization.

1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT^*1at a low state (all other inputs may be unde-

fined.)

- VDD, VDDL and VDDQ are driven from a single power converter output, AND

- VTT is limited to 0.95 V max, AND

- Vref tracks VDDQ/2.

or

- Apply VDD before or at the same time as VDDL.

- Apply VDDL before or at the same time as VDDQ.

- Apply VDDQ before or at the same time as VTT & V_REF

.

at least one of these two sets of conditions must be met.

2. Start clock and maintain stable condition.

3. For the minimum of 200µs after stable power and clock(CK, CK), then apply NOP or deselect & take CKE high.

4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period.

5. Issue EMRS(2) command. (To issue EMRS(2) command, provide “Low” to BA0, “High” to BA1.)

6. Issue EMRS(3) command. (To issue EMRS(3) command, provide “High” to BA0 and BA1.)

7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1

and A12.)

8. Issue a Mode Register Set command for “DLL reset”.

(To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1)

9. Issue precharge all command.

10. Issue 2 or more auto-refresh commands.

11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating parameters

without resetting the DLL.

12. At least 200 clocks after step 8, execute OCD Calibration ( Off Chip Driver impedance adjustment ).

If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD

- 22 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

1. Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of EMRS.

2. The gDDR2 SDRAM is now ready for normal operation.

*1) To guarantee ODT off, V_REFmust be valid and a low level must be applied to the ODT pin.

Initialization Sequence after Power Up

tCHtCL

CK

/CK

tIS

V_IH(ac)

CKE

ODT

ANY

CMD

PRE

ALL

PRE

ALL

NOP

EMRS

MRS

REF

MRS

EMRS

REF

Command

EMRS

OCD

tRFC

tRP

tMRD

tRFC

tMRD

400ns

tRP

Follow OCD

Flowchart

tOIT

min. 200 Cycle

DLL

RESET

DLL

ENABLE

OCD

Default

CAL. MODE

EXIT

Programming the Mode Register

For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR) are user

defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable func-

tion, driver impedance, additive CAS latency, ODT(On Die Termination), single-ended strobe, and OCD(off chip driver

impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set

(EMRS) command. Contents of the Mode Register(MR) or Extended Mode Registers(EMR(#)) can be altered by re-exe-

cuting the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all

variables must be redefined when the MRS or EMRS commands are issued.

MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed

any time after power-up without affecting array contents.

- 23 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

gDDR2 SDRAM Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of gDDR2 SDRAM. It controls CAS latency,

burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make gDDR2 SDRAM

useful for various applications. The default value of the mode register is not defined, therefore the mode register must be

written after power-up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0 and

BA1, while controlling the state of address pins A0 ~ A15. The gDDR2 SDRAM should be in all bank precharge with CKE

already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to com-

plete the write operation to the mode register. The mode register contents can be changed using the same command and

clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is

divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and 8 bit burst

lengths. The burst length decodes are compatible with gDDR SDRAM. Burst address sequence type is defined by A3,

CAS latency is defined by A4 ~ A6. The gDDR2 doesn’t support half clock latency mode. A7 is used for test mode. A8 is

used for DLL reset. A7 must be set to low for normal MRS operation. Write recovery time tWR is defined by A9 ~ A11.

Refer to the table for specific codes.

BA1 BA0

A12

PD

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

RFU

0

DLL

TM

CAS Latency

BT

Burst Length

tWR

Active Power

Down exit time

Burst Type

A3

A12

Test Mode

Type

0

1

Fast exit (use tXARD)

Slow exit (use tXARDS)

A7

0

mode

0

1

Sequential

Interleave

Normal

Test

1

BA1

BA0

MRS Mode

MRS

Burst Length

0

1

0

1

0

1

DLL

A2

0

A1

1

A0 Burst Length

EMRS (1)

A8

0

DLL Reset

No

0

1

4

8

EMRS (2) : Reserved

EMRS (3) : Reserved

0

1

Yes

CAS Latency

Write Recovery for Auto Precharge

A6 A5 A4 Latency

A11

0

A10 A9

MRS Select

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

0

Reserved

0

Reserved

0

4

5

6

7

8

4

5

6

7

1

*1 : A13 is reserved for future use and must be programmed to 0 when setting the mode register.

BA2 and A14 are not used for 512Mb, but used for 1Gb and 2Gb gDDR2 SDRAMs. A15 is reserved for future

usage.

*2 : WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock cycles is

calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to the next integer

(WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is also used with tRP to determine tDAL.

- 24 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

gDDR2 SDRAM Extended Mode Register Set

EMRS(1)

The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT value selec-

tion and additive latency. The default value of the extended mode register is not defined, therefore the extended mode reg-

ister must be written after power-up for proper operation. The extended mode register is written by asserting low on CS,

RAS, CAS, WE and high on BA0, while controlling the states of address pins A0 ~ A12. The gDDR2 SDRAM should be in

all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set command

cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode register contents

can be changed using the same command and clock cycle requirements during normal operation as long as all banks are

in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength data-output driver.

A3~A5 determines the additive latency, A2 and A6 are used for ODT value selection, A7~A9 are used for OCD control,

A10 is used for DQS# disable.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to

normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation

and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset),

200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized

with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parame-

ters.

- 25 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

EMRS (1) Programming

BA1 BA0

A12

A11

A10

A9

A8

A7

A6

Rtt

A5

A4

A3

A2

Rtt

A1

A0

0

1

Qoff

0

DQS

OCD Program

Additive Latency

D.I.C DLL

BA1 BA0

MRS mode

MRS

A6

0

A2

Rtt (NOMINAL)

0

1

0

1

0

1

0

1

0

1

ODT Disabled

75 ohm

A0

DLL Enable

Enable

EMRS(1)

0

1

EMRS(2): Reserved

EMRS(3): Reserved

1

150 ohm

50 ohm

Disable

1

A9 A8 A7 OCD Calibration Program

A5 A4 A3 Additive Latency

0

1

0

1

0

1

0

OCD Calibration mode exit; maintain setting

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Drive(1)

Drive(0)

1

2

Adjust mode^a

3

4

OCD Calibration default ^b

1

5

a: When Adjust mode is issued, AL from previously set value must be applied.

b: After setting to default, OCD mode needs to be exited by setting A9-A7 to

000. Refer to the following 3.2.2.3 section for detailed information

Reserved

a

A12

Qoff (Optional)

Output Driver

Impedance Control

Driver

Size

0

1

Output buffer enabled

A1

Output buffer disabled

0

1

Normal

100%

60%

a. Outputs disabled - DQs, DQSs, DQSs .

Weak

This feature is used in conjunction with dimm

IDD meaurements when IDDQ is not desired to

be included.

A10

0

DQS

Enable

Disable

Strobe Function

Matrix

A10

(DQS Enable)

1

DQS

Hi-z

0 (Enable)

1 (Disable)

- 26 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Off-Chip Driver (OCD) Impedance Adjustment

gDDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence. Every calibration

mode command should be followed by “OCD calibration mode exit” before any other command being issued. MRS should

be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depend-

ing on system environment.

MRS shoud be set before entering OCD impedance adjustment and ODT should

be carefully controlled depending on system environment

Start

EMRS: OCD calibration mode exit

EMRS: Drive(1)

EMRS: Drive(0)

DQ & DQS High; DQS Low

DQ & DQS Low; DQS High

ALL OK

Test

Need Calibration

EMRS: OCD calibration mode exit

EMRS :

Enter Adjust Mode

BL=4 code input to all DQs

Inc, Dec, or NOP

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

End

- 27 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Extended Mode Register Set for OCD impedance adjustment

OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by

gDDR2 SDRAM and drive of DQS is dependent on EMRS bit enabling DQS operation. In Drive(1) mode, all DQ, DQS sig-

nals are driven high and all DQS signals are driven low. In drive(0) mode, all DQ, DQS signals are driven low and all DQS

signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default,

output driver characteristics have a nominal impedance value of 18 ohms during nominal temperature and voltage condi-

tions. Output driver characteristics for OCD calibration default are specified in section 6. OCD applies only to normal full

strength output drive setting defined by EMRS(1) and if half strength is set, OCD default output driver

characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver

characteristics are not applicable. After OCD calibration is completed or driver strength is set to default,

subsequent EMRS commands not intended to adjust OCD characteristics must specify A9-A7 as '000' in order to maintain

the default or calibrated value.

Off- Chip-Driver program

A9 A8 A7 Operation

0

1

0

1

0

1

0

1

0

1

OCD calibration mode exit

Drive(1) DQ, DQShigh and DQS low

Drive(0) DQ, DQS low and DQS high

Adjust mode

OCD calibration default

OCD impedance adjust

To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code to

gDDR2 SDRAM as in the folowing table. For this operation, Burst Length has to be set to BL = 4 via MRS command before

activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in the following table means all

DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all gDDR2 SDRAM DQs

simultaneously and after OCD calibration, all DQs of a given gDDR2 SDRAM will be adjusted to the same driver strength

setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code

has no effect. The default setting may be any step within the 16 step range. When Adjust mode command is issued, AL

from previously set value must be applied

Off- Chip-Driver Program

4bit burst code inputs to all DQs

Operation

Pull-down driver strength

DT0

0

DT1

0

DT2

0

DT3

0

Pull-up driver strength

NOP (No operation)

Increase by 1 step

Decrease by 1 step

NOP

NOP (No operation)

NOP

0

1

0

1

0

NOP

0

1

0

Increase by 1 step

Decrease by 1 step

Increase by 1 step

1

0

NOP

0

1

0

1

Increase by 1 step

Decrease by 1 step

0

1

0

- 28 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

1

0

1

0

Increase by 1 step

Decrease by 1 step

Reserved

Other Combinations

For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the following timing

diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by

MRS addressing mode (ie. sequential or interleave).

OCD adjust mode

CMD

OCD calibration mode exit

NOP

EMRS

NOP

EMRS

NOP

CK

WL

WR

DQS

DQS_in

tDS tDH

V_IH(AC)

V_IL(AC)

^VD^IH⁽T^D0^C)

V_IL(DC)

DQ_in

DM

DT2

DT3

DT1

Drive Mode

Drive mode, both Drive(1) and Drive(0), is used for controllers to measure gDDR2 SDRAM Driver impedance. In this

mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers are turned-off tOIT after

“OCD calibration mode exit” command as the following timing diagram.

- 29 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

ODT (On Die Termination)

On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance. For x16 configuration

ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal via the ODT control pin. The ODT feature

is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off

termination resistance for any or all DRAM devices.

The ODT function is supported for ACTIVE and STANDBY modes, and turned off and not supported in SELF REFRESH

mode.

Functional Representation of ODT

VDDQ

sw1

sw2

Rval2

Rval1

DRAM

Input

Buffer

Input

sw1

Q

sw2

Q

VSS

Switch sw1 or sw2 is enabled by ODT pin.

Selection between sw1 or sw2 is determined by “

Termination included on all DQs, DM, DQS and DQS pins.

tt ohm) (Rval1) / 2 or (Rval2) / 2

Rtt (nominal)” in EMRS

Target

R

(

=

ODT DC Electrical Characteristics

Parameter/Condition

Symbol

Min

Nom

Max

Units Notes

Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm

Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm

Rtt mismatch tolerance between any pull-up/pull-down pair

Rtt1(eff)

Rtt2(eff)

Rtt(mis)

60

120

-3.75

75

150

90

180

+3.75

ohm

%

1

Note 1: Test condition for Rtt measurements

Measurement Definition for Rtt(eff): Apply V_IH(AC) and V_IL(AC) to test pin separately, then measure current I(V_IH(AC)) and I( V_IL(AC))

respectively. V_IH(AC), V_IL(AC), and VDDQ values defined in SSTL_18

V_IH(AC) - V_IL(AC)

Rtt(eff) =

I(V_IH(AC)) - I(V_IL(AC))

Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load.

2 x Vm

- 1

x 100%

delta VM =

VDDQ

- 30 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

ODT timing for active/standby mode

T0

T1

T2

T3

T4

T5

T6

CK

CKE

ODT

t

IS

t

IS

V_IH(AC)

V_IL(AC)

t

AOFD

t

AOND

Internal

Term Res.

RTT

t

AOF,min

AON,min

t

AOF,max

AON,max

ODT timing for powerdown mode

T0

T1

T2

T3

T4

T5

T6

CK

CKE

ODT

t

IS

t

IS

V_IH(AC)

V_IL(AC)

t

AOFPD,max

t

AOFPD,min

Internal

Term Res.

RTT

t

AONPD,min

t

AONPD,max

- 31 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

ODT timing mode switch at entering power down mode

T-5

T-4

T-3

T-2

T-1

T0

T1

T2

T3

T4

CK

t

ANPD

t

IS

CKE

Entering Slow Exit Active Power Down Mode

or Precharge Power Down Mode.

t

IS

ODT

V_IL(AC)

Active & Standby

mode timings to

be applied.

t

AOFD

Internal

Term Res.

RTT

t

IS

ODT

V_IL(AC)

Power Down

mode timings to

be applied.

t

AOFPDmax

Internal

Term Res.

RTT

t

IS

V_IH(AC)

ODT

t

AOND

Active & Standby

mode timings to

be applied.

Internal

Term Res.

RTT

t

IS

V_IH(AC)

ODT

Power Down

mode timings to

be applied.

t

AONPDmax

Internal

Term Res.

RTT

- 32 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

ODT timing mode switch at exiting power down mode

T0

T1

T4

T5

T6

T7

T8

T9

T10

T11

CK

t

IS

t

AXPD

V_IH(AC)

CKE

Exiting from Slow Active Power Down Mode

or Precharge Power Down Mode.

t

IS

ODT

V_IL(AC)

Active & Standby

t

AOFD

mode timings to

be applied.

Internal

Term Res.

RTT

t

IS

ODT

V_IL(AC)

Power Down

mode timings to

t

AOFPDmax

be applied.

Internal

RTT

Term Res.

t

IS

V_IH(AC)

Active & Standby

mode timings to

be applied.

ODT

t

AOND

Internal

RTT

Term Res.

t

IS

V_IH(AC)

ODT

Power Down

mode timings to

be applied.

t

AONPDmax

Internal

RTT

Term Res.

- 33 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Bank Activate Command

The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock.

The bank addresses BA0 and BA1 are used to select the desired bank. The row address A0 through A12 is used to deter-

mine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write

operation can be executed. Immediately after the bank active command, the gDDR2 SDRAM can accept a read or write

command on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specifica-

tion, then additive latency must be programmed into the device to delay when the R/W command is internally issued to the

device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5 are

supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied

to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time

interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the

device (t_RC). The minimum time interval between Bank Activate commands is t_RRD

.

Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2

T0

T1

T2

T3

Tn

Tn+1

Tn+2

Tn+3

. . . . . . . . . .

CK / CK

Internal RAS-CAS delay (>= t_RCDmin

Bank A

)

Bank B

Col. Addr.

Bank A

Row Addr.

Bank A

Bank B

Bank A

Addr.

Bank B

Addr.

. . . . . . . . . .

ADDRESS

Col. Addr.

Row Addr.

CAS-CAS delay time (t_CCD

)

RCD =1

additive latency delay (_AL

Read Begins

RAS - RAS delay time (>= t_RRD

)

Post CAS

Read B

Post CAS

Read A

Bank B

Activate

Bank A

Activate

Bank B

Precharge

Bank A

Active

Bank A

Precharge

. . . . . . . . . .

COMMAND

Bank Active (>= t_RAS

)

Bank Precharge time (>= t_RP

)

: “H” or “L”

RAS Cycle time (>= t_RC

)

- 34 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and

CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether the access cycle is a read

operation (WE high) or a write operation (WE low).

The gDDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a serial read

or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of

the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of 2048 bits (defined by CA0-CA9,

CA11). The page length of 2048 is divided into 512 or 256 uniquely addressable boundary segments depending on burst

length, 512 for 4 bit burst, 256 for 8 bit burst respectively. A 4-bit or 8 bit burst operation will occur entirely within one of the

512 or 256 groups beginning with the column address supplied to the device during the Read or Write Command (CA0-

CA9, CA11). The second, third and fourth access will also occur within this group segment, however, the burst order is a

function of the starting address, and the burst sequence.

A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL

= 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes

interrupted by a write with 4 bit burst boundry respectively. The minimum CAS to CAS delay is defined by tCCD, and is a

minimum of 2 clocks for read or write cycles.

- 35 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Posted CAS

Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in gDDR2

SDRAM. In this operation, the gDDR2 SDRAM allows a CAS read or write command to be issued immediately after the

RAS bank activate command (or any time during the RAS-CAS-delay time, tRCD, period). The command is held for the

time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of

AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCDmin, then AL (greater

than 0) must be written into the EMR(1). The Write Latency (WL) is always defined as RL - 1 (read latency -1) where read

latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL). Read or Write operations using AL allow

seamless bursts (refer to seamless operation timing diagram examples in Read burst and Write burst section)

Examples of posted CAS operation

Example 1 Read followed by a write to the same bank

[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]

-1

0

1

2

3

4

5

6

7

8

9

10

11

12

CK/CK

CMD

Write

A-Bank

Active

A-Bank

Read

A-Bank

WL = RL -1 = 4

CL = 3

AL = 2

DQS/DQS

DQ

> = tRCD

RL = AL + CL = 5

Dout2

Dout3

Din0

Din1

Din2

Din3

Dout0

Dout1

> = tRAC

Example 2 Read followed by a write to the same bank

[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]

-1

0

1

2

3

4

5

6

7

8

9

10

11

12

CK/CK

CMD

AL = 0

Read

A-Bank

Write

A-Bank

Active

A-Bank

CL = 3

WL = RL -1 = 2

DQS/DQS

DQ

> = tRCD

RL = AL + CL = 3

Dout2

Dout3

Din0

Din1

Din2

Din3

Dout0

Dout1

> = tRAC

- 36 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory loca-

tions (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length.

gDDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is

supported, however, sequential address ordering is nibble based for ease of implementation. The burst type, either

sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS, which is similar to the DDR

SDRAM operation. Seamless burst read or write operations are supported. Unlike DDR devices, interruption of a burst

read or write cycle during BL = 4 mode operation is prohibited. However in case of BL = 8 mode, interruption of a burst

read or write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write. Therefore the

Burst Stop command is not supported on gDDR2 SDRAM devices.

Burst Length and Sequence

BL = 4

Burst Length

Starting Address (A1 A0)

Sequential Addressing (decimal) Interleave Addressing (decimal)

0 0

0 1

1 0

1 1

0, 1, 2, 3

1, 2, 3, 0

2, 3, 0, 1

3, 0, 1, 2

0, 1, 2, 3

1, 0, 3, 2

2, 3, 0, 1

3, 2, 1, 0

4

BL = 8

Burst Length

Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 0, 5, 6, 7, 4

2, 3, 0, 1, 6, 7, 4, 5

3, 0, 1, 2, 7, 4, 5, 6

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 4, 1, 2, 3, 0

6, 7, 4, 5, 2, 3, 0, 1

7, 4, 5, 6, 3, 0, 1, 2

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

8

Note: Page length is a function of I/O organization and column addressin

- 37 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Burst Read Command

The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the

clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to

when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe out-

put (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchro-

nized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the

DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is

defined by the Mode Register Set (MRS), similar to the existing SDR and DDR SDRAMs. The AL is defined by the

Extended Mode Register Set (1)(EMRS(1)).

gDDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the setting of

the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by

which the gDDR2 SDRAM pin timings are measured is mode dependent. In single

ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differen-

tial mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This dis-

tinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is

disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 Kohm resis-

tor to insure proper operation.

t

CL

CH

CK

DQS

DQ

t

RPRE

RPST

Q

t

DQSQmax

t

DQSQmax

t

QH

t

QH

Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

DQS

Posted CAS

READ A

NOP

=< t_DQSCK

AL = 2

CL =3

RL = 5

DQs

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

- 38 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Burst Read Operation: RL = 3 (AL = 0 and CL = 3, BL = 8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

DQS

CAS

READ A

NOP

=< t_DQSCK

CL =3

RL = 3

DQs

DOUT A₀

DOUT A₄

DOUT A₁

DOUT A₂

DOUT A₃

DOUT A₅

DOUT A₆

DOUT A₇

Burst Read followed by Burst Write: RL = 5, WL = (RL-1) = 4, BL = 4

T0

T1

Tn-1

Tn

Tn+1

Tn+2

Tn+3

Tn+4

Tn+5

CK/CK

CMD

DQS

Post CAS

READ A

Post CAS

WRITE A

NOP

t_RTW(Read to Write turn around time)

RL =5

WL = RL - 1 = 4

DQ’s

DOUT A₀

DIN A₀

DOUT A₁

DOUT A₂

DOUT A₃

DIN A₁

DIN A₂

DIN A₃

The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around-

time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.

- 39 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Seamless Burst Read Operation: RL = 5, AL = 2, and CL = 3, BL=4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

DQS

Post CAS

READ A4

Post CAS

READ A0

NOP

CL =3

AL = 2

RL = 5

DQs

DOUT A₀

DOUT A₄

DOUT A₁

DOUT A₂

DOUT A₃

DOUT A₅

DOUT A₆

The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation,

and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the

banks are activated.

- 40 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Reads Intrrupted by a Read

Burst read can only be interrupted by another read with 4 bit burst boundary. Any other case of read interrupt is not

allowed.

Read Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, BL=8)

CK/CK

Read B

Read A

NOP

CMD

DQS/DQS

DQs

A0

A1

A2

A3

B0

B1

B2

B3

B4

B5

B6

B7

Notes:

1. Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.

2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write command or

Precharge command is prohibited.

3. Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst interrupt

timings are prohibited.

4. Read burst interruption is allowed to any bank inside DRAM.

5. Read burst with Auto Precharge enabled is not allowed to interrupt.

6. Read burst interruption is allowed by another Read with Auto Precharge command.

7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst.

For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register

and not the actual burst (which is shorter because of interrupt).

- 41 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Burst Write Operation

The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the

clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL)

minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the

WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the

preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on succes-

sive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any addi-

tional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete.

The time from the completion of the burst write to bank precharge is the write recovery time (WR).

gDDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the setting of

the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by

which the gDDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are

measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are

measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by

design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary

pin, DQS, must be tied externally to VSS through a 20 ohm to 10K ohm resistor to insure proper operation.

t

DQSL

DQSH

DQS

DQS/

DQS

t

WPST

WPRE

V_IH(ac)

V_IH(dc)

DQ

DM

D

V_IL(ac)

V_IL(dc)

t

DH

t

DH

DS

t

DS

V_IH(ac)

V_IH(dc)

DMin

V_IL(ac)

V_IL(dc)

Burst Write Operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4

T0

CK/CK

T1

T2

T3

T4

T5

T6

T7

Tn

CMD ^{Posted CAS}

NOP

< = t_DQSS

NOP

Precharge

WRITE A

Completion of

the Burst Write

DQS

DQs

WL = RL - 1 = 4

> = WR

DIN A₀

DIN A₁

DIN A₂

DIN A₃

- 42 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Burst Write Operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

Tn

CK/CK

CAS

WRITE A

NOP

< = t_DQSS

NOP

Precharge

NOP

Bank A

Activate

CMD

DQS

DQs

Completion of

the Burst Write

WL = RL - 1 = 2

> = tRP

> = WR

DIN A₀

DIN A₁

DIN A₂

DIN A₃

Burst Write followed by Burst Read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK/CK

CMD

Write to Read = CL - 1 + BL/2 + tWTR

Post CAS

READ A

NOP

DQS

CL = 3

AL = 2

WL = RL - 1 = 4

RL =5

> = tWTR

DQ

DOUT A₀

DIN

DOUT A₁

DOUT A₂

DOUT A₃

The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 + tWTR]. This

tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from the input buffer into sense

amplifiers in the array. tWTR is defined in AC spec table of this data sheet.

- 43 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Seamless Burst Write Operation: RL = 5, WL = 4, BL=4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

DQS

Post CAS

WRITE A1

Post CAS

WRITE A0

NOP

WL = RL - 1 = 4

DQ’s

DIN A₀

DIN A₁

DIN A₂

DIN A₃

DIN A₁

DIN A₂

DIN A₃

The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation,

every four clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks

are activated.

- 44 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Writes intrrupted by a write

Burst write can only be interrupted by another write with 4 bit burst boundary. Any other case of write interrupt is not

allowed.

Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8)

CK/CK

NOP

Write A

Write B

NOP

CMD

NOP

DQS/DQS

DQs

A2

B2

B3

B4

B5

B6

B7

A0

A1

A3

B0

B1

Notes:

1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.

2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or

Precharge command is prohibited.

3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt

timings are prohibited.

4. Write burst interruption is allowed to any bank inside DRAM.

5. Write burst with Auto Precharge enabled is not allowed to interrupt.

6. Write burst interruption is allowed by another Write with Auto Precharge command.

7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst.

For example, minimum Write to Precharge timing is WL+BL/2+tWR where tWR starts with the rising clock after the

un-interrupted burst end and not from the end of actual burst end.

- 45 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Write data mask

One write data mask (DM) pin for each 8 data bits (DQ) will be supported on gDDR2 SDRAMs, Consistent with the imple-

mentation on gDDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-direc-

tional manner, is internally loaded identically to data bits to insure matched system timing. DM of x16 bit organization is

not used during read cycles.

Data Mask Timing

DQS/

DQS

DQ

V_IH(ac)

V_IL(ac)

V_IH(dc)

V

(dc)

IH

DM

V_IL(dc)

_(ac)V (dc)

V_IL

IL

tDS tDH

Data Mask Function, WL=3, AL=0, BL = 4 shown

Case 1 : min t^DQSS

CK

Write

COMMAND

tWR

tDQSS

DQS/DQS

DQ

DM

Case 2 : max t^DQSS

DQS/DQS

tDQSS

DQ

DM

- 46 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is trig-

gered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be

used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 for

256Mb are used to define which bank to precharge when the command is issued.

Bank Selection for Precharge by Address Bits

Precharged

Bank(s)

A10

BA1

BA0

Remarks

LOW

HIGH

LOW

HIGH

Bank 0 only

Bank 1 only

Bank 2 only

Bank 3 only

All Banks

HIGH

LOW

HIGH

DON’T CARE

Burst Read Operation Followed by Precharge

Minimum Read to precharge command spacing to the same bank = AL + BL/2 clocks.

For the earliest possible precharge, the precharge command may be issued on the rising edge which is “Additive

latency(AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued to the same bank after

the RAS precharge time (t_RP). A precharge command cannot be issued until t_RASis satisfied.

The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that ini-

tiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4

this is the time from the actual read (AL after the Read command) to Precharge command. For BL = 8 this is the time from

AL + 2 clocks after the Read to the Precharge command.

- 47 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Example 1: Burst Read Operation Followed by Precharge:

RL = 4, AL = 1, CL = 3, BL = 4, t

<= 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

DQS

Bank A

Active

Post CAS

READ A

NOP

Precharge

NOP

AL + BL/2 clks

> = t_RP

CL = 3

AL = 1

RL =4

DQ’s

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

> = t_RAS

> = t_RTP

CL =3

Example 2: Burst Read Operation Followed by Precharge:

RL = 4, AL = 1, CL = 3, BL = 8, t

<= 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

DQS

Post CAS

READ A

NOP

Precharge A

NOP

AL + BL/2 clks

CL = 3

AL = 1

RL =4

DQ’s

DOUT A₄

DOUT A₀

DOUT A₅

DOUT A₆

DOUT A₈

DOUT A₁

DOUT A₂

DOUT A₃

> = t_RTP

second 4-bit prefetch

first 4-bit prefetch

- 48 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Example 3: Burst Read Operation Followed by Precharge:

RL = 5, AL = 2, CL = 3, BL = 4, t

<= 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

DQS

Bank A

Activate

Posted CAS

READ A

Precharge A

NOP

AL + BL/2 clks

> = t_RP

AL = 2

CL =3

RL =5

DQ’s

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

> = t_RAS

CL =3

> = t_RTP

Example 4: Burst Read Operation Followed by Precharge:

RL = 6, AL = 2, CL = 4, BL = 4, t <= 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

DQS

Bank A

Activate

Post CAS

READ A

Precharge A

NOP

AL + BL/2 Clks

> = t_RP

AL = 2

CL =4

RL = 6

DQ’s

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

> = t_RAS

CL =4

> = t_RTP

- 49 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Example 5: Burst Read Operation Followed by Precharge:

RL = 4, AL = 0, CL = 4, BL = 8, t

> 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

DQS

Bank A

Activate

Post CAS

READ A

NOP

Precharge A

AL + 2 Clks + max{tRTP;2 tCK}*

> = t_RP

CL =4

RL = 4

AL = 0

DQ’s

DOUT A₀

DOUT A₄

DOUT A₁

DOUT A₂

DOUT A₃

DOUT A₅

DOUT A₆

DOUT A₈

> = t_RAS

> = t_RTP

second 4-bit prefetch

first 4-bit prefetch

* : rounded to next integer

- 50 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Burst Write followed by Precharge

Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR

For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command

can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the

precharge command. No Precharge command should be issued prior to the tWR delay.

Example 1: Burst Write followed by Precharge: WL = (RL-1) =3, BL=4

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

DQS

DQs

Posted CAS

WRITE A

NOP

Precharge A

NOP

Completion of the Burst Write

> = t_WR

WL = 3

DIN A₀

DIN A₁

DIN A₂

DIN A₃

Example 2: Burst Write followed by Precharge: WL = (RL-1) = 4, BL=4

T0

T1

T2

T3

T4

T5

T6

T7

T 9

CK/CK

CMD

DQS

DQs

Posted CAS

WRITE A

NOP

Precharge A

NOP

Completion of the Burst Write

> = t_WR

WL = 4

DIN A₀

DIN A₁

DIN A₂

DIN A₃

- 51 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Com-

mand or the auto-precharge function. When a Read or a Write Command is given to the gDDR2 SDRAM, the CAS timing

accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest

possible moment during the burst read or write cycle. If A10 is low when the READ or WRITE Command is issued, then

normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If

A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto-pre-

charge, a Read Command will execute as normal with the exception that the active bank will begin to precharge on the ris-

ing edge which is CAS latency (CL) clock cycles before the end of the read burst.

Auto-precharge also be implemented during Write commands. The precharge operation engaged by the Auto precharge

command will not begin until the last data of the burst write sequence is properly stored in the memory array.

This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon

CAS latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the

Precharge operation until the array restore operation has been completed (tRAS satisfied) so that the auto precharge com-

mand may be issued with any read or write command.

Burst Read with Auto Precharge

If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The gDDR2 SDRAM

starts an auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than the read with AP command if

tRAS(min) and tRTP are satisfied.

If tRAS(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tRAS(min) is satis-

fied.

If tRTP(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tRTP(min) is satis-

fied.

In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at

the next rising clock edge after this event). So for BL = 4 the minimum time from Read_AP to the next Activate command

becomes AL + (tRTP + tRP)* (see example 2) for BL = 8 the time from Read_AP to the next Activate is AL + 2 + (tRTP +

tRP)*, where “*” means: “rouded up to the next integer”. In any event internal precharge does not start earlier than two

clocks after the last 4-bit prefetch.

A new bank activate (command) may be issued to the same bank if the following two conditions are satisfied simulta-

neously.

(1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.

(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

- 52 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Example 1: Burst Read Operation with Auto Precharge:

RL = 4, AL = 1, CL = 3, BL = 8, t

<= 2 clocks

RTP

T2

T0

T1

T3

T4

T5

T6

T7

T 8

CK/CK

Bank A

Activate

Post CAS

READ A

NOP

CMD

Autoprecharge

AL + BL/2 clks

> = t_RP

DQS

DQ’s

CL = 3

AL = 1

RL =4

DOUT A₄

DOUT A₀

DOUT A₅

DOUT A₆

DOUT A₈

DOUT A₁

DOUT A₂

DOUT A₃

> = t_RTP

second 4-bit prefetch

first 4-bit prefetch

t_RTP

Precharge begins here

Example 2: Burst Read Operation with Auto Precharge:

RL = 4, AL = 1, CL = 3, BL = 4, t

> 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

DQS

Bank A

Activate

Post CAS

READ A

NOP

Autoprecharge

> = AL + tRTP + tRP

CL = 3

AL = 1

RL =4

DQ’s

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

4-bit prefetch

t_RP

t_RTP

Precharge begins here

- 53 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Example 3: Burst Read with Auto Precharge Followed by an activation to the Same Bank

(tRC Limit):

RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, t

<= 2 clocks)

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

DQS

A10 = 1

Bank A

Activate

Post CAS

READ A

NOP

> = tRas(min)

Auto Precharge Begins

> = t_RP

AL = 2

CL =3

RL = 5

DQ’s

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

CL =3

> = t_RC

Example 4: Burst Read with Auto Precharge Followed by an Activation to the Same Bank

(tRP Limit):

RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, t

<= 2 clocks)

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

DQS

A10 = 1

Bank A

Activate

Post CAS

READ A

NOP

> = tRas(min)

Auto Precharge Begins

> = t_RP

AL = 2

CL =3

RL = 5

DQ’s

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

CL =3

> = t_RC

- 54 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Burst Write with Auto-Precharge

If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The gDDR2 SDRAM

automatically begins precharge operation after the completion of the burst write plus write recovery time (tWR). The bank

undergoing auto-precharge from the completion of the write burst may be reactivated if the following two conditions are

satisfied.

(1) The data-in to bank activate delay time (WR + tRP) has been satisfied.

(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

Burst Write with Auto-Precharge (tRC Limit): WL = 2, tWR =2, tRP=3, BL=4

T0

T1

T2

T3

T4

T5

T6

T7

Tm

CK/CK

A10 = 1

Bank A

Active

Post CAS

NOP

CMD_{WRA BankA}

NOP

Auto Precharge Begins

NOP

Completion of the Burst Write

DQS/DQS

DQs

> = t_RP

> = WR

WL =RL - 1 = 2

DIN A₀

DIN A₁

DIN A₂

DIN A₃

> = t_RC

Burst Write with Auto-Precharge (tWR + tRP): WL = 4, tWR =2, tRP=3, BL=4

T0

T3

T4

T5

T6

T7

T8

T9

T12

CK/CK

A10 = 1

Bank A

Active

Post CAS

NOP

CMD_{WRA Bank A}

DQS/DQS

DQs

NOP

Auto Precharge Begins

NOP

Completion of the Burst Write

> = WR

WL =RL - 1 = 4

> = t_RP

DIN A₀

DIN A₁

DIN A₂

DIN A₃

> = t_RC

- 55 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Precharge & Auto Precharge Clarification

Minimum Delay beween”From Com-

mand” to “To Command”

From Command

To Command

Unit

Notes

Precharge ( to same Bank as Read w/AP)

Precharge All

AL + BL/2 + tRTP - 2 * tCK

WL + BL/2 + WR

1 * tCK

clks

1, 2

2

Read w/AP

Precharge ( to same Bank as Write w/AP)

Precharge All

Write w/AP

Precharge

2

Precharge ( to same Bank as Precharge)

Precharge All

2

1 * tCK

2

Precharge

1 * tCK

2

Precharge All

1 * tCK

2

Notes:

1. The value of tRTP is decided by the equation : max( RU<tRTP/tCK>, 2) where RU stands for round up. This is required

to cover the max tCK case, which is 8 ns.

2. For a given bank, the precharge period of tRP should be counted from the latest precharge command issued to that

bank. Similarly, the precharge period of tRPall should be counted from the latest precharge all command ossued to the

DRAM.

2.2.7 Refresh Command

When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Refresh mode

(REF). All banks of the gDDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the

Refresh command (REF) can be applied. An address counter, internal to the device, supplies the bank address during the

refresh cycle. No control of the external address bus is required once this cycle has started.

When the refresh cycle has completed, all banks of the gDDR2 SDRAM will be in the precharged (idle) state. A delay

between the Refresh command (REF) and the next Activate command or subsequent Refresh command must be greater

than or equal to the Refresh cycle time (tRFC).

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval

is provided. A maximum of eight Refresh commands can be posted to any given gDDR2 SDRAM, meaning that the maxi-

mum absolute interval between any Refresh command and the next Refresh command is 9 * tREFI.

T0

T1

T2

T3

Tm

Tn

Tn + 1

CK/CK

High

> = t_RP

> = t_RFC

CKE

Precharge

NOP

REF

NOP

ANY

NOP

CMD

- 56 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Self Refresh Operation

The gDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is

defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off

before issuing Self Refresh command, by either driving ODT pin low or using EMRS command. Once the Command is reg-

istered, CKE must be held low to keep the device in Self Refresh mode. When the gDDR2 SDRAM has entered Self

Refresh mode all of the external signals except CKE, are “don’t care”. Since CKE is an SSTL 2 input, VREF must be main-

tained during Self Refresh operation. The DRAM initiates a minimum of one one Auto Refresh command internally within

tCKE period once it enters Self Refresh mode. The clock is internally disabled during Self Refresh Operation to save

power. The minimum time that the gDDR2 SDRAM must remain in Self Refresh mode is tCKE. The user may change the

external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must

be restarted and stable before the device can exit Self Refresh operation. Once Self Refresh Exit command is registered, a

delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device.

CKE must remain high for the entire Self Refresh exit period tXSRD for proper operation. Upon exit from Self Refresh, the

gDDR2 SDRAM can be put back into Self Refresh mode after tXSRD expires. NOP or deselect commands must be regis-

tered on each positive clock edge during the Self Refresh exit interval. ODT should also be turned off during tXSRD. Upon

exit from Self Refresh, the gDDR2 SDRAM requires a minimum of one extra auto refresh command before it is put back

into Self Refresh mode.

T3

T4

T5

T6

T0

T1

T2

Tm

Tn

tCK

tCH tCL

CK

> = tXSNR

> = tXSRD

tRP*

V_IH(AC)

CKE

ODT

V_IL(AC)

tIS

tAOFD

V_IL(AC)

tIS

tIH

tIS

V_IH(AC)

V_IH(DC)

Self

_(AC)Refresh ^V_IL^(DC)

Valid

NOP

CMD

V_IL

- Device must be in the “All banks idle” state prior to entering Self Refresh mode.

- ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again

when tXSRD timing is satisfied.

- tXSRD is applied for a Read or a Read with autoprecharge command

- tXSNR is applied for any command except a Read or a Read with autoprecharge command.

- 57 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Power-Down

Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE is not

allowed to go low while mode register or extended mode register command time, or read or write operation is in progress.

CKE is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, or auto-refresh

is in progress, but power-down IDD spec will not be applied until finishing those operations. Timing diagrams are shown in

the following pages with details for entry into power down.

The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down

mode for proper read operation. DRAM design guarantees it’s DLL in a locked state with any CKE intensive operations as

long as DRAM controller complies with DRAM specifications. Following figures show two examples of CKE intensive appli-

cations. In both examples, DRAM maintains DLL in a locked state throughout the period.

CK

CKE

tCKE

DRAM maintains DLL in locked state with intensive CKE operation

CK

CKE

tXP

tCKE

CMD

REF

tREFI = 7.8 us

The pattern shown above can repeat over a long period of time. With this pattern,

DRAM maintains DLL in a locked state with temperature and voltage drift.

- 58 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs

when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates

the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering precharge power-

down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down

mode, CKE low and a stable clock signal must be maintained at the inputs of the gDDR2 SDRAM, and ODT should be in

a valid state but all other input signals are “Don’t Care”. CKE low must be maintained until tCKE has been satisfied.

Power-down duration is limited by 9 times tREFI of the device.

The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command).

CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-

down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined at AC spec table of

this data sheet.

Basic Power Down Entry and Exit timing diagram

CK/CK

t

IH

t

IH

t

IH

IS

IH

IS

V_IH(AC)

V_IH(DC)

V_IH(AC)

CKE

V_IL(DC)

V_IH(DC)

VALID

t

V_IL(AC)

VALID

NOP

VALID

NOP

Command

t

XP, XARD,

CKE

t

CKE

XARDS

t

CKE

Enter Power-Down mode

Don’t Care

Exit Power-Down mode

- 59 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Read to power down entry

T0

T1

T2

Tx

Tx+1

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6 Tx+7

Tx+8

Tx+9

CK

Read operation starts with a read command and

CKE should be kept high until the end of burst operation.

CMD

CKE

DQ

RD

BL=4

AL + CL

Q

DQS

T0

T1

T2

Tx

Tx+1

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6 Tx+7

Tx+8

Tx+9

CMD

CKE

RD

BL=8

CKE should be kept high until the end of burst operation.

AL + CL

DQ

Q

DQS

Read with Autoprecharge to power down entry

T0

T1

T2

Tx

Tx+1

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6 Tx+7

Tx+8

Tx+9

CK

CMD

RDA

PRE

BL=4

AL + BL/2

with tRTP = 7.5ns

& tRAS min satisfied

CKE should be kept high

until the end of burst operation.

CKE

DQ

AL + CL

Q

DQS

T0

T1

T2

Tx

Tx+1

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6 Tx+7

Tx+8

Tx+9

Start internal precharge

CMD

RDA

PRE

AL + BL/2

BL=8

with tRTP = 7.5ns

CKE should be kept high

& tRAS min satisfied

until the end of burst operation.

CKE

DQ

AL + CL

Q

DQS

- 60 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Write to power down entry

T0

T1

Tm

Tm+1 Tm+2 Tm+3 Tx

Tx+1

Tx+2

Ty

Ty+1

Ty+2

Ty+3

CK

CMD

WR

BL=4

CKE

WL

D

DQ

DQS

tWTR

T0

T1

Tm

Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx

Tx+1 Tx+2

Tx+3

Tx+4

CMD

CKE

DQ

WR

BL=8

WL

D

tWTR

DQS

Write with Autoprecharge to power down entry

T0

T1

Tm

Tm+1 Tm+2 Tm+3 Tx

Tx+1

Tx+2

Tx+3 Tx+4

Tx+5

Tx+6

CK

CMD

WRA

PRE

BL=4

CKE

DQ

WL

D

WR*1

DQS

T0

T1

Tm

Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx

Tx+1 Tx+2

Tx+3

Tx+4

CK

CMD

WRA

PRE

BL=8

CKE

DQ

WL

D

WR^*1

DQS

* 1: WR is programmed through MRS

- 61 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Refresh command to power down entry

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

CK

CMD

REF

CKE can go to low one clock after an Auto-refresh command

CKE

Active command to power down entry

CMD

CKE

ACT

CKE can go to low one clock after an Active command

Precharge/Precharge all command to power down entry

PR or

PRA

CMD

CKE can go to low one clock after a Precharge or Precharge all command

CKE

MRS/EMRS command to power down entry

MRS or

EMRS

CMD

CKE

tMRD

- 62 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Asynchronous CKE Low Event

DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this data sheet. If CKE asynchronously

drops “LOW” during any valid operation DRAM is not guaranteed to preserve the contents of array. If this event occurs,

memory controller must satisfy DRAM timing specification tDelay before turning off the clocks. Stable clocks must exist at

the input of DRAM before CKE is raised “HIGH” again. DRAM must be fully re-initialized (steps 4 thru 13) as described in

initialization sequence. DRAM is ready for normal operation after the initialization sequence. See AC timing parametric

table for tDelay specification

Stable clocks

tCK

CK#

CK

tDelay

CKE

CKE asynchronously drops low

Clocks can be turned

off after this point

- 63 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Input Clock Frequency Change during Precharge Power Down

gDDR2 SDRAM input clock frequency can be changed under following condition:

gDDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level. A min-

imum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input clock fre-

quency is allowed to change only within minimum and maximum operating frequency specified for the particular speed

grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock fre-

quency is changed, stable new clocks must be provided to DRAM before precharge power down may be exited and DLL

must be RESET via EMRS after precharge power down exit. Depending on new clock frequency an additional MRS com-

mand may need to be issued to appropriately set the WR, CL etc.. During DLL re-lock period, ODT must remain off. After

the DLL lock time, the DRAM is ready to operate with new clock frequency.

Clock Frequency Change in Precharge Power Down Mode

T0

T1

T2

T4

Tx

Tx+1

Ty

Ty+1

Ty+2 Ty+3 Ty+4

Tz

CK

DLL

RESET

NOP

Valid

CMD

CKE

Frequency Change

Occurs here

200 Clocks

ODT

tRP

tAOFD

tXP

ODT is off during

DLL RESET

Stable new clock

before power down exit

Minimum 2 clocks

required before

changing frequency

- 64 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

No Operation Command

The No Operation Command should be used in cases when the gDDR2 SDRAM is in an idle or a wait state. The purpose

of the No Operation Command (NOP) is to prevent the gDDR2 SDRAM from registering any unwanted commands

between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the ris-

ing edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a

burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is

brought high at the rising edge of the clock, the RAS, CAS, and WE signals become don’t cares.

- 65 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Command Truth Table.

Command truth table.

CKE

BA0

BA1

Function

CS

RAS

CAS

WE

A11

A10 A9 - A0 Notes

Previous Current

Cycle

(Extended) Mode Register Set

Refresh (REF)

H

L

H

L

H

L

H

L

H

X

H

L

BA

X

OP Code

1,2

1

X

Self Refresh Entry

L

X

1

X

H

L

X

H

L

Self Refresh Exit

L

H

X

1,7

Single Bank Precharge

Precharge all Banks

Bank Activate

H

X

BA

X

L

X

1,2

1

L

H

L

H

L

BA

X

Row Address

1,2

Write

H

X

H

X

H

Column

X

L

H

L

Column 1,2,3,

Column 1,2,3

Write with Auto Precharge

Read

L

H

X

H

X

H

Read with Auto-Precharge

No Operation

L

H

X

H

X

H

X

H

X

1

Device Deselect

X

Power Down Entry

Power Down Exit

H

L

X

1,4

H

1. All gDDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.

2. Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode

Register.

3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes inter-

rupted by a Write"

4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh

requirements outlined

5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

6. “X” means “H or L (but a defined logic level)”.

7. Self refresh exit is asynchronous.

8. VREF must be maintained during Self Refresh operation.

- 66 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Clock Enable (CKE) Truth Table for Synchronous Transitions

CKE

Command (N) ³

Current State ²

Action (N) ³

Notes

Previous Cycle ¹Current Cycle ¹

RAS, CAS, WE, CS

(N-1)

(N)

L

X

Maintain Power-Down

Power Down Exit

11, 13, 15

4, 8, 11,13

11, 15

Power Down

L

H

L

DESELECT or NOP

X

Maintain Self Refresh

Self Refresh Exit

Self Refresh

Bank(s) Active

All Banks Idle

L

H

L

DESELECT or NOP

REFRESH

4, 5,9

H

Active Power Down Entry

Precharge Power Down Entry

Self Refresh Entry

4,8,10,11,13

4, 8, 10,11,13

6, 9, 11,13

7

L

H

Refer to the Command Truth Table

Notes:

1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge N.

3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).

4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t

period. Read commands may

XSNR

be issued only after t

(200 clocks) is satisfied.

XSRD

6. Self Refresh mode can only be entered from the All Banks Idle state.

7. Must be a legal command as defined in the Command Truth Table.

8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.

9. Valid commands for Self Refresh Exit are NOP and DESELECT only.

10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or Precharge opera-

tions are in progress. See section "Power Down" and "Self Refresh Command" for a detailed list of restrictions.

11. Minimum CKE high time is three clocks.; minimum CKE low time is three clocks.

12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements out-

lined.

14. CKE must be maintained high while the SDRAM is in OCD calibration mode .

15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high or low in Power

Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1) ).

16. VREF must be maintained during Self Refresh operation.

DM Truth Table

Name (Functional)

Write enable

DM

DQs

Note

-

Valid

1

H

X

1

Write inhibit

1. Used to mask write data, provided coincident with the corresponding data

- 67 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Input Signal Overshoot/Undershoot Specification

AC Overshoot/Undershoot Specification for Address and Control Pins A0-A15, BA0-BA2, CS, RAS, CAS, WE,

CKE, ODT

Specification

Parameter

- 37

0.9V

- 30

0.9V

Maximum peak amplitude allowed for overshoot area (See following figyre):

Maximum peak amplitude allowed for undershoot area (See following figure):

Maximum overshoot area above VDD (See following figure).

0.9V

0.56 V-ns

0.45 V-ns

Maximum undershoot area below VSS (See following figure).

Maximum Amplitude

Overshoot Area

VDD

Volts

(V)

VSS

Undershoot Area

Maximum Amplitude

Time (ns)

AC Overshoot and Undershoot Definition for Address and Control Pins

AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Pins DQ, DQS, DM, CK, CK

Specification

Parameter

- 37

0.9V

-30

Maximum peak amplitude allowed for overshoot area (See following figure):

Maximum peak amplitude allowed for undershoot area (See following figure):

Maximum overshoot area above VDDQ (See following figure):

0.9V

0.28 V-ns

0.23 V-ns

Maximum undershoot area below VSSQ (See following figure):

Maximum Amplitude

Overshoot Area

VDDQ

Volts

(V)

VSSQ

Undershoot Area

Maximum Amplitude

Time (ns)

AC Overshoot and Undershoot Definition for Clock, Data, Strobe, and Mask Pins

- 68 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Table 1. Full Strength Default Pulldown Driver Characteristics

Pulldow n Current (mA)

Nominal Default

Low (18 ohms)

Nominal Default

High (18 ohms)

Voltage (V) Minimum (23.4 Ohms)

Maximum (12.6 Ohms)

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

8.5

11.3

16.5

21.2

25.0

28.3

30.9

33.0

34.5

35.5

36.1

36.6

36.9

37.1

37.4

37.6

37.7

37.9

11.8

16.8

22.1

27.6

32.4

36.9

40.9

44.6

47.7

50.4

52.6

54.2

55.9

57.1

58.4

59.6

60.9

15.9

23.8

31.8

39.7

47.7

55.0

62.3

69.4

75.3

80.5

84.6

87.7

90.8

92.9

94.9

97.0

99.1

101.1

12.1

14.7

16.4

17.8

18.6

19.0

19.3

19.7

19.9

20.0

20.1

20.2

20.3

20.4

20.6

Figure 1. gDDR2 Default Pulldown Characteristics for Full Strength Driver

120

100

80

60

40

20

Maximum

Nominal

Default

High

Nominal

Default

Low

Minimum

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9

VOUT to VSSQ (V)

- 69 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

Table 2. Full Strength Default Pullup Driver Characteristics

Pullup Current (mA)

Nominal Default

Low (18 ohms)

Nominal Default

High (18 ohms)

Voltage (V) Minimum (23.4 Ohms)

Maximum (12.6 Ohms)

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

-8.5

-11.1

-16.0

-20.3

-24.0

-27.2

-29.8

-31.9

-33.4

-34.6

-35.5

-36.2

-36.8

-37.2

-37.7

-38.0

-38.4

-38.6

-11.8

-17.0

-22.2

-27.5

-32.4

-36.9

-40.8

-44.5

-47.7

-50.4

-52.5

-54.2

-55.9

-57.1

-58.4

-59.6

-60.8

-15.9

-23.8

-31.8

-39.7

-47.7

-55.0

-62.3

-69.4

-75.3

-80.5

-84.6

-87.7

-90.8

-92.9

-94.9

-97.0

-99.1

-101.1

-12.1

-14.7

-16.4

-17.8

-18.6

-19.0

-19.3

-19.7

-19.9

-20.0

-20.1

-20.2

-20.3

-20.4

-20.6

Figure 2. gDDR2 Default Pullup Characteristics for Full Strength Output Driver

0

-20

-40

Minimum

Nominal

Default

Low

-60

Nominal

Default

High

-80

-100

-120

Maximum

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0.3

0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

VDDQ to VOUT (V)

- 70 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

gDDR2 SDRAM Default Output Driver V–I Characteristics

gDDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS1 bits

A7-A9 = ‘111’. Figures 1 and 2 show the driver characteristics graphically, and tables 1 and 2 show the same data in tabu-

lar format suitable for input into simulation tools. The driver characteristics evaluation conditions are:

Nominal Default 25 ^oC (T case), VDDQ = 1.8 V, typical process

Minimum TBD ^oC (T case), VDDQ = 1.7 V, slow–slow process

Maximum 0 ^oC (T case), VDDQ = 1.9 V, fast–fast process

Default Output Driver Characteristic Curves Notes:

1) The full variation in driver current from minimum to maximum process, temperature, and voltage will

lie within the outer bounding lines of the V–I curve of figures 1 and 2.

2) It is recommended that the ”typical” IBIS V–I curve lie within the inner bounding lines of the V–I curves

of figures 1 and 2.

Table 3. Full Strength Calibrated Pulldown Driver Characteristics

Calibrated Pulldow n Current (mA)

Nominal Minimum Nominal Low (18.75

Nominal High (17.25 Nominal Maximum (15

Voltage (V)

Nominal (18 ohms)

(21 ohms)

ohms)

0.2

0.3

0.4

9.5

10.7

16.0

21.0

11.5

16.6

21.6

11.8

17.4

23.0

13.3

20.0

27.0

14.3

18.7

Table 4. Full Strength Calibrated Pullup Driver Characteristics

Calibrated Pullup Current (mA)

Nominal Minimum Nominal Low (18.75

Nominal High (17.25Nominal Maximum (15

Voltage (V)

Nominal (18 ohms)

(21 ohms)

ohms)

0.2

0.3

0.4

-9.5

-14.3

-18.7

-10.7

-16.0

-21.0

-11.4

-16.5

-21.2

-11.8

-17.4

-23.0

-13.3

-20.0

-27.0

gDDR2 SDRAM Calibrated Output Driver V–I Characteristics

gDDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the proce-

dure outlined in Off-Chip Driver (OCD) Impedance Adjustment. Tables 3 and 4 show the data in tabular format suitable for

input into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high

values represent the range that can be achieved with a maximum 1.5 ohm step size with no calibration error at the exact

nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification).

Real system calibration error needs to be added to these values. It must be understood that these V-I curves as repre-

sented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system calibration error.

Since this is a system specific phenomena, it cannot be quantified here. The values in the calibrated tables represent just

the DRAM portion of uncertainty while looking at one DQ only. If the cali

- 71 -

Rev 1.5 (Mar. 2005)

256M gDDR2 SDRAM

K4N56163QF-GC

bration procedure is used, it is possible to cause the device to operate outside the bounds of the default

device characteristics tables and figures. In such a situation, the timing parameters in the specification cannot be guaran-

teed. It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum

default values at all times. If this can’t be guaranteed by the system calibration procedure, re-calibration policy, and uncer-

tainty with DQ to DQ variation, then it is recommended that only the default values be used. The nominal maximum and

minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature

change from the nominal condition to the maximum and minimum conditions. If calibrated at an extreme condition, the

amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. The driver

characteristics evaluation conditions are:

Nominal 25 ^oC (T case), VDDQ = 1.8 V, typical process

Nominal Low and Nominal High 25 ^oC (T case), VDDQ = 1.8 V, any process

Nominal Minimum TBD ^oC (T case), VDDQ = 1.7 V, any process

Nominal Maximum 0 ^oC (T case), VDDQ = 1.9 V, any process

- 72 -

Rev 1.5 (Mar. 2005)


型号：	K4N56163QF-ZC300
厂家：	SAMSUNG
描述：	DDR DRAM, 16MX16, 0.45ns, CMOS, PBGA84, LEAD FREE, FBGA-84 动态存储器双倍数据速率内存集成电路
文件：	总72页 (文件大小：1249K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K4N56163QF-ZC300 [SAMSUNG]

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