K4R571669E-GCN1_技术文档

™

K4R571669E

Direct RDRAM

256Mbit RDRAM^(E-die)

512K x 16bit x 32s banks

Direct RDRAM^TM

Version 1.4

January 2004

Version 1.4 Jan. 2004

Page -1

™

K4R571669E

Direct RDRAM

Change History

Version 1.4( Jan. 2004)

- First Copy ( Version 1.4x is named to unify the version of component and device operation datasheets)

- Based on the 256/288Mb D-die Version 1.4

Version 1.4 Jan. 2004

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K4R571669E

Direct RDRAM

Overview

The RDRAM^device is a general purpose high-perfor-

mance memory device suitable for use in a broad range of

applications including computer memory, graphics, video

and any other application where high bandwidth and low

latency are required.

SAMSUNG 350

K4R571669E- GC

The 256Mbit RDRAM devices are extremely high-speed

CMOS DRAMs organized as 16M words by 16 bits. The use

of Rambus Signaling Level (RSL) technology permits up to

1200 MHz transfer rates while using conventional system

and board design technologies. RDRAM devices are capable

of sustained data transfers up to 0.883ns per two bytes (6.7ns

per sixteen bytes).

xx

The architecture of RDRAM devices allows the highest

sustained bandwidth for multiple, simultaneous randomly

addressed memory transactions. The separate control and

data buses with independent row and column control yield

over 95% bus efficiency. The RDRAM device's 32 banks

support up to four simultaneous transactions.

Figure 1: Direct RDRAM CSP Package

The 256Mbit RDRAM devices are offered in a CSP hori-

zontal package suitable for desktop as well as low-profile

add-in card and mobile applications.

System oriented features for mobile, graphics and large

memory systems include power management and byte

masking. .

Key Timing Parameters/Part Numbers

Features

Speed

t_RAC

♦ Highest sustained bandwidth per DRAM device

- 2.4GB/s sustained data transfer rate

- Separate control and data buses for maximized

efficiency

Organization

512Kx16x32s^a

Part Number

I/O

(Row

Access

Time) ns

Bin

Freq.

MHz

- Separate row and column control buses for

easy scheduling and highest performance

- 32 banks: four transactions can take place simul-

taneously at full bandwidth data rates

-CN1 1200

-CT9 1066

-CM8 800

32

32P

40

K4R571669E-G^bC^cN1

K4R571669E-GCT9

K4R571669E-GCM8

K4R571669E-GCK8

-CK8

800

45

♦ Low latency features

- Write buffer to reduce read latency

- 3 precharge mechanisms for controller flexibility

- Interleaved transactions

a.“32s” - 32 banks which use a “split” bank architecture.

b.“G” - WBGA lead-free package.

♦ Advanced power management:

c.“C” - RDRAM core uses normal power self refresh.

- Multiple low power states allows flexibility in power

consumption versus time to transition to active state

- Power-down self-refresh

♦ Organization: 2kbyte pages and 32 banks, x 16

- x16 organization for low cost applications

♦ Uses Rambus Signaling Level (RSL) for up to 1200MHz

operation

Version 1.4 Jan. 2004

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K4R571669E

Direct RDRAM

Pinouts and Definitions

Center-Bonded Devices

package are shown in a later section. Refer to Section

“Center-Bonded WBGA Package” on page 18. Note - pin #1

is at the A1 position.

These tables shows the pin assignments of the center-bonded

RDRAM package. The mechanical dimensions of this

Table 1: Center-Bonded Device (top view)

V_DD

GND

V_DD

GND

V_DD

GND

V_DD

10

9

8

7

6

5

4

3

2

1

V_DD

CMD

V_DD

GND

GNDa

V_DD

GND

RQ5

GND

RQ3

V_DD

GND

V_CMOS

DQB7

V_DD

DQA8

DQA7

DQA5

DQA3

DQA1

CTMN

CTM

RQ7

RQ1

DQB1

DQB3

DQB5

DQB8

GND

DQA6

SCK

DQA4

DQA2

GND

DQA0

V_DD

CFM

GND

CFMN

V_DDa

RQ6

RQ4

GND

RQ2

V_DD

RQ0

GND

DQB0

GND

DQB2

V_DD

DQB4

SIO0

DQB6

SIO1

GND

V_CMOS

V_REF

V_DD

GND

V_DD

GND

V_DD

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

S

ROW

COL

SAMSUNG 350

K4R571669E- GC

xx

Top View

Chip

The pin #1(ROW 1, COL A) is located at the

A1 position on the top side and the A1 position

is marked by the marker “ ”.

Version 1.4 Jan. 2004

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K4R571669E

Direct RDRAM

Table 2: Pin Description

Description

# Pins

center

Signal

I/O

Type

SIO1,SIO0

I/O

CMOS^a

2

1

Serial input/output. Pins for reading from and writing to the control regis-

ters using a serial access protocol. Also used for power management.

CMD

SCK

I

CMOS^a

Command input. Pins used in conjunction with SIO0 and SIO1 for reading

from and writing to the control registers. Also used for power manage-

ment.

1

Serial clock input. Clock source used for reading from and writing to the

control registers

V_DD

20

1

Supply voltage for the RDRAM core and interface logic.

Supply voltage for the RDRAM analog circuitry.

Supply voltage for CMOS input/output pins.

V_DDa

V_CMOS

GND

2

24

2

Ground reference for RDRAM core and interface.

Ground reference for RDRAM analog circuitry.

GNDa

DQA8..DQA0

I/O

RSL^b

9

Data byte A. Nine pins which carry a byte of read or write data between

the Channel and the RDRAM device. DQA8 is not used (no connection)

by RDRAM device with a x16 organization.

CFM

I

RSL^b

1

Clock from master. Interface clock used for receiving RSL signals from

the Channel. Positive polarity.

CFMN

Clock from master. Interface clock used for receiving RSL signals from

the Channel. Negative polarity

V_REF

1

Logic threshold reference voltage for RSL signals

CTMN

I

RSL^b

Clock to master. Interface clock used for transmitting RSL signals to the

Channel. Negative polarity.

CTM

I

1

3

5

9

Clock to master. Interface clock used for transmitting RSL signals to the

Channel. Positive polarity.

RQ7..RQ5 or

ROW2..ROW0

Row access control. Three pins containing control and address informa-

tion for row accesses.

RQ4..RQ0 or

COL4..COL0

I

Column access control. Five pins containing control and address informa-

tion for column accesses.

DQB8..

DQB0

I/O

Data byte B. Nine pins which carry a byte of read or write data between

the Channel and the RDRAM device. DQB8 is not used (no connection)

by RDRAM device with a x16 organization.

Total pin count per package

84

a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.

b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.

Version 1.4 Jan. 2004

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K4R571669E

Direct RDRAM

RQ7..RQ5 or

ROW2..ROW0

3

RQ4..RQ0 or

DQB8..DQB0

9

CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN

COL4..COL0

5

DQA8..DQA0

9

2

RCLK

1:8 Demux

TCLK

RCLK

6

Control Registers

Packet Decode

COLC

ROWR

11

ROWA

9

COLX

5

COLM

5

7

8

ROP DR BR

AV

R

REFR

DEVID

XOP DX BX COP DC BC

C

MB MA

Power Modes

M

S

Match

Mux

Match

Write

Buffer

DM

Row Decode

XOP Decode

PRER

ACT

PREX

Mux

Column Decode & Mask

PREC

RD, WR

DRAM Core

Sense Amp

64x64

512x128x128

64x64

64

Internal DQB Data Path

Internal DQA Data Path

64

Bank 0

Bank 1

Bank 2

64

9

Bank 13

Bank 14

Bank 15

9

Bank 16

Bank 17

Bank 18

9

Bank 29

Bank 30

Bank 31

Figure 2: 256Mbit (512Kx16x32s) RDRAM Device Block Diagram

Version 1.4 Jan. 2004

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K4R571669E

Direct RDRAM

amps of the RDRAM device. These pins are de-multiplexed

into a 24-bit ROWA (row-activate) or ROWR (row-opera-

tion) packet.

General Description

Figure 2 is a block diagram of the 256Mbit RDRAM device.

It consists of two major blocks: a “core” block built from

banks and sense amps similar to those found in other types

of DRAM and a Direct Rambus^TMinterface block which

permits an external controller to access this core at up to

2.4GB/s.

COL Pins: The principle use of these five pins is to

manage the transfer of data between the DQA/DQB pins and

the sense amps of the RDRAM device. These pins are de-

multiplexed into a 23-bit COLC (column-operation) packet

and either a 17-bit COLM (mask) packet or a 17-bit COLX

(extended-operation) packet.

Control Registers: The CMD, SCK, SIO0, and SIO1

pins appear in the upper center of Figure 2. They are used to

write and read a block of control registers. These registers

supply the RDRAM configuration information to a

controller and they select the operating modes of the device.

The REFR value is used for tracking the last refreshed row.

Most importantly, the five bit DEVID specifies the device

address of the RDRAM device on the Channel.

ACT Command: An ACT (activate) command from an

ROWA packet causes one of the 512 rows of the selected

bank to be loaded to its associated sense amps (two 512

bytes sense amps for DQA and two for DQB).

PRER Command: A PRER (precharge) command from

an ROWR packet causes the selected bank to release its two

associated sense amps, permitting a different row in that

bank to be activated, or permitting adjacent banks to be acti-

vated.

Clocking: The CTM and CTMN pins (Clock-To-Master)

generate TCLK (Transmit Clock), the internal clock used to

transmit read data. The CFM and CFMN pins (Clock-From-

Master) generate RCLK (Receive Clock), the internal clock

signal used to receive write data and to receive the ROW and

COL pins.

RD Command: The RD (read) command causes one of

the 128 dualocts of one of the sense amps to be transmitted

on the DQA/DQB pins of the Channel.

DQA,DQB Pins: These 16 pins carry read (Q) and write

(D) data across the Channel. They are multiplexed/de-multi-

plexed from/to two 64bit data paths (running at one-eighth

the data frequency) inside the RDRAM device.

WR Command: The WR (write) command causes a

dualoct received from the DQA/DQB data pins of the

Channel to be loaded into the write buffer. There is also

space in the write buffer for the BC bank address and C

column address information. The data in the write buffer is

automatically retired (written with optional bytemask) to one

of the 128 dualocts of one of the sense amps during a subse-

quent COP command. A retire can take place during a RD,

WR, or NOCOP to another device, or during a WR or

NOCOP to the same device. The write buffer will not retire

during a RD to the same device. The write buffer reduces the

delay needed for the internal DQA/DQB data path turn-

around.

Banks: The 32Mbyte core of the RDRAM device is

divided into thirty two 1Mbyte banks, each organized as 512

rows, with each row containing 128 dualocts, and each

dualoct containing 16 bytes. A dualoct is the smallest unit of

data that can be addressed.

Sense Amps: The RDRAM device contains 34 sense

amps. Each sense amp consists of 1kbyte of fast storage (512

bytes for DQA and 512 bytes for DQB) and can hold one-

half of one row of one bank of the RDRAM device. The

sense amp may hold any of the 1024 half-rows of an associ-

ated bank. However, each sense amp is shared between two

adjacent banks of the RDRAM device (except for sense

amps 0, 15, 16, and 31). This introduces the restriction that

adjacent banks may not be simultaneously accessed.

PREC Precharge: The PREC, RDA and WRA

commands are similar to NOCOP, RD and WR, except that a

precharge operation is performed at the end of the column

operation. These commands provide a second mechanism

for performing precharge.

PREX Precharge: After a RD command, or after a WR

command with no byte masking (M=0), a COLX packet may

be used to specify an extended operation (XOP). The most

important XOP command is PREX. This command provides

a third mechanism for performing precharge.

RQ Pins: These pins carry control and address informa-

tion. They are broken into two groups. RQ7..RQ5 are also

called ROW2..ROW0, and are used primarily for controlling

row accesses. RQ4..RQ0 are also called COL4..COL0, and

are used primarily for controlling column accesses.

ROW Pins: The principle use of these three pins is to

manage the transfer of data between the banks and the sense

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K4R571669E

Direct RDRAM

The AV (ROWA/ROWR packet selection) bit distinguishes

between the two packet types. Both the ROWA and ROWR

packet provide a five bit device address and a five bit bank

address. An ROWA packet uses the remaining bits to specify

a nine bit row address, and the ROWR packet uses the

remaining bits for an eleven bit opcode field. Note the use of

the “RsvX” notation to reserve bits for future address field

extension.

Packet Format

Figure 3 shows the formats of the ROWA and ROWR

packets on the ROW pins. Table 3 describes the fields which

comprise these packets. DR4T and DR4F bits are encoded to

contain both the DR4 device address bit and a framing bit

which allows the ROWA or ROWR packet to be recognized

by the RDRAM device.

Table 3: Field Description for ROWA Packet and ROWR Packet

Description

Field

DR4T,DR4F

DR3..DR0

BR4..BR0

AV

Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit.

Device address for ROWA or ROWR packet.

Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM device.

Selects between ROWA packet (AV=1) and ROWR packet (AV=0).

R8..R0

Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM device.

Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.

ROP10..ROP0

Figure 3 also shows the formats of the COLC, COLM, and

COLX packets on the COL pins. Table 4 describes the fields

which comprise these packets.

The remaining 17 bits are interpreted as a COLM (M=1) or

COLX (M=0) packet. A COLM packet is used for a COLC

write command which needs bytemask control. The COLM

packet is associated with the COLC packet from at least t_RTR

earlier. A COLX packet may be used to specify an indepen-

dent precharge command. It contains a five bit device

address, a five bit bank address, and a five bit opcode. The

COLX packet may also be used to specify some house-

keeping and power management commands. The COLX

packet is framed within a COLC packet but is not otherwise

associated with any other packet.

The COLC packet uses the S (Start) bit for framing. A

COLM or COLX packet is aligned with this COLC packet,

and is also framed by the S bit.

The 23 bit COLC packet has a five bit device address, a five

bit bank address, a seven bit column address, and a four bit

opcode. The COLC packet specifies a read or write

command, as well as some power management commands.

Table 4: Field Description for COLC Packet, COLM Packet, and COLX Packet

Description

Field

S

Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets.

Device address for COLC packet.

DC4..DC0

BC4..BC0

C6..C0

Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0 ’ s).

Column address for COLC packet. RsvC denotes bits ignored by the RDRAM device.

Opcode field for COLC packet. Specifies read, write, precharge, and power management functions.

Selects between COLM packet (M=1) and COLX packet (M=0).

COP3..COP0

M

MA7..MA0

MB7..MB0

DX4..DX0

BX4..BX0

XOP4..XOP0

Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0.

Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0.

Device address for COLX packet.

Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0’ s).

Opcode field for COLX packet. Specifies precharge, I_OLcontrol, and power management functions.

Version 1.4 Jan. 2004

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T

11

0

1

2

3

8

9

10

CTM/CFM

DR2 BR0 BR3 RsvR R8

DR1 BR1 BR4 RsvR R7

R5

R4

R3

R2

R1

R0

DR2 BR0 BR3 ROP10 ROP8 ROP5 ROP2

DR1 BR1 BR4 ROP9 ROP7 ROP4 ROP1

DR4F

ROW2 DR4T

ROW1

ROW2 DR4T

ROW1

DR4F

ROW0 DR3 DR0 BR2 RsvB AV=1 R6

ROW0 DR3 DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0

ROWA Packet

ROWR Packet

T

3

T₀T₁T₂T₃T₄T₅T₆T₇T₈T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅

0

1

2

CTM/CFM

ROW2

..ROW0

DC4 S=1

DC3

C6

C5

C4

C3

ACT a0

WR b1

PRER c0

COL4

COL3

COL2

COL1

COL0

t_PACKET

COL4

..COL0

MSK (b1) PREX d0

COP1

RsvB BC2 C2

BC4 BC1 C1

DC2

DQA8..0

DQB8..0

DC1 COP0

COP2

COP3 BC3 BC0 C0

DC0

COLC Packet

T

15

8

9

10

11

12

13

14

CTM/CFM

a

b

COL4

COL3

COL2

COL1

S=1 MA7 MA5 MA3 MA1

M=1 MA6 MA4 MA2 MA0

MB7 MB4 MB1

COL4

COL3

COL2

COL1

COL0

S=1 DX4 XOP4 RsvB BX1

M=0 DX3 XOP3 BX4 BX0

DX2 XOP2 BX3

MB6 MB3 MB0

DX1 XOP1 BX2

COL0

MB5 MB2

DX0 XOP0

a

b

The COLM is associated with a

previous COLC, and is aligned

with the present COLC, indicated

by the Start bit (S=1) position.

The COLX is aligned

with the present COLC,

indicated by the Start

bit (S=1) position.

COLM Packet

COLX Packet

Figure 3: Packet Formats

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broadcast operation is indicated when both bits are set.

Field Encoding Summary

Broadcast operation would typically be used for refresh and

power management commands. If the device is selected, the

DM (DeviceMatch) signal is asserted and an ACT or ROP

command is performed.

Table 5 shows how the six device address bits are decoded

for the ROWA and ROWR packets. The DR4T and DR4F

encoding merges a fifth device bit with a framing bit. When

neither bit is asserted, the device is not selected. Note that a

Table 5: Device Field Encodings for ROWA Packet and ROWR Packet

DR4T

DR4F

Device Selection

Device Match signal (DM)

1

0

1

0

1

0

All devices (broadcast)

One device selected

No packet present

DM is set to 1

DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0

DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0

DM is set to 0

Table 6 shows the encodings of the remaining fields of the

ROWA and ROWR packets. An ROWA packet is specified

by asserting the AV bit. This causes the specified row of the

specified bank of this device to be loaded into the associated

sense amps.

row address comes from an internal register REFR, and

REFR is incremented at the largest bank address. The REFP

(refresh-precharge) command is identical to a PRER

command.

The NAPR, NAPRC, PDNR, ATTN, and RLXR commands

are used for managing the power dissipation of the RDRAM

device and are described in more detail in “Power State

Management” on page 50. The TCEN and TCAL commands

are used to adjust the output driver slew rate and they are

described in more detail in “Current and Temperature

Control” on page 56.

An ROWR packet is specified when AV is not asserted. An

11 bit opcode field encodes a command for one of the banks

of this device. The PRER command causes a bank and its

two associated sense amps to precharge, so another row or

an adjacent bank may be activated. The REFA (refresh-acti-

vate) command is similar to the ACT command, except the

Table 6: ROWA Packet and ROWR Packet Field Encodings

ROP10..ROP0 Field

a

DM

AV

Name

Command Description

10

9

8

7

6

5

4

3

2:0

---

0

-

No operation.

b

1

0

Row address

ACT

Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTN .

c

1

0

1

0

1

0

1

x

0

x

0

x

000 PRER

000 REFA

Precharge bank BR4..BR0 of this device.

Refresh (activate) row REFR8..REFR0 of bank BR4..BR0 of device.

Increment REFR if BR4..BR0 = 11111 (see Figure 52).

1

0

1

x

0

x

0

1

0

x

0

x

0

1

0

x

0

1

x

0

1

0

1

x

0

x

0

1

x

0

000 REFP

000 PDNR

000 NAPR

Precharge bank BR4..BR0 of this device after REFA (see Figure 52).

Move this device into the powerdown (PDN) power state (see Figure 49).

Move this device into the nap (NAP) power state (see Figure 49).

000 NAPRC Move this device into the nap (NAP) power state conditionally

b

000 ATTN

000 RLXR

001 TCAL

010 TCEN

Move this device into the attention (ATTN) power state (see Figure 47).

Move this device into the standby (STBY) power state (see Figure 48).

Temperature calibrate this device (see Figure 55).

Temperature calibrate/enable this device (see Figure 55).

000 NOROP No operation.

a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 5.

b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1).

c. An “x” entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000).

Version 1.4 Jan. 2004

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Table 7 shows the COP field encoding. The device must be

in the ATTN power state in order to receive COLC packets.

The COLC packet is used primarily to specify RD (read) and

WR (write) commands. Retire operations (moving data from

the write buffer to a sense amp) happen automatically. See

Figure 18 for a more detailed description.

The COLC packet can also specify a PREC command,

which precharges a bank and its associated sense amps. The

RDA/WRA commands are equivalent to combining RD/WR

with a PREC. RLXC (relax) performs a power mode transi-

tion. See “Power State Management” on page 50.

Table 7: COLC Packet Field Encodings

DC4.. DC0

(select device)

S

COP3..0 Name

Command Description

a

0

----

-----

-

No operation.

Retire write buffer of this device.

1

/= (DEVID4 ..0)

== (DEVID4 ..0)

-----

b

x000

x001

x010

x011

x100

x101

x110

x111

1xxx

NOCOP Retire write buffer of this device.

WR

Retire write buffer of this device, then write column C6..C0 of bank BC4..BC0 to write buffer.

RSRV

RD

Reserved, no operation.

Read column C6..C0 of bank BC4..BC0 of this device.

Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 15).

Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired.

Reserved, no operation.

PREC

WRA

RSRV

RDA

RLXC

Same as RD, but precharge bank BC4..BC0 afterward.

Move this device into the standby (STBY) power state (see Figure 48).

a. “/=” means not equal, “==” means equal.

b. An “x” entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001).

Table 8 shows the COLM and COLX field encodings. The

M bit is asserted to specify a COLM packet with two 8 bit

bytemask fields MA and MB. If the M bit is not asserted, an

COLX is specified. It has device and bank address fields,

and an opcode field. The primary use of the COLX packet is

to permit an independent PREX (precharge) command to be

specified without consuming control bandwidth on the ROW

pins. It is also used for the CAL(calibrate) and SAM (sam-

ple) current control commands (see “Current and Tempera-

ture Control” on page 56), and for the RLXX power mode

command (see “Power State Management” on page 50).

Table 8: COLM Packet and COLX Packet Field Encodings

DX4 .. DX0

(selects device)

M

XOP4..0

Name

Command Description

1

----

-

MSK

MB/MA bytemasks used by WR/WRA.

0

/= (DEVID4 ..0)

== (DEVID4 ..0)

-

No operation.

00000

1xxx0

x10x0

x11x0

xxx10

xxxx1

NOXOP

PREX

CAL

No operation.

a

Precharge bank BX3..BX0 of this device (see Figure 15).

Calibrate (drive) I current for this device (see Figure 54).

OL

CAL/SAM

RLXX

RSRV

Calibrate (drive) and Sample ( update) I current for this device (see Figure 54).

OL

Move this device into the standby (STBY) power state (see Figure 48).

Reserved, no operation.

a. An “x” entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).

Version 1.4 Jan. 2004

Page 9

™

K4R571669E

Direct RDRAM

Electrical Conditions

Table 9: Electrical Conditions

Parameter and Conditions

Junction temperature under bias

Supply voltage

Symbol

Min

Max

Unit

T

-

100

2.50 + 0.13

2.0

°C

V

J

V

2.50 - 0.13

DD, DDA

V

Supply voltage droop (DC) during NAP interval (t

)

-

%

DD,N, DDA,N

NLIMIT

v

Supply voltage ripple (AC) during NAP interval (t

)

-2.0

2.0

DD,N, DDA,N

Supply voltage for CMOS pins (2.5V controllers)

Supply voltage for CMOS pins (1.8V controllers)

V

a

DD

V

CMOS

REF

1.80 - 0.1

1.80 + 0.2

Reference voltage

1.40 - 0.2

1.40 + 0.2

V

RSL data input - low voltage @ t

=1.667ns

=1.875ns

=2.50ns

V

- 0.5

V

- 0.15

- 0.2

CYCLE

REF

V

RSL data input - low voltage @ t

V

DIL

REF

RSL data input - low voltage @ t

b

V

REF

RSL data input - high voltage @ t

=1.667ns

=1.875ns

=2.50ns

V

+ 0.15

+ 0.2

V

+ 0.5

CYCLE

REF

b

V

RSL data input - high voltage @ t

V

DIH

DA

V

b

RSL data input - high voltage @ t

V

REF

R

RSL data asymmetry : R = (V

- V ) / (V

- V

)

0.67

1.00

-

DA

DIH

REF

DIL

V

RSL clock input - common mode V = (V +V /2

CIL)

1.3

0.35

0.225

1.8

V

CM

CIH

RSL clock input swing: V = V

- V

(CTM,CTMN pins).

(CFM,CFMN pins).

1.00

CIS,CTM

CIS,CFM

IL,CMOS

IH,CMOS

CIS

CIH

CIL

RSL clock input swing: V = V

CIS

- V

c

CMOS input low voltage

CMOS input high voltage

- 0.3

V

/2 - 0.25

d

CMOS

V

/2 + 0.25

V

+0.3

CMOS

a. V

b. V

must remain on as long as V is applied and cannot be turned off.

DD

CMOS

is typically equal to V

(1.8V±0.1V) under DC conditions in a system.

TERM

DIH

c. Voltage undershoot is limited to -0.7V for a duration of less than 5ns.

d. Voltage overshoot is limited toV +0.7V for a duration of less than 5ns

CMOS

Version 1.4 Jan. 2004

Page 10

™

K4R571669E

Direct RDRAM

Electrical Characteristics

Table 10: Electrical Characteristics

Symbol

Parameter and Conditions

Junction-to-Case thermal resistance

current @ V

Min

Max

Unit

Θ

-

0.5

10

°C/Watt

µA

JC

REF

OH

I

V

-10

32.0

30.0

-

REF

REF,MAX

RSL output high current @ (0≤V

≤V

)

10

µA

OUT

DD

a

RSL I current @ t

= 1.667ns V = 0.9V, V

, T

90.0

1.5

-

OL

CYCLE

OL

DD,MIN

J,MAX

I

RSL I current @ t

= 1.875ns V = 0.9V, V

mA

ALL

OL

DD,MIN

J,MAX

a

RSL I current @ t

=2.50ns V = 0.9V, V

, T

OL

DD,MIN J,MAX

∆I

RSL I current resolution step

mA

OL

r

I

Dynamic output impedance @ V = 0.9V

OL

150

27.1

26.6

-10.0

-

Ω

OUT

b,c

RSL I current @ V = 1.0V @ t

=1.667ns

30.1

30.6

10.0

0.3

-

OL

CYCLE

b,c

RSL I current @ V = 1.0V @ t

=1.875ns

=2.5ns

mA

OL,NOM

I,CMOS

OL

b,c

RSL I current @ V = 1.0V @ t

OL

CMOS input leakage current @ (0≤V

≤V

)

CMOS

µA

V

I,CMOS

V

CMOS output voltage @ I

= 1.0mA

OL,CMOS

OH,CMOS

OL,CMOS

CMOS output high voltage @ I

= -0.25mA

V

-0.3

V

OH,CMOS

CMOS

a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current.

b. This measurement is made in automatic current control mode after at least 64 current control calibration operations to a device and after CCA and

CCB are initialized to a value of 64. This value applies to all DQA and DQB pins.

c. This measurement is made in automatic current control mode in a 25Ω test system with V

= 1.714V and V = 1.357V and with the ASYMA

REF

TERM

and ASYMB register fields set to 0.

Version 1.4 Jan. 2004

Page 11

™

K4R571669E

Direct RDRAM

Timing Conditions

Table 11: Timing Conditions

Parameter

CTM and CFM cycle times (-1200)

CTM and CFM cycle times (-1066)

CTM and CFM cycle times (-800)

Symbol

Min

Max

Unit

Figure(s)

1.667

1.875

2.50

2.5

t

ns

Figure 56

CYCLE

3.33

CTM and CFM input rise and fall times. Use the minimum value of

these parameters during testing. (-1200)

0.2

0.45

, t

ns

Figure 56

CR CF

CTM and CFM input rise and fall times. Use the minimum value of

these parameters during testing. (-1066,-800)

0.2

0.5

t

, t

CTM and CFM high and low times

40%

60%

t

CH CL

CYCLE

CTM-CFM differential (MSE/MS=0/0)

CTM-CFM differential (MSE/MS=1/1)

0.0

0.9

1.0

a

CYCLE

Figure 43

Figure 56

TR

CTM-CFM differential for 1.875ns and 1.667ns (MSE/MS=1/0)

Domain crossing window

-0.1

0.1

t

Figure 62

Figure 57

DCW

CYCLE

DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the

minimum value of these parameters during testing.@ t

0.2

0.45

0.65

=1.667ns

CYCLE

DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the

minimum value of these parameters during testing.@ t

t

, t

ns

DR DF

=1.875ns

CYCLE

DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the

minimum value of these parameters during testing.@ t

=2.50ns

CYCLE

b

DQA/DQB/ROW/COL-to-CFM set/hold @ t

SIO0, SIO1 input rise and fall times

=1.667ns

=1.875ns

=2.50ns

0.140

CYCLE

b,c

t , t

0.160

-

ns

Figure 57

S

H

b.d

0.200

-

t

5.0

ns

Figure 59

DR1, DF1

t

CMD, SCK input rise and fall times

-

2.0

-

DR2, DF2

SCK cycle time - Serial control register transactions

1000

7.5

10

SCK cycle time - Power transitions @ t

=1.667ns

-

CYCLE

t

ns

Figure 59

CYCLE1

=1.875ns

=2.50ns

-

SCK high and low times @ t

=1.667ns

=1.875ns

=2.50ns

3.5

4.25

1.0

1.25

1

-

CYCLE

, t

-

CH1 CL1

-

e

CMD setup time to SCK rising or falling edge @ t

=1.667ns

=1.875ns

=2.50ns

-

CYCLE

e

t

CMD setup time to SCK rising or falling edge @ t

-

ns

Figure 59

S1

e

CMD setup time to SCK rising or falling edge @ t

-

e

CMD hold time to SCK rising or falling edge

-

H1

Version 1.4 Jan. 2004

Page 12

™

K4R571669E

Direct RDRAM

Table 11: Timing Conditions

Parameter

SIO0 setup time to SCK falling edge

Symbol

Min

Max

Unit

Figure(s)

t

40

0

-

ns

Figure 59

Figure 50

Figure 60

Figure 50

Figure 49

Figure 54

Figure 50

Figure 49

Figure 48

Figure 47

Figure 52

S2

SIO0 hold time to SCK falling edge

-

H2

PDEV setup time on DQA5..0 to SCK rising edge.

PDEV hold time on DQA5..0 to SCK rising edge.

ROW2..0, COL4..0 setup time for quiet window

-

S3

5.5

-1

5

-

H3

-

t

S4

CYCLE

f

ROW2..0, COL4..0 hold time for quiet window

-

H4

Quiet on ROW/COL bits during NAP/PDN entry

Offset between read data and CC packets (same device)

Offset between CC packet and read data (same device)

CTM/CFM stable before NAP/PDN exit

CTM/CFM stable after NAP/PDN entry

ROW packet to COL packet ATTN framing delay

Maximum time in NAP mode

4

-

NPQ

12

8

-

READTOCC

-

CCSAMTOREAD

2

-

CE

100

7

CD

-

FRM

NLIMIT

REF

CYCLE

ms

10.0

32

Refresh interval

ms

Interval after PDN or NAP (with self-refresh) exit in which all

banks of the RDRAM device must be refreshed at least once.

t

200

Figure 53

BURST

t

Current control interval

34 t

100ms

ms/t

CYCLE

Figure 54

Figure 55

CCTRL

CYCLE

Temperature control interval

TCE command to TCAL command

TCAL command to quiet window

Quiet window (no read data)

100

ms

TEMP

150

2

-

2

-

t

TCEN

CYCLE

ms

TCAL

140

TCQUIET

t

RDRAM device delay (no RSL operations allowed)

200.0

page 38

PAUSE

a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.

b. t and t for other t values can be interpolated between or extrapolated from the timings at the 2 specified t values.

CYCLE

S,MIN

H,MIN

CYCLE

c. This parameter also applies to a-1200 part when operated with t

= 1.875ns

CYCLE

d. This parameter also applies to a-1200 or -1066 part when operated with t

= 2.50ns

CYCLE

e. With V

=0.5V

-0.4V and V

=0.5V

+0.4V

IL,CMOS

CMOS

IH,CMOS

CMOS

f. Effective hold becomes t ’=t +[PDNXA•64•t

+t

]-[PDNX•256•t

] if [PDNX•256•t

] < [PDNXA•64•t

H4 H4

SCYCLE PDNXB,MAX

SCYCLE

SCYCLE SCY-

+t

]. See Figure 50

CLE PDNXB,MAX

Version 1.4 Jan. 2004

Page 13

™

K4R571669E

Timing Characteristics

Symbol

Direct RDRAM

Table 12: Timing Characteristics

Parameter

Min

Max

Unit

Figure(s)

a

CTM-to-DQA/DQB output time @ t

=1.667ns

=1.875ns

=2.5ns

-0.170

+0.170

CYCLE

a,b

t

CTM-to-DQA/DQB output time @ t

-0.195

+0.195

+0.260

0.32

0.45

10

ns

Figure 58

Q

a,c

-0.260

DQA/DQB output rise and fall times @ t

=1.667ns

0.2

CYCLE

t

, t

=1.875ns

=2.5ns

0.2

ns

QR QF

0.2

-

t

SCK(neg)-to-SIO0 delay @ C

SCK(pos)-to-SIO0 delay @ C

= 20pF (SD read data valid).

= 20pF (SD read data hold).

ns

µs

Figure 61

Figure 50

Figure 48

Figure 49

Q1

LOAD,MAX

2

-

HR

, t

SIO

rise/fall @ C = 20pF

LOAD,MAX

12

QR1 QF1

OUT

SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C

= 20pF

LOAD,MAX

-

20

PROP1

NAPXA

NAPXB

PDNXA

PDNXB

AS

NAP exit delay - phase A

-

50

NAP exit delay - phase B

-

40

PDN exit delay - phase A

-

4

PDN exit delay - phase B

-

9000

t

CYCLE

ATTN-to-STBY power state delay

STBY-to-ATTN power state delay

ATTN/STBY-to-NAP power state delay

ATTN/STBY-to-PDN power state delay

-

1

0

8

-

SA

-

ASN

-

ASP

a. t

and t

for other t

values can be interpolated between or extrapolated from the timings at the 3 specified t

values.

Q,MIN

Q,MAX

CYCLE

b. This parameter also applies to a-1200 part when operated with t

= 1.875ns

CYCLE

c. This parameter also applies to a-1200 or -1066 part when operated with t

= 2.50ns

CYCLE

Version 1.4 Jan. 2004

Page 14

™

K4R571669E

Direct RDRAM

Timing Parameters

Table 13: Timing Parameter Summary

Min Min Min Min

Parameter

Description

-32 -32P -40 -45

-1200 -1066 -800 -800

Max Units Figure(s)

Row Cycle time of RDRAM banks -the interval between ROWA packets with

ACT commands to the same bank.

Figure 16

t

32

22

28

20

28

20

28

20

-

t

RC

CYCLE

Figure 17

RAS-asserted time of RDRAM bank - the interval between ROWA packet with

Figure 16

Figure 17

a

b

t

ACT command and next ROWR packet with PRER command to the same

64µs

t

RAS

bank.

Row Precharge time of RDRAM banks - the interval between ROWR packet

Figure 16

Figure 17

a

t

with PRER command and next ROWA packet with ACT command to the

10

8

-

t

RP

CYCLE

same bank.

Precharge-to-precharge time of RDRAM device - the interval between succes-

t

8

-

t

Figure 13

Figure 14

PP

CYCLE

a

sive ROWR packets with PRER commands to any banks of the same device.

RAS-to-RAS time of RDRAM device - the interval between successive

ROWA packets with ACT commands to any banks of the same device.

RR

CYCLE

RAS-to-CAS Delay - the interval from ROWA packet with ACT command to

COLC packet with RD or WR command). Note - the RAS-to-CAS delay seen

Figure 16

Figure 17

t

9

7

9

-

t

RCD

CYCLE

by the RDRAM core (t

) is equal to t

= 1 + t

because of differ-

RCD

RCD-C

ences in the row and column paths through the RDRAM interface.

CAS Access delay - the interval from RD command to Q read data. The equa-

Figure 5

t

9

6

4

8

6

4

8

6

4

8

6

4

8

12

6

-

t

CAC

CYCLE

tion for t

is given in the TPARM register in Figure 40.

Figure 40

CAC

CAS Write Delay (interval from WR command to D write data.

Figure 5

CWD

CC

CAS-to-CAS time of RDRAM bank - the interval between successive COLC

commands).

Figure 16

Figure 17

Length of ROWA, ROWR, COLC, COLM or COLX packet.

4

-

Figure 3

PACKET

RTR

Interval from COLC packet with WR command to COLC packet which causes

retire, and to COLM packet with bytemask.

Figure 18

The interval (offset) from COLC packet with RDA command, or from COLC

packet with retire command (after WRA automatic precharge), or from COLC

packet with PREC command, or from COLX packet with PREX command to

Figure 15

Figure 40

t

4

t

OFFP

CYCLE

the equivalent ROWR packet with PRER. The equation for t

the TPARM register in Figure 40.

is given in

OFFP

Interval from last COLC packet with RD command to ROWR packet with

PRER.

t

4

-

t

Figure 16

Figure 17

RDP

CYCLE

Interval from last COLC packet with automatic retire command to ROWR

packet with PRER.

RTP

CYCLE

a. Or equivalent PREC or PREX command. See Figure 15.

b. This is a constraint imposed by the core, and is therefore in units of µs rather than t

.

CYCLE

Version 1.4 Jan. 2004

Page 15

™

K4R571669E

Direct RDRAM

Absolute Maximum Ratings

Table 14: Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

V

Voltage applied to any RSL or CMOS pin with respect to Gnd

Voltage on VDD and VDDA with respect to Gnd

Storage temperature

- 0.3

- 0.5

- 50

0

V

+0.3

V

I,ABS

DD,ABS

STORE

MIN

DD

, V

+1.0

DDA,ABS

T

100

Note*

°C

Minimum operation temperature

Note*) Component : refer to T Θ

Module: refre to T

PLATE, MAX

J, JC

I_DD- Supply Current Profile

Table 15: Supply Current Profile

Max

I_DDvalue

RDRAM Power State and Steady-State Transaction Rates^aMin (1200MHz (1066MHz (800MHz Unit

, -32)

, -32P)

, -40/-45)

I

Device in PDN, self-refresh enabled and INIT.LSR=0.

Device in NAP.

-

6000

4

6000

4

6000

4

uA

DD,PDN

DD,NAP

mA

Device in STBY. This is the average for a device in STBY with (1) no

packets on the Channel, and (2) with packets sent to other devices.

I

-

115

170

105

160

95

mA

DD,STBY

Device in STBY and refreshing rows at the t

period.

DD,REFRESH

DD,ATTN

REF,MAX

Device in ATTN. This is the average for a device in ATTN with (1) no

packets on the Channel, and (2) with packets sent to other devices.

135

Device in ATTN. ACT command every 8•t

, PRE command

, and data is 1100..1100

b

CYCLE

I

-

775(x16)

690(x16)

700(x16)

545(x16)

560(x16)

mA

DD,ATTN-W

DD,ATTN-R

every 8•t

, WR command every 4•t

CYCLE

Device in ATTN. ACT command every 8•t

, PRE command

CYCLE

780(x16)

c

every 8•t

, RD command every 4•t

, and data is 1111..1111

CYCLE

a. CMOS interface consumes power in all power states.

b. x16 RDRAM device data width.

c. This does not include the I sink current. The RDRAM device dissipates I •V in each output driver when a logic one is driven.

OL

OL OL

Table 16: Supply Current at Initialization

Symbol

Parameter

Allowed Range of t_CYCLE

V_DD

Min

Max

Unit

a

I

from power -on to SETR

from SETR to CLRR

1.667ns to 2.5ns

V

-

200

mA

DD,PWRUP,D

DD,SETR,D

DD

DD,MIN

332

a. The supply current will be 150mA when t

is in the range 15ns to 1000ns.

CYCLE

Version 1.4 Jan. 2004

Page 16

™

K4R571669E

Direct RDRAM

Capacitance and Inductance

Table 17: RSL Pin Parasitics

Parameter and Conditions - RSL pins

Symbol

Min

Max

3.5

4.0

0.2

0.6

1.8

2.3

2.4

0.1

Unit

Figure

RSL effective input inductance @ t

=1.667ns

=1.875ns

=2.5ns

-

CYCLE

RSL effective input inductance @ t

L_I

nH

Figure 63

-

Mutual inductance between any DQA or DQB RSL signals.

Mutual inductance between any ROW or COL RSL signals.

Difference in L_Ivalue between any RSL pins of a single device.

-

nH

L₁₂

Figure 63

-

∆L_I

-

RSL effective input capacitance^a@ t

=1.667ns

=1.875ns

=2.5ns

2.0

-

CYCLE

C_I

pF

Figure 63

C₁₂

Mutual capacitance between any RSL signals.

pF

Figure 63

Difference in C_Ivalue between average of {CTM, CTMN,

CFM, CFMN} and any RSL pins of a single device.

∆C_I

-

0.06

RSL effective input resistance @ t

=1.667ns

=1.875ns

=2.5ns

4

10

15

CYCLE

R_I

Ω

Figure 63

a. This value is a combination of the device IO circuitry and package capacitances measured at VDD=2.5V and f=400MHz with pin biased at 1.4V.

Table 18: CMOS Pin Parasitics

Symbol

L_{I ,CMOS}

Parameter and Conditions - CMOS pins

CMOS effective input inductance

Min

Max

8.0

Unit

nH

Figure

C_{I ,CMOS}

CMOS effective input capacitance (SCK,CMD)^a

CMOS effective input capacitance (SIO1, SIO0)^a

1.7

2.1

7.0

pF

Figure 63

C_{I ,CMOS,SIO}

-

a. This value is a combination of the device IO circuitry and package capacitances.

Version 1.4 Jan. 2004

Page 17

™

K4R571669E

Direct RDRAM

Center-Bonded WBGA Package

(84balls)

Figure 4 shows the form and dimensions of the recom-

mended package for the 84balls center-bonded WBGA

device class.

D

Bottom

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

S

Bottom

Top

1

2

3

4

A

5

6

7

8

e2

9

10

d

e1

Bottom

E

E1

Figure 4: Center-Bonded WBGA Package

Table lists the numerical values corresponding to dimen-

sions shown in Figure 4.

Table 19 : Center-Bonded WBGA Package Dimensions

Symbol

Parameter

Ball pitch (x-axis)

Min.

Max.

Unit

e1

e2

A

0.80

9.20

13.40

0.90

0.30

0.40

0.80

9.40

13.60

1.00

0.40

0.50

mm

Ball pitch (y-axis)

Package body length

Package body width

Package total thickness

Ball height

D

E

E1

d

Ball diameter

Version 1.4 Jan. 2004

Page 18


型号：	K4R571669E-GCN1
厂家：	SAMSUNG
描述：	Rambus DRAM, 16MX16, 32ns, CMOS, PBGA84 时钟动态存储器内存集成电路
文件：	总20页 (文件大小：308K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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