K4S510732C-TL1L [SAMSUNG]
Synchronous DRAM, 64MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54;
| 型号： | K4S510732C-TL1L |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 64MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4S510732C
CMOS SDRAM
Stacked 512Mbit SDRAM
16M x 8bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 0.1
Sept. 2001
* Samsung Electronics reserves the right to change products or specification without
Rev. 0.1 Sept.2001
K4S510732C
CMOS SDRAM
Revision 0.0 (Mar., 2001)
Revision 0.1 (Sep., 2001)
•
•
•
Corrected Typo.
Redefined IDD1 & IDD4 in DC Characteristics
Changed the Notes in Operating AC Parameter.
< Before >
5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
< After >
5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.1 Sept.2001
K4S510732C
CMOS SDRAM
16M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
The K4S510732C is 536,870,912 bits synchronous high data rate
Dynamic RAM organized as 4 x 16,777,216 words by 8 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system appli-
cations.
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
• Auto & self refresh
K4S510732C-TC/L7C
K4S510732C-TC/L75
K4S510732C-TC/L1H
K4S510732C-TC/L1L
133MHz(CL=2)
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
• 64ms refresh period (8K Cycle)
54pin
LVTTL
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
CLK,CAS,RAS
/WE,DQM
32Mx8
/CS1,CKE1
32Mx8
/CS0,CKE0
DQ0 ~ DQ7
A0~A12,BA0,BA1
* Samsung Electronics reserves the right to change products or specification without notice.
Stakteks’ stacking technology is Samsungs’ stacking technology of choice.
Rev. 0.1 Sept.2001
K4S510732C
CMOS SDRAM
PIN CONFIGURATION (Top view)
VDD
DQ0
VDDQ
N.C
DQ1
VSSQ
N.C
DQ2
VDDQ
N.C
DQ3
VSSQ
N.C
1
2
3
4
5
6
7
8
VSS
DQ7
VSSQ
N.C
DQ6
VDDQ
N.C
DQ5
VSSQ
N.C
DQ4
VDDQ
N.C
VSS
CKE1
DQM
CLK
CKE0
A12
A11
A9
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VDD
CS1
WE
CAS
RAS
CS0
BA0
BA1
A10/AP
A0
A8
A7
A6
A5
A4
VSS
A1
A2
A3
VDD
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitcH)
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System clock
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CS0~1
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE0~1
Clock enable
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
A0 ~ A12
BA0 ~ BA1
RAS
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM
Data input/output mask
DQ0 ~7
Data input/output
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
VDD/VSS
Power supply/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
VDDQ/VSSQ
Data output power/ground
Rev. 0.1 Sept.2001
K4S510732C
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
2
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
3.3
3.0
0
Max
3.6
Unit
V
Note
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
VDD+0.3
0.8
V
1
VIL
V
2
VOH
-
-
V
IOH = -2mA
IOL = 2mA
3
VOL
-
0.4
V
ILI
-10
-
10
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin
Symbol
CCLK
CIN
Min
5.0
5.0
5.0
2.5
8.0
Max
9.0
Unit
pF
pF
pF
pF
pF
Note
Clock
RAS, CAS, WE, DQM
Address
10.0
10.0
6.5
CADD
Ccs
CS#, CKE#
DQ0 ~ DQ8
COUT
14.0
Rev. 0.1 Sept.2001
K4S510732C
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
Parameter
Symbol
Test Condition
Unit Note
-7C
-75 -1H -1L
Burst length = 1
tRC ³ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
120
110 110 110
mA
mA
1
ICC2P
4
4
CKE £ VIL(max), tCC = 10ns
Precharge standby current in
power-down mode
ICC2PS
CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2N
40
20
Precharge standby current in
non power-down mode
mA
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
Input signals are stable
ICC2NS
ICC3P
8
8
CKE £ VIL(max), tCC = 10ns
Active Standby current
in power-down mode
mA
mA
mA
ICC3PS
CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3N
50
35
Active standby current in
non power-down mode
(One bank active)
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
Input signals are stable
ICC3NS
IO = 0 mA
Page burst
4banks activated.
tCCD = 2CLKs
Operating current
(Burst mode)
ICC4
140
240
140 130 130
mA
1
Refresh current
ICC5
ICC6
tRC ³ tRC(min)
220 210 210
mA
mA
mA
2
3
4
C
6
3
Self refresh current
CKE £ 0.2V
L
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S510732C-TC**
4. K4S510732C-TL**
5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Rev. 0.1 Sept.2001
K4S510732C
CMOS SDRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
Vtt = 1.4V
3.3V
50W
1200W
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Z0 = 50W
Output
Output
50pF
50pF
870W
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-7C
15
15
15
45
-75
-1H
20
20
20
50
-1L
20
20
20
50
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
15
20
20
45
ns
ns
ns
ns
us
ns
CLK
-
1
1
1
1
Row precharge time
Row active time
tRAS(min)
tRAS(max)
tRC(min)
100
2
Row cycle time
60
65
70
70
1
2, 5
5
Last data in to row precharge
Last data in to Active delay
tRDL(min)
tDAL(min)
2 CLK + tRP
Last data in to new col. address delay
Last data in to burst stop
tCDL(min)
tBDL(min)
tCCD(min)
1
1
1
2
1
CLK
CLK
CLK
ea
2
2
3
4
Col. address to col. address delay
Number of valid output data
CAS latency=3
CAS latency=2
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.1 Sept.2001
K4S510732C
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
-7C
-75
-1H
-1L
Parameter
Symbol
tCC
Unit Note
Min
7.5
7.5
Max
Min
7.5
10
Max
Min
10
Max
Min
Max
CAS latency=3
10
12
CLK cycle time
1000
1000
1000
1000
ns
ns
ns
1
1,2
2
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
10
5.4
5.4
5.4
6
6
6
6
7
CLK to valid
output delay
tSAC
3
3
3
3
3
3
2
1
1
3
3
3
3
2
1
1
Output data
hold time
tOH
3
3
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
tSH
tSLZ
Input hold time
CLK to output in Low-Z
CAS latency=3
CAS latency=2
5.4
5.4
5.4
6
6
6
6
7
CLK to output
in Hi-Z
tSHZ
ns
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 0.1 Sept.2001
K4S510732C
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
A11,A12,
A9 ~ A0
CKEn-1
H
CKEn
CS
L
RAS
L
CAS
L
WE
L
DQM
X
BA0,1
A10/AP
Note
Command
Register
Refresh
Mode register set
Auto refresh
X
H
L
OP code
1,2
3
H
L
L
L
L
H
X
X
X
X
Entry
3
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
Column
address
(A0 ~ A9)
Read &
column address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
L
L
H
H
L
L
H
L
Column
address
(A0 ~ A9)
Write &
column address
H
X
X
V
H
4,5
6
Burst Stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Bank selection
All banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
No operation command
(V=Valid, X=Don't care, H=Logic high)
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.1 Sept.2001
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