K4S51323LC-MS1L [SAMSUNG]
Synchronous DRAM, 16MX32, 7ns, CMOS, PBGA90, FBGA-90;
| 型号： | K4S51323LC-MS1L |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 16MX32, 7ns, CMOS, PBGA90, FBGA-90 动态存储器 |
| 文件： | 总8页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4S51323LC-MG/S
CMOS SDRAM
16Mx32
Mobile SDRAM
90FBGA
( VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V, PASR & TCSR )
Revision 1.2
December 2002
Rev. 1.2 Dec. 2002
K4S51323LC-MG/S
CMOS SDRAM
4M x 32Bit x 4 Banks Mobile SDRAM
FEATURES
GENERAL DESCRIPTION
• 2.5V power supply
The K4S51323LC is 536,870,912 bits synchronous high data
rate Dynamic RAM organized as 4 x 4,196,304 words by 32bits,
fabricated with SAMSUNG's high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth and high performance memory system
applications.
• LVCMOS compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (1, 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
ORDERING INFORMATION
• Burst read single-bit write operation
• Special Function Support.
Part No.
Max Freq.
Interface Package
K4S51323LC-MG/S1H
100MHz(CL=2)
-. PASR (Partial Array Self Refresh).
-. TCSR (Temperature Compensated Self Refresh).
• DQM for masking
*1
K4S51323LC-MG/S1L
K4S51323LC-MG/S15
100MHz(CL=3)
LVCMOS 90FBGA
*2
66MHz(CL=2/3)
• Auto & self refresh
-MS ; Super Low Power, Operating Temp : -25°C ~ 85°C.
-MG ; Low Power, Operating Temp : -25°C ~ 85°C.
Notes :
1. In case of 40MHz Frequency, CL1 can be supported.
2. In case of 33MHz Frequency, CL1 can be supported.
• 64ms refresh period (8K cycle)
• Extended Temperature Operation (-25°C ~ 85°C).
• 90balls DDP FBGA
FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
4M x 32
4M x 32
4M x 32
4M x 32
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 Dec. 2002
K4S51323LC-MG/S
CMOS SDRAM
Package Dimension and Pin Configuration
*1
*2
< Bottom View >
< Top View >
E
1
90Ball(6x15) CSP
9
8
7
6
5
4
3
2
1
1
2
3
7
8
9
A
B
C
D
E
F
A
B
C
D
E
F
DQ26 DQ24
VSS
VSSQ
VDD
VDDQ
DQ23 DQ21
VSSQ DQ19
DQ28
VSSQ
VSSQ
VDDQ
VSS
VDDQ
DQ27 DQ25 DQ22 DQ20
DQ29 DQ30 DQ17 DQ18
VDDQ
VDDQ
VSSQ
VDD
DQ31
DQM3
A5
NC
A3
NC
A2
DQ16
DQM2
A0
G
H
J
G
H
J
A4
A6
A10
NC
A1
A7
A8
A12
A9
BA1
CS
A11
CLK
CKE
NC
BA0
CAS
VDD
DQ6
DQ1
VDDQ
VDD
RAS
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ2
K
L
K
L
DQM1
VDDQ
VSSQ
VSSQ
DQ11
NC
VSS
DQ9
WE
DQ8
DQ10
DQ7
DQ5
DQ3
VSSQ
DQ0
M
N
P
R
M
N
P
R
DQ12 DQ14
VDDQ
VSSQ
VSS
DQ13 DQ15
E
E/2
Pin Name
Pin Function
System Clock
*2: Top View
CLK
CS
Chip Select
CKE
Clock Enable
A0 ~ A12
BA0 ~ BA1
RAS
Address
A
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
A1
Max. 0.20
Encapsulant
z
b
CAS
*1: Bottom View
WE
*2
< Top View >
DQM0 ~DQM3
DQ0 ~ 31
VDD/VSS
VDDQ/VSSQ
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
#A1 Ball Origin Indicator
[Unit:mm]
Symbol
Min
Typ
1.30
0.32
9.50
6.40
15.50
11.20
0.80
0.45
-
Max
A
1.20
1.40
A
0.27
0.37
1
1
1
E
-
-
E
-
-
D
-
-
-
D
-
e
b
z
-
0.40
-
-
0.50
0.10
Rev. 1.2 Dec. 2002
K4S51323LC-MG/S
CMOS SDRAM
ABSOLUTE MAXIMUM
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
1
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Notes :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C to 85°C)
Parameter
Supply voltage
Symbol
VDD
VDDQ
VIH
Min
Typ
Max
Unit
Note
2.3
2.5
2.7
V
V
1.65
-
-
2.7
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
0.8 x VDDQ
VDDQ + 0.3
V
1
VIL
-0.3
0
-
0.3
-
V
2
VOH
VOL
VDDQ -0.2V
V
IOH = -0.1mA
IOL = 0.1mA
3
-
-
0.2
10
V
ILI
-10
-
uA
Notes :
1. VIH (max) = 3.0V AC.The overshoot voltage duration is £ 3ns.
2. VIL (min) = -1.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V £ VOUT £ VDDQ.
CAPACITANCE (VDD = 2.5V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin
Symbol
CCLK
CIN
Min
3.0
3.0
1.5
3.0
3.0
Max
9.0
9.0
4.5
9.0
6.5
Unit
Note
Clock
pF
pF
pF
pF
pF
RAS, CAS, WE, CKE, CS
DQM
CIN
Address
CADD
COUT
DQ0 ~ DQ31
Rev. 1.2 Dec. 2002
K4S51323LC-MG/S
CMOS SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C to 85°C)
Version
Parameter
Symbol
Test Condition
Unit Note
-1H
-1L
-15
Burst length = 1
tRC ³ tRC(min)
IO = 0 mA
Operating Current
(One Bank Active)
ICC1
145
130
120
mA
mA
1
ICC2P
CKE £ VIL(max), tCC = 10ns
1.5
1.5
Precharge Standby Current
in power-down mode
ICC2PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
ICC2N
30
20
Input signals are changed one time during 20ns
Precharge Standby Current
in non power-down mode
mA
mA
CKE ³ VIH(min), CLK £ VIL (max), tCC = ¥
ICC2NS
Input signals are stable
ICC3P
CKE £ VIL(max), tCC = 10ns
14
14
Active Standby Current
in power-down mode
ICC3PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
ICC3N
46
40
mA
mA
Active Standby Current
in non power-down mode
(One Bank Active)
Input signals are changed one time during 20ns
CKE ³ VIH(min), CLK £ VIL (max), tCC = ¥
ICC3NS
Input signals are stable
IO = 0 mA
Operating Current
(Burst Mode)
Page burst
4Banks Activated
tCCD = 2CLKs
ICC4
210
190
280
160
250
mA
mA
1
2
Refresh Current
ICC5
tRC ³ tRC(min)
320
Max 45
1100
900
TCSR Range
°C
Max 85
1600
1200
950
°C
°C
4 Banks
-MG
-MS
3
4
2 Banks
1 Bank
Self Refresh Current
ICC6
CKE £ 0.2V
800
uA
4 Banks
2 Banks
1 Bank
850
1300
900
600
500
700
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S51323LC-MG**
4. K4S51323LC-MS**
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 1.2 Dec. 2002
K4S51323LC-MG/S
CMOS SDRAM
AC OPERATING TEST CONDITIONS (VDD = 2.5V ± 0.2V, TA = -25°C to 85°C)
Parameter
AC input levels (Vih/Vil)
Value
0.9 x VDDQ / 0.2
0.5 x VDDQ
tr/tf = 1/1
Unit
V
Input timing measurement reference level
Input rise and fall time
V
ns
V
Output timing measurement reference level
Output load condition
0.5 x VDDQ
See Fig. 2
VDDQ
Vtt=0.5 x VDDQ
500W
50W
VOH (DC) = VDDQ-0.2V, IOH = -0.1mA
VOL (DC) = 0.2V, IOL = 0.1mA
30pF
Output
Output
Z0=50W
30pF
500W
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
- 1H
20
-1L
-15
30
30
30
60
Row active to row active delay
RAS to CAS delay
tRRD (min)
tRCD (min)
tRP(min)
20
ns
ns
1
1
1
1
20
24
Row precharge time
20
24
ns
tRAS(min)
tRAS(max)
tRC(min)
50
60
ns
Row active time
100
us
Row cycle time
70
84
90
ns
1
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL (min)
tCDL(min)
tBDL (min)
tCCD (min)
2
CLK
-
2,3
tRDL + tRP
1
1
1
2
1
CLK
CLK
CLK
2
2
3
Col. address to col. address delay
CAS latency=3
CAS latency=2
CAS latency=1
Number of valid output data
ea
4
-
0
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge
command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.2 Dec. 2002
K4S51323LC-MG/S
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
-1H
-1L
- 15
Parameter
Symbol
Unit
Note
Min
10
10
-
Max
Min
10
Max
Min
15
Max
CAS latency=3
CAS latency=2
CAS latency=1
CAS latency=3
CAS latency=2
CAS latency=1
CAS latency=3
CAS latency=2
CAS latency=1
CLK cycle time
tCC
1000
1000
1000
ns
1
12
15
25
30
7
7
-
7
8
9
9
CLK to valid output delay
Output data hold time
tSAC
tOH
ns
ns
1,2
2
20
24
2.5
2.5
-
2.5
2.5
2.5
3
2.5
2.5
2.5
3.5
3.5
3.5
2.0
1
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tC L
tSS
3
ns
ns
ns
ns
ns
3
3
3
3
2
3
3
2.5
1.5
1
2.5
1.5
1
Input hold time
tSH
tSLZ
CLK to output in Low-Z
CAS latency=3
CAS latency=2
CAS latency=1
7
7
-
7
8
9
9
CLK to output in Hi-Z
tSHZ
ns
20
24
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
1. This is to advise Samsung customers that, in accordance with certain terms of an agreement, Samsung is prohibited from
selling any DRAM products configured in "Multi-Die Plastic" format for use as components in general and scientific computers,
such as mainframes, servers, work stations or desk top personal computers (hereinafter "Prohibited Computer Use").
Applications such as mobile, including cell phones, telecom, including televisions and display monitors, or non-desktop
computer systems, including laptops, notebook computers, are, however, permissible. "Multi-Die Plastic" is defined as two or
more DRAM die encapsulated within a single plastic leaded package.
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life
is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of
a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea
repeater use.
Rev. 1.2 Dec. 2002
K4S51323LC-MG/S
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
A11, A12,
A9 ~ A 0
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Register
Refresh
Mode Register Set
Auto Refresh
H
X
H
L
L
L
L
L
X
OP CODE
1, 2
3
H
L
L
L
H
X
X
X
X
Entry
3
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
Refresh
Exit
L
H
H
H
X
X
3
Bank Active & Row Addr.
X
X
V
V
Row Address
Column
Address
(A0~ A8)
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
4
4, 5
4
L
H
L
H
H
Column
Address
(A0~ A8)
Write &
Column Address
L
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
H
4, 5
6
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock Suspend or
Active Power Down
X
X
H
L
Entry
H
Precharge Power Down Mode
X
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
H
L
X
H
X
H
No Operation Command
(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)
Notes :
1. OP Code : Operand Code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
PASR & TCSR can be issued only after setting partial self refresh mode.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
Rev. 1.2 Dec. 2002
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