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K4S643233H-HF1H [SAMSUNG]

Synchronous DRAM, 2MX32, 7ns, CMOS, PBGA90;
K4S643233H-HF1H
型号： K4S643233H-HF1H
厂家： SAMSUNG    SAMSUNG
描述：

Synchronous DRAM, 2MX32, 7ns, CMOS, PBGA90

时钟 动态存储器 内存集成电路
文件： 总12页 (文件大小：141K)
中文：  中文翻译
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K4S643233H - F(H)E/N/G/C/L/F  
Mobile-SDRAM  
512K x 32Bit x 4 Banks Mobile SDRAM in 90FBGA  
FEATURES  
GENERAL DESCRIPTION  
• 3.0V & 3.3V power supply.  
The K4S643233H is 67,108,864 bits synchronous high data  
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,  
fabricated with SAMSUNG’s high performance CMOS technol-  
ogy. Synchronous design allows precise cycle control with the  
use of system clock and I/O transactions are possible on every  
clock cycle. Range of operating frequencies, programmable  
burst lengths and programmable latencies allow the same  
device to be useful for a variety of high bandwidth and high per-  
formance memory system applications.  
• LVCMOS compatible with multiplexed address.  
• Four banks operation.  
• MRS cycle with address key programs.  
-. CAS latency (1, 2 & 3).  
-. Burst length (1, 2, 4, 8 & Full page).  
-. Burst type (Sequential & Interleave).  
• EMRS cycle with address key programs.  
• All inputs are sampled at the positive going edge of the system  
clock.  
• Burst read single-bit write operation.  
• Special Function Support.  
-. PASR (Partial Array Self Refresh).  
-. Internal TCSR (Temperature Compensated Self Refresh)  
• DQM for masking.  
• Auto refresh.  
• 64ms refresh period (4K cycle).  
• Commercial Temperature Operation (-25°C ~ 70°C).  
• Extended Temperature Operation (-25°C ~ 85°C).  
• 90Balls FBGA with 0.8mm ball pitch  
( -FXXX : Leaded, -HXXX : Lead Free).  
ORDERING INFORMATION  
Part No.  
Max Freq.  
Interface  
Package  
K4S643233H-F(H)E/N/G/C/L/F60  
K4S643233H-F(H)E/N/G/C/L/F75  
K4S643233H-F(H)E/N/G/C/L/F1H  
K4S643233H-F(H)E/N/G/C/L/F1L  
166MHz(CL=3)  
133MHz(CL=3)  
105MHz(CL=2)  
90 FBGA  
Leaded (Lead Free)  
LVCMOS  
105MHz(CL=3)*1  
- F(H)E/N/G : Normal / Low / Low Power, Extended Temperature(-25°C ~ 85°C)  
- F(H)C/L/F : Normal / Low / Low Power, Commercial Temperature(-25°C ~ 70°C)  
NOTES :  
1. In case of 40MHz Frequency, CL1 can be supported.  
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.  
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific  
purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.  
February 2004  
K4S643233H - F(H)E/N/G/C/L/F  
Mobile-SDRAM  
FUNCTIONAL BLOCK DIAGRAM  
LWE  
Data Input Register  
LDQM  
Bank Select  
512K x 32  
512K x 32  
512K x 32  
512K x 32  
DQi  
CLK  
ADD  
Column Decoder  
Latency & Burst Length  
LCKE  
Programming Register  
LWCBR  
LRAS  
LCBR  
LWE  
LCAS  
LDQM  
Timing Register  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
DQM  
February 2004  
K4S643233H - F(H)E/N/G/C/L/F  
Mobile-SDRAM  
Package Dimension and Pin Configuration  
< Bottom View*1  
>
< Top View*2  
>
E1  
90Ball(6x15) FBGA  
9
8
7
6
5
4
3
2
1
1
2
3
7
8
9
A
B
C
D
E
F
A
B
C
D
E
F
DQ26 DQ24  
VSS  
VSSQ  
VDD  
VDDQ  
DQ23 DQ21  
DQ28  
VSSQ  
VSSQ  
VDDQ  
VSS  
VDDQ  
VSSQ  
DQ19  
VDDQ  
VDDQ  
VSSQ  
VDD  
DQ27 DQ25 DQ22 DQ20  
DQ29 DQ30 DQ17 DQ18  
DQ31  
DQM3  
A5  
NC  
A3  
NC  
A2  
DQ16  
DQM2  
A0  
G
H
J
G
H
J
A4  
A6  
A10  
NC  
A1  
A7  
A8  
NC  
A9  
BA1  
CS  
NC  
CLK  
CKE  
NC  
BA0  
CAS  
VDD  
DQ6  
DQ1  
VDDQ  
VDD  
RAS  
DQM0  
VSSQ  
VDDQ  
VDDQ  
DQ4  
DQ2  
K
L
K
L
DQM1  
VDDQ  
VSSQ  
VSSQ  
DQ11  
NC  
VSS  
DQ9  
WE  
DQ8  
DQ10  
DQ7  
DQ5  
DQ3  
VSSQ  
DQ0  
M
N
P
R
M
N
P
R
DQ12 DQ14  
VDDQ  
VSSQ  
VSS  
DQ13 DQ15  
E
E/2  
Pin Name  
Pin Function  
System Clock  
Chip Select  
Clock Enable  
Address  
CLK  
CS  
A
CKE  
A1  
A0 ~ A10  
BA0 ~ BA1  
RAS  
Substrate(2Layer)  
z
b
Bank Select Address  
Row Address Strobe  
Column Address Strobe  
Write Enable  
< Top View*2  
>
CAS  
#A1 Ball Origin Indicator  
WE  
DQM0 ~ DQM3  
DQ0 ~ 31  
Data Input/Output Mask  
Data Input/Output  
VDD/VSS  
Power Supply/Ground  
VDDQ/VSSQ  
Data Output Power/Ground  
[Unit:mm]  
Symbol  
Min  
Typ  
1.30  
0.35  
8.00  
6.40  
13.00  
11.20  
0.80  
0.45  
-
Max  
A
A1  
E
-
1.40  
0.30  
0.40  
-
-
E1  
D
-
-
-
-
-
D1  
e
-
-
0.40  
-
-
b
0.50  
0.10  
z
February 2004  
K4S643233H - F(H)E/N/G/C/L/F  
Mobile-SDRAM  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
VIN, VOUT  
VDD, VDDQ  
TSTG  
Value  
-1.0 ~ 4.6  
-1.0 ~ 4.6  
-55 ~ +150  
1.0  
Unit  
V
Voltage on any pin relative to Vss  
Voltage on VDD supply relative to Vss  
Storage temperature  
V
°C  
W
Power dissipation  
PD  
Short circuit current  
IOS  
50  
mA  
NOTES:  
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.  
Functional operation should be restricted to recommended operating condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.  
DC OPERATING CONDITIONS  
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)  
Parameter  
Symbol  
VDD  
VDDQ  
VIH  
Min  
2.7  
2.7  
2.2  
-0.3  
2.4  
-
Typ  
3.0  
3.0  
3.0  
0
Max  
Unit  
V
Note  
3.6  
Supply voltage  
3.6  
V
Input logic high voltage  
Input logic low voltage  
Output logic high voltage  
Output logic low voltage  
Input leakage current  
NOTES :  
VDDQ + 0.3  
V
1
VIL  
0.5  
-
V
2
VOH  
VOL  
-
V
IOH = -2mA  
IOL = 2mA  
3
-
0.4  
10  
V
ILI  
-10  
-
uA  
1. VIH (max) = 5.3V AC.The overshoot voltage duration is ≤ 3ns.  
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.  
3. Any input 0V ≤ VIN ≤ VDDQ.  
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.  
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.  
CAPACITANCE (VDD = 3.0V & 3.3V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)  
Pin  
Symbol  
CCLK  
CIN  
Min  
Max  
4.0  
4.0  
4.0  
4.0  
6.0  
Unit  
Note  
Clock  
-
-
-
-
-
pF  
pF  
pF  
pF  
pF  
RAS, CAS, WE, CS, CKE  
DQM  
CIN  
Address  
CADD  
COUT  
DQ0 ~ DQ31  
February 2004  
K4S643233H - F(H)E/N/G/C/L/F  
Mobile-SDRAM  
DC CHARACTERISTICS  
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)  
Version  
Parameter  
Symbol  
Test Condition  
Unit Note  
-60  
-75  
-1H  
-1L  
Burst length = 1  
tRC ≥ tRC(min)  
IO = 0 mA  
Operating Current  
(One Bank Active)  
ICC1  
85  
80  
75  
75  
mA  
mA  
1
ICC2P CKE ≤ VIL(max), tCC = 10ns  
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞  
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns  
0.5  
0.5  
Precharge Standby Current  
in power-down mode  
ICC2N  
11  
8
Input signals are changed one time during  
20ns  
Precharge Standby Current  
in non power-down mode  
mA  
mA  
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞  
Input signals are stable  
ICC2NS  
ICC3P CKE ≤ VIL(max), tCC = 10ns  
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞  
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns  
5
5
Active Standby Current  
in power-down mode  
ICC3N  
22  
22  
mA  
mA  
Input signals are changed one time during  
20ns  
Active Standby Current  
in non power-down mode  
(One Bank Active)  
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞  
Input signals are stable  
ICC3NS  
IO = 0 mA  
Operating Current  
(Burst Mode)  
Page burst  
4Banks Activated  
tCCD = 2CLKs  
ICC4  
ICC5  
100  
145  
95  
75  
75  
mA  
1
Refresh Current  
Self Refresh Current  
NOTES:  
tRC ≥ tRC(min)  
135  
120  
120  
mA  
uA  
°C  
2
4
5
3
-E/C  
1500  
350  
-N/L  
Internal TCSR  
Max 40  
Max 85/70  
350  
ICC6  
CKE ≤ 0.2V  
Full Array  
-G/F  
235  
210  
195  
uA  
6
1/2 of Full Array  
290  
1/4 of Full Array  
270  
1. Measured with outputs open.  
2. Refresh period is 64ms.  
3. Internal TCSR can be supported.  
In commercial Temp : Max 40°C/Max 70°C, In extended Temp : Max 40°C/Max 85°C  
4. K4S643233H-F(H)E/C**  
5. K4S643233H-F(H)N/L**  
6. K4S643233H-F(H)G/F**  
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).  
February 2004  
K4S643233H - F(H)E/N/G/C/L/F  
Mobile-SDRAM  
AC OPERATING TEST CONDITIONS(VDD = 2.7V ∼ 3.6V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)  
Parameter  
AC input levels (Vih/Vil)  
Value  
2.4 / 0.4  
1.4  
Unit  
V
Input timing measurement reference level  
Input rise and fall time  
V
tr/tf = 1/1  
1.4  
ns  
V
Output timing measurement reference level  
Output load condition  
See Figure 2  
VDDQ  
1200Ω  
Vtt=0.5 x VDDQ  
VOH (DC) = 2.4V, IOH = -2mA  
VOL (DC) = 0.4V, IOL = 2mA  
30pF  
Output  
50Ω  
870Ω  
Output  
Z0=50Ω  
30pF  
Figure 1. DC Output Load Circuit  
Figure 2. AC Output Load Circuit  
February 2004  
K4S643233H - F(H)E/N/G/C/L/F  
Mobile-SDRAM  
OPERATING AC PARAMETER  
(AC operating conditions unless otherwise noted)  
Version  
Parameter  
Symbol  
Unit  
Note  
-60  
12  
18  
18  
42  
-75  
15  
19  
19  
45  
-1H  
19  
19  
19  
50  
-1L  
19  
24  
24  
60  
Row active to row active delay  
RAS to CAS delay  
tRRD(min)  
tRCD(min)  
tRP(min)  
ns  
ns  
1
1
1
1
Row precharge time  
ns  
tRAS(min)  
tRAS(max)  
tRC(min)  
ns  
Row active time  
100  
2
us  
Row cycle time  
60  
64  
69  
84  
ns  
1
2
3
2
2
4
Last data in to row precharge  
Last data in to Active delay  
Last data in to new col. address delay  
Last data in to burst stop  
tRDL(min)  
tDAL(min)  
tCDL(min)  
tBDL(min)  
tCCD(min)  
CLK  
-
tRDL + tRP  
1
1
1
2
CLK  
CLK  
CLK  
Col. address to col. address delay  
Number of valid output data  
Number of valid output data  
Number of valid output data  
CAS latency=3  
CAS latency=2  
CAS latency=1  
ea  
5
-
1
-
0
NOTES:  
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next  
higher integer.  
2. Minimum delay is required to complete write.  
3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).  
4. All parts allow every cycle column address change.  
5. In case of row precharge interrupt, auto precharge and read burst stop.  
February 2004  
K4S643233H - F(H)E/N/G/C/L/F  
Mobile-SDRAM  
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)  
- 60  
Max  
- 75  
Max  
-1H  
Max  
-1L  
Parameter  
Symbol  
Unit Note  
Min  
Min  
7.5  
9.5  
-
Min  
9.5  
9.5  
-
Min  
9.5  
12  
Max  
CAS latency=3  
CAS latency=2  
CAS latency=1  
CAS latency=3  
CAS latency=2  
CAS latency=1  
CAS latency=3  
CAS latency=2  
CAS latency=1  
tCC  
tCC  
tCC  
tSAC  
tSAC  
tSAC  
tOH  
tOH  
tOH  
tCH  
tCL  
6.0  
CLK cycle time  
1000  
1000  
1000  
1000  
ns  
ns  
ns  
1
1,2  
2
-
-
25  
5.4  
6
7
-
7
7
-
7
8
CLK to valid output delay  
Output data hold time  
-
-
20  
2.5  
-
2.5  
2.5  
-
2.5  
2.5  
-
2.5  
2.5  
2.5  
3
-
CLK high pulse width  
CLK low pulse width  
Input setup time  
2.5  
2.5  
2.0  
1.0  
1
2.5  
2.5  
2.0  
1.0  
1
3
ns  
ns  
ns  
ns  
ns  
3
3
3
3
2
3
3
tSS  
2.5  
1.5  
1
2.5  
1.5  
1
Input hold time  
tSH  
CLK to output in Low-Z  
tSLZ  
CAS latency=3  
CAS latency=2  
CAS latency=1  
5.4  
6
7
-
7
7
-
7
8
CLK to output in Hi-Z  
tSHZ  
ns  
-
-
20  
NOTES :  
1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.  
3. Assumed input rise and fall time (tr & tf) = 1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered,  
i.e., [(tr + tf)/2-1]ns should be added to the parameter.  
February 2004  
K4S643233H - F(H)E/N/G/C/L/F  
Mobile-SDRAM  
SIMPLIFIED TRUTH TABLE  
BA  
0,1  
COMMAND  
CKEn-1 CKEn CS RAS CAS WE DQM  
A10/AP A9 ~ A0 Note  
Register  
Refresh  
Mode Register Set  
Auto Refresh  
H
H
X
H
L
L
L
L
L
L
L
L
X
X
OP CODE  
X
1, 2  
3
H
Entry  
3
Self  
L
H
L
H
X
L
H
X
H
H
X
H
3
Refresh  
Exit  
L
H
H
H
X
X
X
X
X
X
3
Bank Active & Row Addr.  
V
V
Row Address  
Read &  
Column Address  
Auto Precharge Disable  
Auto Precharge Enable  
L
Column  
4
L
H
L
H
Address  
(A0~A7)  
H
4, 5  
Write &  
Column Address  
Auto Precharge Disable  
Auto Precharge Enable  
L
Column  
Address  
(A0~A7)  
4
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
H
4, 5  
Burst Stop  
Precharge  
X
6
Bank Selection  
All Banks  
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry  
H
L
L
H
L
X
X
X
Clock Suspend or  
Active Power Down  
X
X
Exit  
X
H
L
Entry  
H
Precharge Power Down  
Mode  
H
L
Exit  
L
H
H
H
X
X
V
X
DQM  
X
X
7
H
L
X
H
X
H
No Operation Command  
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)  
NOTES :  
1. OP Code : Operand Code  
A0 ~ A10 & BA0 ~ BA1 : Program keys. (@MRS)  
2. MRS can be issued only at all banks precharge state.  
A new command can be issued after 2 CLK cycles of MRS.  
3. Auto refresh functions are the same as CBR refresh of DRAM.  
The automatical precharge without row precharge command is meant by "Auto".  
Auto/self refresh can be issued only at all banks precharge state.  
Partial self refresh can be issued only after setting partial self refresh mode of EMRS.  
4. BA0 ~ BA1 : Bank select addresses.  
5. During burst read or write with auto precharge, new read/write command can not be issued.  
Another bank read/write command can be issued after the end of burst.  
New row active of the associated bank can be issued at tRP after the end of burst.  
6. Burst stop command is valid at every burst length.  
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation,  
it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).  
February 2004  
K4S643233H - F(H)E/N/G/C/L/F  
Mobile-SDRAM  
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES  
Register Programmed with Normal MRS  
A9*2  
BA0 ~ BA1  
Address  
A10/AP  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
"0" Setting for  
Normal MRS  
RFU*1  
Function  
W.B.L  
Test Mode  
CAS Latency  
BT  
Burst Length  
Normal MRS Mode  
Test Mode  
CAS Latency  
Burst Type  
Type  
Burst Length  
A8 A7  
Type  
Mode Register Set  
Reserved  
A6 A5 A4  
Latency  
Reserved  
1
A3  
0
A2  
A1  
0
A0  
0
BT=0  
BT=1  
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sequential  
Interleave  
0
0
0
0
1
1
1
1
1
2
4
8
1
2
4
8
1
0
1
Reserved  
2
Mode Select  
1
0
Reserved  
3
BA1 BA0  
Mode  
1
1
Write Burst Length  
Length  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
Reserved Reserved  
Reserved Reserved  
Reserved Reserved  
Full Page Reserved  
Setting  
for Nor-  
mal MRS  
A9  
0
0
1
0
0
Burst  
1
0
1
Single Bit  
1
1
Full Page Length x32 : 64Mb(256)  
Register Programmed with Extended MRS  
Address  
BA1  
BA0  
A10/AP  
A9  
RFU*1  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
RFU*1  
Function  
Mode Select  
DS  
PASR  
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)  
Mode Select  
Mode  
Driver Strength  
PASR  
A0 Size of Refreshed Array  
BA1  
BA0  
A6  
0
A5  
0
Driver Strength  
A2  
0
A1  
0
0
0
1
1
0
1
0
1
Normal MRS  
Reserved  
Full  
1/2  
0
1
0
1
0
1
0
1
Full Array  
1/2 of Full Array  
1/4 of Full Array  
Reserved  
0
1
0
0
EMRS for Mobile SDRAM  
Reserved  
1
0
Reserved  
Reserved  
0
1
1
1
0
1
Reserved Address  
1
0
Reserved  
A10/AP  
A9  
0
A8  
0
A7  
0
A4  
0
A3  
0
1
0
Reserved  
1
1
Reserved  
0
1
1
Reserved  
NOTES:  
1. RFU(Reserved for future use) should stay "0" during MRS cycle.  
2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.  
February 2004  
K4S643233H - F(H)E/N/G/C/L/F  
Mobile-SDRAM  
Partial Array Self Refresh  
1. In order to save power consumption, Mobile SDRAM has PASR option.  
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array and 1/4 of Full Array.  
BA1=0  
BA0=0  
BA1=0  
BA0=1  
BA1=0  
BA0=0  
BA1=0  
BA0=1  
BA1=0  
BA0=0  
BA1=0  
BA0=1  
BA1=1  
BA0=0  
BA1=1  
BA0=1  
BA1=1  
BA0=0  
BA1=1  
BA0=1  
BA1=1  
BA0=0  
BA1=1  
BA0=1  
- 1/4 Array  
- Full Array  
- 1/2 Array  
Partial Self Refresh Area  
Temperature Compensated Self Refresh  
1. In order to save power consumption, Mobile-DRAM includes the internal temperature sensor and control units to control the self  
refresh cycle automatically according to the two temperature range : Max 40 °C and Max 85 °C(for Extended), Max 70 °C(for  
Commercial).  
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.  
Self Refresh Current (Icc6)  
Temperature Range  
- G/F  
1/2 of Full Array  
290  
Unit  
- E/C  
- N/L  
Full Array  
350  
1/4 of Full Array  
Max 85/70 °C  
Max 40 °C  
270  
195  
1500  
350  
uA  
235  
210  
B. POWER UP SEQUENCE  
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.  
- Apply VDD before or at the same time as VDDQ.  
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.  
3. Issue precharge commands for all banks of the devices.  
4. Issue 2 or more auto-refresh commands.  
5. Issue a mode register set command to initialize the mode register.  
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.  
EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.  
The default state without EMRS command issued is the full driver strength and full array refreshed.  
The device is now ready for the operation selected by EMRS.  
For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.  
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not  
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.  
February 2004  
K4S643233H - F(H)E/N/G/C/L/F  
Mobile-SDRAM  
C. BURST SEQUENCE  
1. BURST LENGTH = 4  
Initial Address  
Sequential  
Interleave  
A1  
A0  
0
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
2. BURST LENGTH = 8  
Initial Address  
Sequential  
Interleave  
A2  
0
A1  
0
A0  
0
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
0
0
1
6
7
0
1
2
3
4
0
3
2
5
4
7
6
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
February 2004  

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