K4T51163QB-GCD5 [SAMSUNG]
512Mb B-die DDR2 SDRAM; 512MB B-死DDR2 SDRAM
| 型号： | K4T51163QB-GCD5 |
| 厂家： | 
SAMSUNG |
| 描述： | 512Mb B-die DDR2 SDRAM |
| 文件： | 总28页 (文件大小：591K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
512Mb B-die DDR2 SDRAM Specification
Version 1.5
July 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Page 1 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Contents
0. Ordering Information
1. Key Feature
2. Package Pinout/Mechanical Dimension & Addressing
2.1 Package Pinout & Mechanical Dimension
2.2 Input/Output Function Description
2.3 Addressing
3. Absolute Maximum Rating
4. AC & DC Operating Conditions & Specifications
Page 2 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
0. Ordering Information
Organization
DDR2-533 4-4-4
K4T51043QB-GCD5
K4T51043QB-ZCD5
K4T51083QB-GCD5
K4T51083QB-ZCD5
K4T51163QB-GCD5
K4T51163QB-ZCD5
DDR2-400 3-3-3
K4T51043QB-GCCC
K4T51043QB-ZCCC
K4T51083QB-GCCC
K4T51083QB-ZCCC
K4T51163QB-GCCC
K4T51163QB-ZCCC
Package
60 FBGA
60 FBGA
60 FBGA
60 FBGA
84 FBGA
84 FBGA
128Mx4
64Mx8
32Mx16
Note : Speed bin is in order of CL-tRCD-tRP.
1.Key Features
Speed
CAS Latency
tRCD(min)
DDR2-533 4-4-4
DDR2-400 3-3-3
Units
tCK
ns
4
3
15
15
55
15
15
55
tRP(min)
ns
tRC(min)
ns
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4
banks, 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks
device. This synchronous device achieves high speed double-
data-rate transfer rates of up to 533Mb/sec/pin (DDR2-533) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency -1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 512Mb(x4) device receive
14/11/2 addressing.
• 200 MHz f for 400Mb/sec/pin, 267MHz f for 533Mb/sec/
CK
CK
pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
The 512Mb DDR2 device operates with a single 1.8V ± 0.1V
power supply and 1.8V ± 0.1V VDDQ.
The 512Mb DDR2 device is available in 60ball FBGAs(x4/x8) and
in 84ball FBGAs(x16).
-High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than T
85°C,
CASE
3.9us at 85°C < T
< 95 °C
Note: The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of oper-
ation.
CASE
• Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA -
32Mx16
• All of Lead-free products are compliant for RoHS
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2
SDRAM Device Operation & Timing Diagram”
Page 3 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
2. Package Pinout/Mechanical Dimension & Addressing
2.1 Package Pinout
x4 package pinout (Top View) : 60ball FBGA Package
1
2
3
7
8
9
VDDQ
VDD
NC
NC
VSS
DM
DQS
VSSQ
DQ0
A
VSSQ
DQS
VSSQ
NC
B
C
VDDQ
DQ3
VDDQ
DQ2
VDDQ
VDDQ
NC
DQ1
VSSQ
VSSQ
CK
NC
D
E
F
VDDL
VREF
VSSDL
VSS
VDD
ODT
CK
CKE
BA0
WE
RAS
CAS
NC
BA1
CS
G
H
J
A10
A3
A1
A5
A2
A6
A0
VDD
VSS
VSS
A4
A7
A9
K
A11
NC
A8
VDD
A12
NC
A13
L
Notes:
1. Pin B3 has identical capacitance as pin B7.
2. VDDL and VSSDL are power and ground for the DLL.
Ball Locations (x4)
: Populated Ball
: Depopulated Ball
+
Top View (See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+
+
G
H
J
+
+
+
K
L
+
+
Page 4 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
x8 package pinout (Top View) : 60ball FBGA Package
1
2
3
7
8
9
NU/
VSSQ
VDD
DQ6
VSS
DQS
VSSQ
DQ0
VSSQ
CK
VDDQ
A
RDQS
DM/
VSSQ
DQ1
DQS
VDDQ
DQ2
DQ7
B
C
RDQS
VDDQ
DQ4
VDDQ
DQ3
VDDQ
VSSQ
VREF
CKE
DQ5
D
E
F
VDDL
VSS
WE
VSSDL
RAS
VDD
ODT
CK
NC
BA0
A10
A3
BA1
A1
CAS
A2
CS
A0
A4
A8
G
H
J
VDD
VSS
VSS
A5
A6
A7
A9
K
A11
VDD
A12
NC
NC
A13
L
Notes:
1. Pins B3 and A2 have identical capacitance as pins B7 and A8.
2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS
& DQS and input masking function is disabled.
3. The function of DM or RDQS/RDQS are enabled by EMRS command.
4. VDDL and VSSDL are power and ground for the DLL.
Ball Locations (x8)
: Populated Ball
: Depopulated Ball
+
Top View (See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+
+
+
G
H
J
+
+
+
K
L
Page 5 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
x16 package pinout (Top View) : 84ball FBGA Package
1
2
3
7
8
9
A
VSSQ
UDQS
VDDQ
UDQ2
VSSQ
UDQS
VSSQ
VDDQ
VDD
NC
VSS
UDM
UDQ6
VSSQ
B
C
UDQ7
VDDQ
VDDQ
UDQ3
VSS
VDDQ
UDQ4
VDD
UDQ1
UDQ0
D
E
F
VSSQ
LDQS
VSSQ
UDQ5
VDDQ
VSSQ
NC
LDQ6
VSSQ
LDQ1
LDM
LDQS
VDDQ
LDQ2
LDQ7
VDDQ
LDQ4
VDDQ
LDQ3
LDQ0
VSSQ
CK
VDDQ
G
H
J
VSSQ
VREF
CKE
LDQ5
VDDL
VSS
WE
VSSDL
RAS
VDD
ODT
K
CK
NC
L
BA0
A10
A3
BA1
A1
CAS
A2
CS
A0
A4
A8
M
N
P
VDD
VSS
VSS
A5
A6
A7
A9
A11
R
VDD
A12
NC
NC
NC
Note :
1. VDDL and VSSDL are power and ground for the DLL.
2. In case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used.
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
Ball Locations (x16)
: Populated Ball
: Depopulated Ball
+
G
H
J
Top View
(See the balls through the Package)
K
L
+
+
+
+
+
+
M
N
P
R
Page 6 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
FBGA Package Dimension(x4/x8)
11.00 ± 0.10
# A1 INDEX MARK
6.40
0.80
1.60
4
9
8
7
6
5
3
2
1
A
B
C
D
E
F
G
H
J
K
L
3.20
(5.50)
(0.90)
(1.80)
60-∅0.45±0.05
∅0.2 M
A B
11.00 ± 0.10
#A1
0.35±0.05
MAX.1.20
Page 7 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
FBGA Package Dimension(x16)
11.00 ± 0.10
# A1 INDEX MARK
6.40
0.80
1.60
4
9
8
7
6
5
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
3.20
(5.50)
(0.90)
(1.80)
84-∅0.45±0.05
∅0.2 M
A B
11.00 ± 0.10
#A1
0.35±0.05
MAX.1.20
Page 8 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
2.2 Input/Output Functional Description
Symbol
Type
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of
the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
(both directions of crossing).
CK, CK
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and
output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or
Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self
refresh entry. CKE is asynchronous for self refresh exit. After V
has become stable during the power on and ini-
REF
CKE
CS
Input
Input
tialization swquence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry
and exit, V
must be maintained to this input. CKE must be maintained high throughout read and write accesses.
REF
Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on
systems with multiple Ranks. CS is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When
enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For
x16 configuration, ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin
will be ignored if the Extended Mode Register Set(EMRS) is programmed to disable ODT.
ODT
RAS, CAS, WE
DM
Input
Input
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coin-
cident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is
enabled by EMRS command.
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines if the mode register or extended mode register is to be accessed during a
MRS or EMRS cycle.
BA0 - BA1
Input
Input
Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit
for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled
during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also pro-
vide the op-code during Mode Register Set commands.
A0 - A13
DQ
Input/Output Data Input/ Output: Bi-directional data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For
the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an
RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS,
UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS,
UDQS, and RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1)
control bit enables or disables all complementary data strobe signals.
DQS, (DQS)
(LDQS), (LDQS)
(UDQS), (UDQS)
(RDQS), (RDQS)
Input/Output
NC
No Connect: No internal electrical connection is present.
Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V
Ground, DQ Ground
V
/V
Supply
Supply
Supply
Supply
Supply
DD DDQ
V
/V
SS SSQ
V
DLL Power Supply: 1.8V +/- 0.1V
DLL Ground
Reference voltage
DDL
V
SSDL
V
REF
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)
x4 DQS/DQS
x8 DQS/DQS
if EMRS(1)[A11] = 0
if EMRS(1)[A11] = 1
x8 DQS/DQS, RDQS/RDQS,
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)
x4 DQS
x8 DQS
if EMRS(1) [A11] = 0
x8 DQS, RDQS, if EMRS(1) [A11] = 1
x16 LDQS and UDQS
Page 9 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
2.3 512Mb Addressing
Configuration
128Mb x4
64Mb x 8
32Mb x16
# of Bank
4
4
4
Bank Address
Auto precharge
Row Address
BA0,BA1
A10/AP
A0 ~ A13
A0 ~ A9,A11
BA0,BA1
A10/AP
A0 ~ A13
A0 ~ A9
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9
Column Address
* Reference information: The following tables are address mapping information for other densities.
256Mb
Configuration
64Mb x4
32Mb x 8
16Mb x16
# of Bank
4
4
4
Bank Address
Auto precharge
Row Address
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9,A11
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A8
Column Address
1Gb
Configuration
256Mb x4
128Mb x 8
64Mb x16
# of Bank
8
8
8
Bank Address
Auto precharge
Row Address
Column Address
BA0 ~ BA2
A10/AP
A0 ~ A13
A0 ~ A9,A11
BA0 ~ BA2
A10/AP
A0 ~ A13
A0 ~ A9
BA0 ~ BA2
A10/AP
A0 ~ A12
A0 ~ A9
2Gb
Configuration
512Mb x4
256Mb x 8
128Mb x16
# of Bank
8
8
8
Bank Address
Auto precharge
Row Address
Column Address
BA0 ~ BA2
A10/AP
A0 ~ A14
A0 ~ A9,A11
BA0 ~ BA2
A10/AP
A0 ~ A14
A0 ~ A9
BA0 ~ BA2
A10/AP
A0 ~ A13
A0 ~ A9
4Gb
Configuration
1 Gb x4
512Mb x 8
256Mb x16
# of Bank
8
8
8
Bank Address
Auto precharge
Row Address
BA0 ~ BA2
A10/AP
A0 - A15
BA0 ~ BA2
A10/AP
A0 - A15
A0 - A9
BA0 ~ BA2
A10/AP
A0 - A14
A0 - A9
Column Address/page size
A0 - A9,A11
Page 10 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
3. Absolute Maximum DC Ratings
Symbol
VDD
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Rating
- 1.0 V ~ 2.3 V
Units
V
Notes
1
VDDQ
VDDL
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
V
V
1
1
VIN VOUT
,
V
1
TSTG
°C
1, 2
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
4. AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
Typ.
Max.
VDD
VDDL
VDDQ
VREF
VTT
1.7
1.8
1.9
V
V
Supply Voltage
1.7
1.8
1.8
1.9
4
4
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1,2
3
Note :
There is no specific device V supply voltage requirement for SSTL-1.8 compliance. However under all conditions V
must be less than or equal to
DDQ
DD
V
.
DD
1. The value of V
may be selected by the user to provide optimum noise margin in the system. Typically the value of V
is expected to be about 0.5
REF
REF
x V
of the transmitting device and V
is expected to track variations in V
.
DDQ
REF
DDQ
2. Peak to peak AC noise on V
may not exceed +/-2% V
(DC).
REF
REF
3. V of transmitting device must track V
of receiving device.
TT
REF
4. AC parameters are measured with V , V
and V
tied together
DD
DDQ
DDL
Page 11 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°C
1, 2
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51.2 standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to
self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol
Parameter
Min.
+ 0.125
Max.
V + 0.3
DDQ
Units
V
Notes
Notes
V
(DC)
V
DC input logic high
DC input logic low
IH
REF
V (DC)
- 0.3
V
- 0.125
REF
V
IL
Input AC Logic Level
Symbol
Parameter
Min.
Max.
Units
VIH(AC)
V
+ 0.250
-
V
AC input logic high
AC input logic low
REF
VIL(AC)
-
V
- 0.250
V
REF
AC Input Test Conditions
Symbol
Condition
Value
0.5 * V
Units
Notes
V
Input reference voltage
V
1
REF
DDQ
V
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
1.0
V
1
SWING(MAX)
SLEW
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V
2. The input signal minimum slew rate is to be maintained over the range from V
(AC) level applied to the device under test.
IH/IL
REF
to V (AC) min for rising edges and the range from V
to
IH
REF
V (AC) max for falling edges as shown in the below figure.
IL
3. AC timings are referenced with input waveforms switching from V (AC) to V (AC) on the positive transitions and V (AC) to V (AC) on the
IL
IH
IH
IL
negative transitions.
V
V
V
V
V
V
V
DDQ
(AC) min
IH
IH
(DC) min
V
SWING(MAX)
REF
(DC) max
IL
IL
(AC) max
SS
delta TF
V
delta TR
- V (AC) max
IL
V
(AC) min - V
delta TR
REF
IH
REF
Falling Slew =
Rising Slew =
delta TF
< AC Input Test Signal Waveform >
Page 12 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Differential input AC logic Level
Symbol
Parameter
Min.
Max.
Units
Notes
VID(AC)
0.5
VDDQ + 0.6
V
1
AC differential input voltage
AC differential cross point voltage
VIX(AC)
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS)
and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH (AC) - V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ .
VIX(AC) indicates the voltage at which differential input signals must cross.
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Differential AC output parameters
Symbol
Parameter
Min.
0.5 * VDDQ - 0.125
Max.
0.5 * VDDQ + 0.125
Units
V
Note
1
VOX(AC)
AC differential cross point voltage
Note :
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ .
VOX(AC) indicates the voltage at which differential output signals must cross.
Page 13 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
OCD default characteristics
Description
Output impedance
Output impedance step size for OCD calibration
Pull-up and pull-down mismatch
Output slew rate
Parameter
Min
12.6
0
0
1.5
Nom
18
Max
23.4
1.5
4
Unit
ohms
ohms
ohms
V/ns
Notes
1,2
6
1,2,3
1,4,5,6,7,8
Sout
5
Notes:
1. Absolute Specifications (0°C ≤ TCASE ≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for
values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV;
VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from V (AC) to V (AC).
IL
IH
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaran-
teed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty.
Output slew rate load :
VTT
25 ohms
Output
Reference
Point
(VOUT)
7. DRAM output slew rate specification applies to 400Mb/sec/pin and 533Mb/sec/pin speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.
Page 14 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
IDD Specification Parameters and Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)
Symbol
IDD0
Proposed Conditions
Operating one bank active-precharge current;
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Units
Notes
t
t
t
t
t
t
mA
Operating one bank active-read-precharge current;
t
t
t
t
t
t
t
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =
IDD1
mA
t
RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pattern
is same as IDD4W
Precharge power-down current;
All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
t
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
t
mA
mA
mA
Precharge quiet standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
mA
mA
Fast PDN Exit MRS(12) = 0mA
t
t
All banks open; CK = CK(IDD); CKE is LOW; Other control and address bus
Slow PDN Exit MRS(12) = 1mA
inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
t
t
t
t
t
t
mA
mA
All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
t
t
t
t
t
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP
IDD4W
IDD4R
t
= RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current;
t
t
t
t
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-
mA
mA
t
t
max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
Burst auto refresh current;
t
t
t
IDD5B
IDD6
CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid com-
mands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
Normal
mA
mA
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Low Power
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC
t
t
t
t
t
IDD7
t
t
t
t
t
t
t
mA
= RC(IDD), RRD = RRD(IDD), FAW = FAW(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-
lowing page for detailed timing conditions
Notes :
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS
bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control
signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including
masks or strobes.
Page 15 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
For purposes of IDD testing, the following parameters are utilized
DDR2-533
DDR2-400
Units
Parameter
4-4-4
3-3-3
CL(IDD)
4
3
tCK
t
15
60
15
55
7.5
10
5
RCD(IDD)
ns
ns
t
RC(IDD)
t
ns
ns
RRD(IDD)-x4/x8
7.5
t
RRD(IDD)-x16
10
t
3.75
CK(IDD)
ns
ns
t
45
15
40
15
105
RASmin(IDD)
t
ns
ns
RP(IDD)
t
105
RFC(IDD)
Detailed IDD7
The detailed timings are shown below for IDD7.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) and FAW(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
t
t
t
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 3/3/3
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
-DDR2-533 4/4/4
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D
Page 16 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
DDR2 SDRAM IDD Spec Table
128Mx4(K4T51043QB)
D5(DDR2-533@CL=4) CC(DDR2-400@CL=3)
100
Symbol
Unit
Notes
Notes
Notes
IDD0
IDD1
95
100
8
25
30
30
15
65
130
140
185
5.5
265
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
110
8
25
30
30
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
15
70
175
170
195
5.5
270
IDD6
IDD6
IDD6
Normal
IDD7
64Mx8(K4T51083QB)
Symbol
Unit
D5(DDR2-533@CL=4)
CC(DDR2-400@CL=3)
IDD0
IDD1
100
110
8
25
30
30
15
70
200
180
195
5.5
275
95
100
8
25
30
30
15
65
145
145
185
5.5
270
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
Normal
IDD7
32Mx16(K4T51163QB)
Symbol
Unit
D5(DDR2-533@CL=4)
CC(DDR2-400@CL=3)
IDD0
IDD1
120
145
8
25
30
30
15
70
230
205
195
5.5
390
115
125
8
25
30
30
15
65
185
170
185
5.5
375
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
Normal
IDD7
Page 17 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Input/Output capacitance
Parameter
DDR2-400 / DDR2-533
Min Max
Symbol
Units
Input capacitance, CK and CK
CCK
CDCK
CI
1.0
x
2.0
0.25
2.0
pF
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
Input/output capacitance delta, DQ, DM, DQS, DQS
1.0
x
CDI
0.25
4.0
CIO
2.5
x
CDIO
0.5
Electrical Characteristics & AC Timing for DDR2-533/400
(0 °C < T
< 95 °C; V
= 1.8V + 0.1V; V = 1.8V + 0.1V)
DDQ DD
CASE
Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
105
1Gb
2Gb
195
7.8
4Gb
327.5
7.8
Units
Refresh to active/Refresh command time
tRFC
tREFI
75
127.5
7.8
ns
0 °C ≤ T
≤ 85°C
≤ 95°C
7.8
7.8
µs
µs
CASE
Average periodic refresh interval
85 °C < T
3.9
3.9
3.9
3.9
3.9
CASE
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
DDR2-533(D5)
DDR2-400(CC)
3 - 3 - 3
Units
Bin (CL - tRCD - tRP)
4 - 4 - 4
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
min
5
max
min
5
max
8
8
-
8
8
-
ns
ns
ns
ns
ns
ns
ns
3.75
-
5
-
15
15
55
40
15
15
55
40
tRP
tRC
70000
70000
tRAS
Page 18 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
DDR2-533
DDR2-400
Symbol
Units
Notes
Parameter
min
max
min
max
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-500
+500
-600
+600
ps
ps
tDQSCK
tCH
-450
+450
-500
+500
0.45
0.55
0.45
0.55
tCK
tCK
ps
CK low-level width
tCL
0.45
0.55
0.45
0.55
CK half period
tHP
min(tCL, tCH)
x
min(tCL, tCH)
x
20,21
24
Clock cycle time, CL=x
tCK
3750
8000
5000
8000
ps
DQ and DM input hold time
tDH(base)
tDS(base)
tIPW
225
x
275
x
ps
15,16,17,20
15,16,17,21
DQ and DM input setup time
100
x
150
x
ps
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
0.6
x
0.6
x
tCK
tCK
ps
tDIPW
tHZ
0.35
x
0.35
x
x
tAC max
x
tAC max
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
tAC max
tAC min
tAC max
ps
27
27
22
21
2* tACmin
tAC max
2* tACmin
tAC max
ps
x
x
300
400
x
x
x
350
450
x
ps
ps
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock edge
DQS input high pulse width
tQH
tHP - tQHS
-0.25
0.35
0.35
0.2
tHP - tQHS
-0.25
0.35
0.35
0.2
ps
tDQSS
tDQSH
tDQSL
tDSS
0.25
x
0.25
x
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
DQS input low pulse width
x
x
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
x
x
tDSH
0.2
x
0.2
x
tMRD
2
x
2
x
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
tRRD
0.4
0.6
x
0.4
0.6
x
19
Write preamble
0.35
375
250
0.9
0.35
475
350
0.9
Address and control input hold time
Address and control input setup time
Read preamble
x
x
14,16,18,23
x
x
ps
14,16,18,22
1.1
0.6
x
1.1
0.6
x
tCK
tCK
ns
28
28
12
12
Read postamble
0.4
0.4
Active to active command period for 1KB page size products
Active to active command period for 2KB page size products
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
7.5
7.5
tRRD
tFAW
10
x
10
x
ns
37.5
50
37.5
50
ns
tFAW
ns
tCCD
tWR
2
2
tCK
ns
Write recovery time
15
x
x
x
15
x
x
x
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read command
Exit active power down to read command
tDAL
WR+tRP
7.5
WR+tRP
10
tCK
ns
23
33
11
tWTR
tRTP
tXSNR
tXSRD
tXP
7.5
7.5
ns
tRFC + 10
200
2
tRFC + 10
200
2
ns
tCK
tCK
tCK
x
x
x
x
tXARD
2
2
9
Exit active power down to read command
(slow exit, lower power)
tXARDS
6 - AL
6 - AL
tCK
9, 10
Page 19 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
DDR2-533
DDR2-400
Symbol
Units
Notes
Parameter
min
max
min
max
t
CKE minimum pulse width (high and low pulse width)
tCK
tCK
ns
36
3
3
CKE
t
t
ODT turn-on delay
ODT turn-on
2
2
2
2
AOND
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
13, 25
26
AON
2tCK+tAC
(max)+1
2tCK+tAC
(max)+1
t
ODT turn-on(Power-Down mode)
tAC(min)+2
tAC(min)+2
ns
AONPD
t
t
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
2.5
tCK
ns
AOFD
AOF
tAC(min)
tAC(max)+ 0.6
tAC(max)+ 0.6
tAC(min)
2.5tCK+
2.5tCK+
t
ODT turn-off (Power-Down mode)
tAC(min)+2
tAC(min)+2
ns
AOFPD
tAC(max)+1
tAC(max)+1
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after CKE asynchronously
drops LOW
tDelay
tIS+tCK +tIH
tIS+tCK +tIH
ns
24
Page 20 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for
single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS =
+500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for rising edges and from VIH(dc) and VIL(ac)
for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV (250mV to -500 mV for
falling edges).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential
strobe.
2. DDR2 SDRAM AC timing reference load
Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise
representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (gen-
erally a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ
DQS
Output
DQS
RDQS
RDQS
DUT
V
= V
/2
DDQ
TT
Timing
reference
point
25Ω
<AC Timing Reference Load>
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig-
nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in the following figure.
VDDQ
DUT
DQ
Output
Test point
DQS, DQS
RDQS, RDQS
V
= V
/2
DDQ
TT
25Ω
<Slew Rate Test Load>
Page 21 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode
bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by
design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally
to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
t
t
DQSL
DQSH
DQS
DQS
DQS/
DQS
t
t
WPST
WPRE
V
IH(dc)
V
IH(ac)
DQ
DM
D
D
D
D
t
V
IL(ac)
VIL(dc)
t
t
DH
DH
DS
t
DS
V
IH(ac)
VIH(dc)
DMin
DMin
DMin
DMin
V
IL(ac)
V
IL(dc)
<Data input (write) timing>
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
t
QH
QH
<Data output (read) timing>
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
tester correlation.
may be guaranteed by device design or
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
Page 22 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Specific Notes for dedicated AC parameters
9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing.
tXARDS is expected to be used for slow active power down exit timing.
10. AL = Additive Latency
11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied.
12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency
13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns.
14. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.
15. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns.
16. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns
in differential strobe mode and a slew rate of 1V/ns in single ended mode.
17. tDS and tDH derating Values
∆tDS, ∆tDH Derating Values of DDR2-400, DDR2-533 (ALL units in ‘ps’, Note 1 applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
125
45
21
0
-
125
45
125
83
0
45
21
0
-
95
12
1
-
33
12
-2
-19
-42
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
83
0
-
83
0
21
0
-
-
-
-
-
-
-
-
24
13
-1
-19
-43
-
24
10
-7
-30
-59
-
DQ
Siew
rate
-11
-14
-11
-25
-
-14
-31
-
25
11
-7
-31
-74
-
22
5
-18
-47
-89
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-13
-31
-
23
5
17
-6
-35
-77
-
-
6
-
-
-
-
17
-7
-50
V/ns
-
-
-
-
-19
-62
-23
-65
5
-11
-53
-
-
-
-
-
-
-
-
-
-
-
-
-38
-
-
-127 -140 -115 -128 -103 -116
∆tDS, ∆tDH Derating Values for DDR2-667, DDR2-800 (ALL units in ‘ps’, Note 1 applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
100
45
21
0
-
100
45
21
100
67
0
45
21
0
-
79
12
7
-1
-10
-
-
33
12
-2
-19
-42
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
67
0
-
67
0
-5
-
0
24
19
11
2
24
10
-7
-30
-59
-
-
-
-
-
-
-
-
-
-
DQ
Slew
rate
-14
-5
-13
-
-14
-31
-
31
23
14
2
-24
-
22
5
-
-
17
-6
-
-
-
-
-
-
-
-
-
-
-
-
-
35
26
14
-12
-52
-
-
-
-18
-47
-89
-
38
26
0
6
-
-
V/ns
-
-
-
-
-
-
-
-
-
-
-10
-
-35
-77
-140
-23
-65
-128
38
12
-28
-11
-53
-116
-
-
-
-
-
-
-
-
-
-
-
-40
For all input signals the total tDS (setup time) and tDH(hold time) required is calculated by adding the datasheet tDS(base) and tDH(base) value to the
delta tDS and delta tDH derating value respectively. Example: tDS(total setup time)= tDS(base) + delta tDS.
Page 23 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
18. tIS and tIH (input setup and hold) derating.
∆tIS, ∆tIH Derating Values for DDR2-400, DDR2-533
CK, CK Differential Slew Rate
1.5 V/ns 1.0 V/ns
2.0 V/ns
Units
Notes
∆tIS
+187
+179
+167
+150
+125
+83
0
∆tIH
+94
+89
+83
+75
+45
+21
0
∆tIS
+217
+209
+197
+180
+155
+113
+30
∆tIH
+124
+119
+113
+105
+75
+51
+30
+16
-1
∆tIS
+247
+239
+227
+210
+185
+143
+60
∆tIH
+154
+149
+143
+135
+105
+81
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+60
-11
-14
+19
+49
+46
Command/
Address Slew
rate(V/ns)
-25
-31
+5
+35
+29
-43
-54
-13
-24
+17
+6
-67
-83
-37
-53
-7
-23
-110
-175
-285
-350
-525
-800
-125
-188
-292
-375
-500
-708
-80
-95
-50
-65
-145
-255
-320
-495
-770
-158
-262
-345
-470
-678
-115
-225
-290
-465
-740
-128
-232
-315
-440
-648
∆tIS and ∆tIH Derating Values for DDR2-667, DDR2-800
CK, CK Differential Slew Rate
2.0 V/ns
1.5 V/ns
1.0 V/ns
Units
Notes
∆tIS
+150
+143
+133
+120
+100
+67
0
∆tIH
+94
+89
+83
+75
+45
+21
0
∆tIS
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
∆tIH
+124
+119
+113
+105
+75
∆tIS
+210
+203
+193
+180
+160
+127
+60
∆tIH
+154
+149
+143
+135
+105
+81
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+51
+30
+60
-5
-14
+16
+55
+46
Command/
Address Slew
rate(V/ns)
-13
-31
-1
+47
+29
-22
-54
-24
+38
+6
-34
-83
-4
-53
+26
-23
-60
-125
-188
-292
-375
-500
-708
-1125
-30
-95
0
-65
-100
-168
-200
-325
-517
-1000
-70
-158
-262
-345
-470
-678
-1095
-40
-128
-232
-315
-440
-648
-1065
-138
-170
-295
-487
-970
-108
-140
-265
-457
-940
For all input signals the total tIS (setup time) and tIH(hold time) required is calculated by adding the datasheet tIS(base) and tIH(base) value to the delta
tIS and delta tIH derating value respectively. Example: tIS(total setup time)= tIS(base) + delta tIS.
Page 24 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater
than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock
source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.
21. tQH = tHP – tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately,
due to data pin skew and output pattern effects, and pchannel to n-channel variation of the output drivers.
22. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate
mismatch between DQS / DQS and associated DQ in any given cycle.
23. tDAL = WR + RU{tRP(ns)/tCK(ns)}, where RU stands for round up.
tWR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK
refers to the application clock period.
Example: For DDR533 at tCK = 3.75ns with tWR programmed to 4 clocks.
tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
24. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency change during pre-
charge power-down, a specific procedure is required as described in DDR2 device operation
25. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
26. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
27. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which
specifies when the device output is no longer driving (tHZ), or begins driving (tLZ). Following figure shows a method to calculate the point when device is
no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as
long as the calculation is consistent.
28. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST),
or begins driving (tRPRE). Following figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving
(tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.
These notes are referenced in the “Timing parameters by speed grade” tables for DDR2-400 and DDR2-533.
Page 25 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
VTT + 2x mV
VTT + x mV
VOH + x mV
VOH + 2x mV
tLZ
tRPRE begin point
tHZ
tRPST end point
VTT - x mV
VTT - 2x mV
VOL + 2x mV
VOL + x mV
T1
T2
T2
T1
tHZ,tRPST end point = 2*T1-T2
tLZ,tRPRE begin point = 2*T1-T2
<Test method for tLZ, tHZ, tRPRE and tRPST>
29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
level to the differen-
IH(ac)
tial data strobe crosspoint for a rising signal, and from the input signal crossing at the V
nal applied to the device under test.
level to the differential data strobe crosspoint for a falling sig-
IL(ac)
30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
level to the differen-
IH(dc)
tial data strobe crosspoint for a rising signal and V
to the differential data strobe crosspoint for a falling signal applied to the device under test.
IL(dc)
Differential Input waveform timing
DQS
DQS
tDH
tDH
tDS
tDS
V
V
V
V
V
V
V
DDQ
min
min
IH(ac)
IH(dc)
REF(dc)
max
max
IL(dc)
IL(ac)
SS
Page 26 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
31. Input waveform timing is referenced from the input signal crossing at the V
device under test.
level for a rising signal and V
level for a rising signal and V
for a falling signal applied to the
IH(ac)
IL(ac)
IL(dc)
32. Input waveform timing is referenced from the input signal crossing at the V
device under test.
for a falling signal applied to the
IH(dc)
CK
CK
tIH
tIH
tIS
tIS
V
V
V
V
V
V
V
DDQ
min
min
IH(ac)
IH(dc)
REF(dc)
max
max
IL(dc)
IL(ac)
SS
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the sin-
gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-
ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic
between Vil(dc)max and Vih(dc)min.
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-
ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic
between Vil(dc)max and Vih(dc)min.
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registeration. Thus, after any CKE transition, CKE may not change from its valid level during the time period of tIS
+ 2*tCK + tIH.
Page 27 of 28
Rev. 1.5 July 2005
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Revision History
Version 1.0 (Jan. 2004)
- Initial Release
Version 1.1 (Jun. 2004)
- Added Lead-Free part number in ordering information.
- Changed IDD2P
- Corrected Typo
Version 1.2 (Jan. 2005)
- Removed DDR2-667 SDRAM at this datasheet
- Revised current test AC spec condition
- Added derating table
Version 1.3 (Jan. 2005)
- Corrected typo
Version 1.4 (Feb. 2005)
- Corrected from 6.15mm to 5.5mm in dimension of x16 PKG
Version 1.5 (Jul. 2005)
- Corrected typo
Page 28 of 28
Rev. 1.5 July 2005
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