K4T51163QB-GLD50 [SAMSUNG]
DDR DRAM, 32MX16, 0.5ns, CMOS, PBGA84, FBGA-84;
| 型号： | K4T51163QB-GLD50 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 32MX16, 0.5ns, CMOS, PBGA84, FBGA-84 动态存储器 双倍数据速率 |
| 文件： | 总38页 (文件大小：600K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
512Mb B-die DDR2 SDRAM Specification
Version 0.91
September 2003
Rev. 0.91 (Sep. 2003)
Page 1 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Contents
1. Key Feature
2. Package Pinout/Mechnical Dimension & Addressing
2.1 Package Pintout & Mechnical Dimension
2.2 Input/Output Function Description
2.3 Addressing
3. Command Truth Table
3.1 Command truth table
3.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
3.3 DM Truth Table
4. Absolute Maximum Rating
5. AC & DC Operating Conditions & Specifications
Rev. 0.91 (Sep. 2003)
Page 2 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Revision History
Version 0.9 (Aug. 2003)
- Initial Release
Version 0.91 (Sep. 2003)
- Corrected from M to B in Part No Information(K4T51##3Q”M”-### -> K4T51##3Q”B”-###)
- Removed D4 speed bin(400 4-4-4)
- Added operation temperature condition
- Changed setup/hold time values(tlS/tDS, tIH/tDH)
- Added notes for setup/hold time(tIS/tDS, tIH/tDH)
- Changed in/output capacitance values
- Added tREFI values by TCASE (85°C/95°C)
Rev. 0.91 (Sep. 2003)
Page 3 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Part Number Information
Organization
DDR2-667 5-5-5
K4T51043QB-GCE6
K4T51043QB-GLE6
K4T51083QB-GCE6
K4T51083QB-GLE6
K4T51163QB-GCE6
K4T51163QB-GLE6
DDR2-533 4-4-4
K4T51043QB-GCD5
K4T51043QB-GLD5
K4T51083QB-GCD5
K4T51083QB-GLD5
K4T51163QB-GCD5
K4T51163QB-GLD5
DDR2-400 3-3-3
K4T51043QB-GCCC
K4T51043QB-GLCC
K4T51083QB-GCCC
K4T51083QB-GLCC
K4T51163QB-GCCC
K4T51163QB-GLCC
128Mx4
64Mx8
32Mx16
Note:
1. Speed bin is in order of CL-tRCD-tRP
1
2
3
4
5
6
7
8
9
10
11
K 4 T XX XX X X X - X X XX
Memory
DRAM
Speed
Temperature & Power
Small Classification
Density and Refresh
Package
Version
Organization
Bank
Interface (VDD & VDDQ)
1. SAMSUNG Memory : K
2. DRAM : 4
3. Small Classification
T : DDR2 SDRAM
8. Version
M : 1st Generation
A : 2nd Generation
B : 3rd Generation
C : 4th Generation
D : 5th Generation
E : 6th Generation
4. Density & Refresh
51 : 512M 8K/64ms
9. Package
G : BGA
10. Temperature & Power
C : (Commercial, Normal)
L : (Commercial, Low)
5. Organization
04 : x4
08 : x8
16 : x16
11. Speed
CC : DDR2-400 3-3-3
D5 : DDR2-533 4-4-4
E6 : DDR2-667 5-5-5
6. Bank
3 : 4 Bank
7. Interface (VDD & VDDQ)
Q: SSTL-18(1.8V, 1.8V)
Rev. 0.91 (Sep. 2003)
Page 4 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
1.Key Features
Speed
DDR2-667
DDR2-533
DDR2-400
Units
5 - 5- 5
4 - 4 - 4
3- 3- 3
CAS Latency
tRCD(min)
tRP(min)
5
4
3
tCK
ns
15
15
55
15
15
55
15
15
55
ns
tRC(min)
ns
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin
• 4 Bank
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refesh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
• Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA - 32Mx16
Rev. 0.91 (Sep. 2003)
Page 5 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Description
The 512Mb DDR2 SDRAM chip is organized as either 32Mbit x 4 I/O x 4 banks or 16Mbit x 8 I/O x 4banks or
8Mbit x 16I/O x 4 banks device. This synchronous device achieve high speed double-data-rate transfer rates
of up to 667Mb/sec/pin (DDR2-667) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive
latency, (2) write latency = read latency -1, (3) Off-Chip Driver(OCD) impedance adjustment, (4) On Die Ter-
mination.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized
with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. A fourteen bit address
bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For
example, 512Mb(x4) device receive 14/11/2 addressing.
The 512Mb DDR2 devices operate with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The 512Mb DDR2 devices are available in 60ball FBGAs(x4/8) and in 84ball FBGAs(x16).
Note: The functionality described and the timing specifications included in this data sheet are for the DLL
Enabled mode of operation.
Rev. 0.91 (Sep. 2003)
Page 6 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
2. Package Pinout/Mechnical Dimension & Addressing
2.1 Package Pinout
x4 package pinout (Top View) : 60ball FBGA Package
1
2
3
7
8
9
VDDQ
NC
VDD
NC
NC
VSSQ
VSS
DM
A
B
C
DQS
VSSQ
VSSQ
DQS
VDDQ
DQ3
VDDQ DQ0
VDDQ
VDDQ DQ1
VSSQ
NC
DQ2
VSSQ
CK
NC
D
E
F
VDDL
VREF
VSSDL
VSS
VDD
ODT
CK
CKE
BA0
WE
RAS
CAS
NC
BA1
CS
G
H
J
A10
A3
A1
A5
A2
A6
A0
VDD
VSS
VSS
A4
A7
A9
K
L
A11
NC
A8
VDD
A12
NC
A13
Notes:
B1, B9, D1, D9 = NC for x4 organization.
Pins B3 has identical capacitance as pins B7.
VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device from
VDD, VDDQ, VSS, and VSSQ.
Ball Locations (x4)
: Populated Ball
: Depopulated Ball
+
Top View (See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+
+
G
H
J
+
+
+
K
L
+
+
Rev. 0.91 (Sep. 2003)
Page 7 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
x8 package pinout (Top View) : 60ball FBGA Package
1
2
3
7
8
9
NU/
VSSQ
VDD
DQ6
VSS
DQS
VSSQ
DQ0
VSSQ
CK
VDDQ
A
RDQS
DM/
VSSQ
DQS
VDDQ
DQ2
DQ7
B
C
RDQS
VDDQ
DQ4
DQ1
VSSQ
VREF
CKE
VDDQ
DQ3
VDDQ
DQ5
D
E
F
VDDL
VSS
WE
VSSDL
RAS
VDD
ODT
CK
NC
BA0
A10
A3
BA1
A1
CAS
A2
CS
A0
A4
A8
G
H
J
VDD
VSS
VSS
A5
A6
A7
A9
K
A11
VDD
A12
NC
NC
A13
L
Notes:
1. Pins B3 and A2 have identical capacitance as pins B7 and A8.
2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS
& DQS and input masking function is disabled.
3. The function of DM or RDQS/RDQS are enabled by EMRS command.
4. VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.
Ball Locations (x8)
: Populated Ball
: Depopulated Ball
+
Top View (See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+
+
+
G
H
J
+
+
+
K
L
Rev. 0.91 (Sep. 2003)
Page 8 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
x16 package pinout (Top View) : 84ball FBGA Package
1
2
3
7
8
9
A
VSSQ
UDQS
VDDQ
UDQ2
VSSQ
LDQS
VDDQ
LDQ2
UDQS
VSSQ
VDDQ
VDD
UDQ6
VDDQ
UDQ4
VDD
NC
VSS
UDM
VDDQ
UDQ3
VSS
VSSQ
UDQ1
B
C
UDQ7
VDDQ
UDQ0
VSSQ
LDQS
VSSQ
D
UDQ5
VDDQ
VSSQ
NC
E
F
LDQ6
VDDQ
LDQ4
VDDL
VSSQ
LDQ1
LDM
LDQ7
VDDQ
LDQ5
VDDQ
LDQ3
VSS
LDQ0
VSSQ
CK
G
H
J
VSSQ
VREF
VSSDL
VDD
ODT
K
CK
CKE
BA0
A10
A3
WE
BA1
A1
RAS
CAS
A2
NC
L
CS
A0
A4
A8
M
N
P
VDD
VSS
VSS
A5
A6
A7
A9
A11
R
VDD
A12
NC
NC
NC
Notes:
VDDL and VSSDL are power and ground for the DLL. lt is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
Ball Locations (x16)
: Populated Ball
: Depopulated Ball
+
G
H
J
Top View
(See the balls through the Package)
K
L
+
+
+
+
+
+
M
N
P
R
Rev. 0.91 (Sep. 2003)
Page 9 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
FBGA Package Dimension(x4/x8)
11.00 ± 0.10
6.40
# A1 INDEX MARK (OPTIONAL)
0.80
1.60
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
3.20
(5.50)
(0.90)
(1.80)
60-∅0.45±0.05
∅0.2 M
A B
11.00 ± 0.10
#A1
0.35±0.05
MAX.1.20
Rev. 0.91 (Sep. 2003)
Page 10 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
FBGA Package Dimension(x16)
11.00 ± 0.10
# A1 INDEX MARK (OPTIONAL)
6.40
0.80
1.60
4
9
8
7
6
5
3
2
1
A
B
C
D
E
F
G
H
M
J
K
N
L
P
R
3.20
(6.15)
(0.90)
(1.80)
84-∅0.45±0.05
∅0.2 M
A B
11.00 ± 0.10
#A1
0.35±0.05
MAX.1.20
Rev. 0.91 (Sep. 2003)
Page 11 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
2.2 Input/Output Functional Description
Symbol
Type
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
CK, CK
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE,
are disabled during self refresh.
CKE
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
Rank selection on systems with multiple Ranks. CS is considered part of the command code.
CS
Input
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM
signal for x4x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS/UDQS,
LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register
(EMRS) is programmed to disable ODT.
ODT
RAS, CAS, WE
DM
Input
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS load-
ing. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.
Bank Address Inputs: BA0 and BA1 for 256 and 512Mb, BA0 - BA2 define to which bank an
Active, Read, Write or Precharge command is being applied. Bank address also determines if the
mode register or extended mode register is to be accessed during a MRS or EMRS cycle.
BA0 - BA1
Input
Input
Address Inputs: Provided the row address for Active commands and the column address and
Auto Precharge bit for Read/Write commands to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be pre-
charged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during
Mode Register Set commands.
A0 - A13
DQ
Input/Output Data Input/ Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in
write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the
data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to
simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single
ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to
provide differential pair signaling to the system during both reads and writes. An EMRS(1) control
bit enables or disables all complementary data strobe signals.
DQS, (DQS)
(LDQS), (LDQS)
(UDQS), (UDQS)
(RDQS), (RDQS)
Input/Output
NC
No Connect: No internal electrical connection is present.
DQ Power Supply: 1.8V +/- 0.1V
DQ Ground
V
Supply
Supply
Supply
Supply
Supply
Supply
Supply
DDQ
V
SSQ
V
DLL Power Supply: 1.8V +/- 0.1V
DLL Ground
DDL
V
SSDL
V
Power Supply: 1.8V +/- 0.1V
Ground
DD
V
SS
V
Reference voltage
REF
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)
x4 DQS/DQS
x8 DQS/DQS
if EMRS(1)[A11] = 0
if EMRS(1)[A11] = 1
x8 DQS/DQS, RDQS/RDQS,
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)
x4 DQS
x8 DQS
if EMRS(1) [A11] = 0
if EMRS(1) [A11] = 1
x8 DQS, RDQS,
x16 LDQS and UDQS
Rev. 0.91 (Sep. 2003)
Page 12 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
2.3 512Mb Addressing
Configuration
# of Bank
128Mb x4
64Mb x 8
32Mb x16
4
4
4
Bank Address
Auto precharge
Row Address
BA0,BA1
A10/AP
BA0,BA1
A10/AP
A0 ~ A13
A0 ~ A9
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9
A0 ~ A13
A0 ~ A9,A11
Column Address
* Reference information: The following tables are address mapping information for other densities.
256Mb
Configuration
# of Bank
64Mb x4
32Mb x 8
16Mb x16
4
4
4
Bank Address
Auto precharge
Row Address
BA0,BA1
A10/AP
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A8
A0 ~ A12
A0 ~ A9,A11
Column Address
1Gb
Configuration
# of Bank
256Mb x4
128Mb x 8
64Mb x16
8
8
8
Bank Address
Auto precharge
Row Address
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
A0 ~ A13
A0 ~ A9,A11
A0 ~ A13
A0 ~ A9
A0 ~ A12
A0 ~ A9
Column Address
2Gb
Configuration
# of Bank
512Mb x4
256Mb x 8
128Mb x16
8
8
8
Bank Address
Auto precharge
Row Address
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
A0 ~ A14
A0 ~ A9,A11
A0 ~ A14
A0 ~ A9
A0 ~ A13
A0 ~ A9
Column Address
4Gb
Configuration
1 Gb x4
512Mb x 8
256Mb x16
# of Bank
8
BA0 ~ BA2
A10/AP
tbd
8
BA0 ~ BA2
A10/AP
tbd
8
BA0 ~ BA2
A10/AP
tbd
Bank Address
Auto precharge
Row Address
Column Address/page size
tbd
tbd
tbd
Rev. 0.91 (Sep. 2003)
Page 13 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
3. Command Truth Table.
3.1 Command truth table.
CKE
BA0
Function
CS
RAS
CAS
WE BA1 A15-A11 A10 A9 - A0 Notes
BA2
Previous
Cycle
Current
Cycle
(Extended) Mode Register Set
Refresh (REF)
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
H
H
X
H
L
BA
X
OP Code
1,2
1
X
X
X
X
X
X
Self Refresh Entry
L
L
X
1
X
H
L
X
H
H
H
H
L
Self Refresh Exit
L
H
X
X
X
X
1,7
Single Bank Precharge
Precharge all Banks
Bank Activate
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
BA
X
X
X
L
H
X
X
1,2
1
L
L
L
H
L
BA
Row Address
1,2
Write
H
H
H
H
H
X
X
H
X
H
BA Column
BA Column
BA Column
BA Column
L
H
L
Column 1,2,3,
Column 1,2,3,
Column 1,2,3
Column 1,2,3
Write with Auto Precharge
Read
L
L
L
H
H
H
X
X
H
X
H
Read with Auto-Precharge
No Operation
L
H
X
X
H
X
X
H
X
H
X
X
X
X
X
X
1
1
Device Deselect
Power Down Entry
Power Down Exit
H
L
L
X
X
X
X
X
X
X
X
1,4
1,4
H
1. All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.
2. Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode
Register.
3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes inter-
rupted by a Write" in section 2.2.4 for details.
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements outlined in section 2.2.7.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See
section 2.2.2.4.
6. “X” means “H or L (but a defined logic level)”.
7. Self refresh exit is asynchronous.
Rev. 0.91 (Sep. 2003)
Page 14 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
3.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
CKE
1
3
Command (N)
2
3
Notes
Current State
Power Down
Action (N)
1
Previous Cycle
(N-1)
Current Cycle
RAS, CAS, WE, CS
X
(N)
L
L
L
Maintain Power-Down
Power Down Exit
11, 13, 15
4, 8, 11,13
11, 15
H
L
DESELECT or NOP
X
L
Maintain Self Refresh
Self Refresh Exit
Self Refresh
L
H
L
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
REFRESH
4, 5,9
Bank(s) Active
All Banks Idle
H
H
H
H
Active Power Down Entry
Precharge Power Down Entry
Self Refresh Entry
4,8,10,11,13
4, 8, 10,11,13
6, 9, 11,13
7
L
L
H
Refer to the Command Truth Table
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t
period.
XSNR
Read commands may be issued only after t
(200 clocks) is satisfied.
XSRD
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.
10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or
Precharge operations are in progress. See section 2.2.9 "Power Down" and 3.2.8 "Self Refresh Command" for a detailed list of
restrictions.
11. Minimum CKE high time is three clocks.; minimum CKE low time is three clocks.
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See
section 2.2.2.4.
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh
requirements outlined in section 2.2.7.
14. CKE must be maintained high while the SDRAM is in OCD calibration mode .
15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high or
low in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1) ).
3.3 DM Truth Table
Name (Functional)
Write enable
Write inhibit
DM
-
DQs
Note
1
Valid
H
X
1
1. Used to mask write data, provided coincident with the corresponding data
Rev. 0.91 (Sep. 2003)
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Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
4. Absolute Maximum DC Ratings
Symbol
VDD
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Rating
Units
V
Notes
1
- 1.0 V ~ 2.3 V
VDDQ
VDDL
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
V
V
1
1
1
1
VIN VOUT
,
V
TSTG
°C
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.
5. AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
1.7
Typ.
1.8
Max.
1.9
VDD
VDDL
VDDQ
VREF
VTT
V
V
Supply Voltage
1.7
1.8
1.8
1.9
4
4
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1.2
3
There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must
be less than or equal to VDD.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is
expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
2. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
Rev. 0.91 (Sep. 2003)
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Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Operating Temperature Condition
SYMBOL
TOPER
PARAMETER
RATING
0 to 95
UNITS
NOTES
1, 2
Operating Temperature
°C
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM.
2. The operation temperature range are the temperature where all DRAM specification will be supported.
Input DC Logic Level
Symbol
VIH(dc)
Parameter
dc input logic high
dc input logic low
Min.
Max.
Units
V
Notes
VREF + 0.125
VDDQ + 0.3
VIL(dc)
- 0.3
VREF - 0.125
V
Input AC Logic Level
Symbol
IH (ac)
Parameter
Min.
Max.
-
Units
V
Notes
V
VREF + 0.250
ac input logic high
ac input logic low
VIL (ac)
-
VREF - 0.250
V
AC Input Test Conditions
Symbol
Condition
Input reference voltage
Value
Units
Notes
V
V
0.5 * V
1.0
V
V
1
1
REF
DDQ
Input signal maximum peak to peak swing
Input signal minimum slew rate
SWING(MAX)
SLEW
1.0
V/ns
2, 3
Note :
1. Setup (tIS & tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vih(dc)min and the
first crossing of Vih(ac)min. Setup (tIS & tDS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of Vil(dc)max and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line
between shaded ‘dc to ac region’, use nominal slew rate for derating value (see Fig a.) If the actual signal is later than the nominal
slew rate line anywhere between shaded ‘dc to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc
level is used for derating value (see Fig b.)
2. Hold (tIH & tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first
crossing of Vref. Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
Vih(dc)min and the first crossing of Vref. If the actual signal is always later than the nominal slew rate line between shaded ‘dc to
Vref region’, use nominal slew rate for derating value (see Fig a.) If the actual signal is earlier than the nominal slew rate line any-
where between shaded ‘dc to Vref region’, the slew rate of a tangent line to the actual signal from the dc level to Vref level is used
for derating value (see Fig b.)Input waveform timing is referenced to the input signal crossing through the V
level applied to the
REF
device under test.
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Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
DQS
DQS
CK
CK
Hold
Time
Setup Hold
Time
Setup
Time
Hold
Time
Hold
Time
Setup
Time
Setup
Time
Time
VDDQ
V
DDQ
VIH(ac) min
VIH(dc) min
V
V
min
IH(ac)
IH(dc)
dc to ac
region
dc to ac
region
min
VREF
V
REF
V
max
max
VIL(dc) max
IL(dc)
IL(ac)
dc to ac
region
dc to ac
region
V
VIL(ac) max
Setup
Delta TR
V
VSS
SS
Hold
Delta TR
Hold
Delta TF
Hold
Delta TF
Setup
Delta TF
Hold
Delta TR
Setup
Delta TR
Setup
Delta TF
tangent line[Vih(ac)min - Vih(dc)min]
Setup Delta TR
Setup Slew Rate
Rising Signal
Vil(dc)max - Vil(ac)max
Setup Delta TF
Setup Slew Rate
Falling Signal
=
=
Setup Slew Rate
Rising Signal
Vih(ac)min - Vih(dc)min
Setup Delta TR
tangent line[Vil(dc)max - Vil(ac)max]
Setup Delta TF
Setup Slew Rate
Falling Signal
=
=
=
=
Vref - Vil(dc)max
Hold Delta TR
Hold Slew Rate
Rising Signal
tangent line [ Vref - Vil(dc)max ]
Hold Delta TR
Hold Slew Rate
Rising Signal
Vih(dc)min - Vref
Hold Delta TF
tangent line [ Vih(dc)min - Vref ]
Hold Delta TF
Hold Slew Rate
Falling Signal
Hold Slew Rate
Falling Signal
=
=
<Figure. a>
<Figure. b>
Rev. 0.91 (Sep. 2003)
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Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Differential input AC logic Level
Symbol
VID (ac)
Parameter
Min.
0.5
Max.
Units
V
Notes
1
VDDQ + 0.6
ac differential input voltage
ac differential cross point voltage
VIX (ac)
0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175
V
2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and
UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS
or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V
IL(DC).
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS,
LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC)
- V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in
VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross.
Differential AC output parameters
Symbol
VOX (ac)
Parameter
Min.
Max.
Units
V
Notes
1
0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125
ac differential cross point voltage
Notes:
1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations
in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Rev. 0.91 (Sep. 2003)
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Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Input Signal Overshoot/Undershoot Specification
AC Overshoot/Undershoot Specification for Address and Control Pins A0-A15, BA0-BA2, CS, RAS,
CAS, WE, CKE, ODT
Parameter
Specification
DDR2-400
0.9V
DDR2-533 DDR2-667
Maximum peak amplitude allowed for overshoot area (See Figure 1):
Maximum peak amplitude allowed for undershoot area (See Figure 1):
Maximum overshoot area above VDD (See Figure1).
0.9V
0.9V
0.9V
0.9V
0.9V
0.75 V-ns
0.75 V-ns
0.56 V-ns
0.56 V-ns
0.45 V-ns
0.45 V-ns
Maximum undershoot area below VSS (See Figure 1).
Maximum Amplitude
Overshoot Area
VDD
Volts
(V)
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
AC Overshoot and Undershoot Definition for Address and Control Pins
AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Pins DQ, DQS, DM, CK,
CK
Parameter
Specification
DDR2-533
0.9V
DDR2-400
0.9V
DDR2-667
0.9V
Maximum peak amplitude allowed for overshoot area (See Figure 2):
Maximum peak amplitude allowed for undershoot area (See Figure 2):
Maximum overshoot area above VDDQ (See Figure 2).
0.9V
0.9V
0.9V
0.38 V-ns
0.38 V-ns
0.28 V-ns
0.28 V-ns
0.23 V-ns
0.23 V-ns
Maximum undershoot area below VSSQ (See Figure 2).
Maximum Amplitude
Overshoot Area
VDDQ
Volts
(V)
VSSQ
Undershoot Area
Maximum Amplitude
Time (ns)
AC Overshoot and Undershoot Definition for Clock, Data, Strobe, and Mask Pins
Rev. 0.91 (Sep. 2003)
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Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Power and ground clamps are implemented on the following input only pins:
1. BA0-BA2
2. A0-A15
3. RAS
4. CAS
5. WE
6. CS
7. ODT
8. CKE
V-I Characteristics for input only pins with clamps
Minimum Ground
Clamp Current (mA)
0
Voltage across
clamp(V)
Minimum Power
Clamp Current (mA)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.1
1.0
2.5
4.7
6.8
9.1
11.0
13.5
16.0
18.2
21.0
0.1
1.0
2.5
4.7
6.8
9.1
11.0
13.5
16.0
18.2
21.0
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Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Output Buffer Levels
Output AC Test Conditions
Symbol
VOH
Parameter
SSTL_18 Class II
Units
V
Notes
Minimum Required Output Pull-up under AC Test Load
Maximum Required Output Pull-down under AC Test Load
Output Timing Measurement Reference Level
V
+ 0.603
- 0.603
TT
VOL
V
V
TT
VOTR
0.5 * V
V
1
DDQ
1. The VDDQ of the device under test is referenced.
Output DC Current Drive
Symbol
IOH(dc)
IOL(dc)
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
SSTl_18 Class II
- 13.4
Units
mA
Notes
1, 3, 4
2, 3, 4
13.4
mA
1.
2.
V
= 1.7 V; V
= 1420 mV. (V
- V
)/I must be less than 21 ohm for values of V
between V
and V
- 280
DDQ
DDQ
OUT
OUT
DDQ OH
OUT
DDQ
mV.
V
= 1.7 V; V
= 280 mV. V
/I must be less than 21 ohm for values of V
between 0 V and 280 mV.
DDQ
OUT
OUT OL
OUT
3. The dc value of V
applied to the receiving device is set to V
TT
REF
4. The values of I
and I
are based on the conditions given in Notes 1 and 2. They are used to test device drive current
OH(dc)
OL(dc)
capability to ensure V min plus a noise margin and V max minus a noise margin are delivered to an SSTL_18 receiver. The
IH
IL
actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define
a convenient driver current for measurement.
OCD default characteristics
Description
Parameter
Min
12.6
Nom
18
Max
23.4
Unit
Notes
Output impedance
ohms 1,2
Output impedance step
size for OCD calibration
0
1.5
ohms
6
Pull-up and pull-down
mismatch
0
4
ohms 1,2,3
V/ns 1,4,5
Output slew rate
tbd
tbd
Note 1: Absolute Specifications (0°C ≤ TCASE ≤ +tbd°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
Note 2: Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;
(VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.
Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol
must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
Note 3: Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and
voltage.
Note 4: Slew rate measured from vil(ac) to vih(ac).
Note 5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew
rate as measured from AC to AC. This is guaranteed by design and characterization.
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Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Note 6 : This represents the step size when the OCD is near 18 ohms at nominal conditions across all
process and represents only the DRAM uncertainty. A 0 ohm value (no calibration) can only be achieved if the
OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions.
Output slew rate load :
VTT
25 ohms
Output
(VOUT)
Reference
Point
Rev. 0.91 (Sep. 2003)
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Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Table 1. Full Strength Default Pulldown Driver Characteristics
Pulldow n Current (mA)
Nominal Default
Low (18 ohms)
Nominal Default
High (18 ohms)
Voltage (V) Minimum (23.4 Ohms)
Maximum (12.6 Ohms)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
8.5
11.3
16.5
21.2
25.0
28.3
30.9
33.0
34.5
35.5
36.1
36.6
36.9
37.1
37.4
37.6
37.7
37.9
11.8
16.8
22.1
27.6
32.4
36.9
40.9
44.6
47.7
50.4
52.6
54.2
55.9
57.1
58.4
59.6
60.9
15.9
23.8
31.8
39.7
47.7
55.0
62.3
69.4
75.3
80.5
84.6
87.7
90.8
92.9
94.9
97.0
99.1
101.1
12.1
14.7
16.4
17.8
18.6
19.0
19.3
19.7
19.9
20.0
20.1
20.2
20.3
20.4
20.6
Figure 1. DDR2 Default Pulldown Characteristics for Full Strength Driver
120
100
80
60
40
20
0
Maximum
Nominal
Default
High
Nominal
Default
Low
Minimum
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
VOUT to VSSQ (V)
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Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Table 2. Full Strength Default Pullup Driver Characteristics
Pullup Current (mA)
Nominal Default
Low (18 ohms)
Nominal Default
High (18 ohms)
Voltage (V) Minimum (23.4 Ohms)
Maximum (12.6 Ohms)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
-8.5
-11.1
-16.0
-20.3
-24.0
-27.2
-29.8
-31.9
-33.4
-34.6
-35.5
-36.2
-36.8
-37.2
-37.7
-38.0
-38.4
-38.6
-11.8
-17.0
-22.2
-27.5
-32.4
-36.9
-40.8
-44.5
-47.7
-50.4
-52.5
-54.2
-55.9
-57.1
-58.4
-59.6
-60.8
-15.9
-23.8
-31.8
-39.7
-47.7
-55.0
-62.3
-69.4
-75.3
-80.5
-84.6
-87.7
-90.8
-92.9
-94.9
-97.0
-99.1
-101.1
-12.1
-14.7
-16.4
-17.8
-18.6
-19.0
-19.3
-19.7
-19.9
-20.0
-20.1
-20.2
-20.3
-20.4
-20.6
Figure 2. DDR2 Default Pullup Characteristics for Full Strength Output Driver
0
-20
-40
Minimum
Nominal
Default
Low
-60
Nominal
Default
High
-80
-100
-120
Maximum
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
VDDQ to VOUT (V)
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Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
DDR2 SDRAM Default Output Driver V–I Characteristics
DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by
the EMRS1 bits A7-A9 = ‘111’. Figures 1 and 2 show the driver characteristics graphically, and tables 1 and
2 show the same data in tabular format suitable for input into simulation tools. The driver characteristics
evaluation conditions are:
Nominal Default 25 oC (T case), VDDQ = 1.8 V, typical process
Minimum TBD oC (T case), VDDQ = 1.7 V, slow–slow process
Maximum 0 oC (T case), VDDQ = 1.9 V, fast–fast process
Default Output Driver Characteristic Curves Notes:
1) The full variation in driver current from minimum to maximum process, temperature, and voltage will
lie within the outer bounding lines of the V–I curve of figures 1 and 2.
2) It is recommended that the ”typical” IBIS V–I curve lie within the inner bounding lines of the V–I curves
of figures 1 and 2.
Table 3. Full Strength Calibrated Pulldown Driver Characteristics
Calibrated Pulldow n Current (mA)
Nominal Minimum Nominal Low (18.75
Nominal High (17.25 Nominal Maximum (15
Voltage (V)
Nominal (18 ohms)
(21 ohms)
ohms)
ohms)
ohms)
0.2
0.3
0.4
9.5
10.7
16.0
21.0
11.5
16.6
21.6
11.8
17.4
23.0
13.3
20.0
27.0
14.3
18.7
Table 4. Full Strength Calibrated Pullup Driver Characteristics
Calibrated Pullup Current (mA)
Nominal Minimum Nominal Low (18.75
Nominal High (17.25Nominal Maximum (15
Voltage (V)
Nominal (18 ohms)
(21 ohms)
ohms)
ohms)
ohms)
0.2
0.3
0.4
-9.5
-14.3
-18.7
-10.7
-16.0
-21.0
-11.4
-16.5
-21.2
-11.8
-17.4
-23.0
-13.3
-20.0
-27.0
DDR2 SDRAM Calibrated Output Driver V–I Characteristics
DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by
the procedure outlined in section 2.2.2.3, Off-Chip Driver (OCD) Impedance Adjustment. Tables 3 and 4
show the data in tabular format suitable for input into simulation tools. The nominal points represent a
device at exactly 18 ohms. The nominal low and nominal high values represent the range that can be
achieved with a maximum 1.5 ohm step size with no calibration error at the exact nominal conditions only
(i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). Real system
calibration error needs to be added to these values. It must be understood that these V-I curves as repre-
sented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system cali-
bration error. Since this is a system specific phenomena, it cannot be quantified here. The values in the
calibrated tables represent just the DRAM portion of uncertainty while looking at one DQ only. If the cali
Rev. 0.91 (Sep. 2003)
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Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
bration procedure is used, it is possible to cause the device to operate outside the bounds of the default
device characteristics tables and figures. In such a situation, the timing parameters in the specification can-
not be guaranteed. It is solely up to the system application to ensure that the device is calibrated between the
minimum and maximum default values at all times. If this can’t be guaranteed by the system calibration pro-
cedure, re-calibration policy, and uncertainty with DQ to DQ variation, then it is recommended that only the
default values be used. The nominal maximum and minimum values represent the change in impedance
from nominal low and high as a result of voltage and temperature change from the nominal condition to the
maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation could be as
much as from the nominal minimum to the nominal maximum or vice versa. The driver characteristics evalu-
ation conditions are:
Nominal 25 oC (T case), VDDQ = 1.8 V, typical process
Nominal Low and Nominal High 25 oC (T case), VDDQ = 1.8 V, any process
Nominal Minimum TBD oC (T case), VDDQ = 1.7 V, any process
Nominal Maximum 0 oC (T case), VDDQ = 1.9 V, any process
Rev. 0.91 (Sep. 2003)
Page 27 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
IDD Specification Parameters and Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)
Sym-
bol
Proposed Conditions
DDR2-
667
DDR2-
533
DDR2-
400
Units
Notes
(CL=5)
(CL=4)
(CL=3)
IDD0
Operating one bank active-precharge current;
TBD
TBD
TBD
mA
mA
t
t
t
t
t
t
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD1
Operating one bank active-read-precharge current;
IOUT = 0mA;
TBD
TBD
TBD
BL = 4, CL = CL(IDD), AL = 0;
t
t
t
t
t
t
CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD),
t
t
RCD = RCD(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
IDD2P
IDD2Q
IDD2N
IDD3P
Precharge power-down current;
All banks idle;
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
t
t
CK = CK(IDD);
CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge quiet standby current;
All banks idle;
t
t
CK = CK(IDD);
CKE is HIGH, CS\ is HIGH;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge standby current;
All banks idle;
t
t
CK = CK(IDD);
CKE is HIGH, CS\ is HIGH;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
All banks open;
Fast PDN
Exit MRS(12)
= 0mA
t
t
CK = CK(IDD);
CKE is LOW;
Other control and address bus inputs are
STABLE;
Data bus inputs are FLOATING
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
Slow PDN
Exit MRS(12)
= 1mA
IDD3N
Active standby current;
All banks open;
t
t
t
t
t
t
CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Rev. 0.91 (Sep. 2003)
Page 28 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
IDD4W
Operating burst write current;
All banks open, Continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
t
t
t
t
t
t
CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
mA
t
t
t
t
t
t
CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
IDD5B
Burst auto refresh current;
mA
t
t
CK = CK(IDD);
t
Refresh command at every RFC(IDD) interval;
CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD6
Self refresh current;
CK and CK\ at 0V;
CKE ≤ 0.2V;
Other control and address bus inputs are
FLOATING;
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
Normal
Low Power
Data bus inputs are FLOATING
IDD7
Operating bank interleave read current;
mA
All bank interleaving reads, IOUT = 0mA;
t
t
BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD);
t
t
t
t
t
t
CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD),
t
t
RCD = 1* CK(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
- Refer to the following page for detailed timing conditions
Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combi-
nations of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control
signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including
masks or strobes.
Rev. 0.91 (Sep. 2003)
Page 29 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
For purposes of IDD testing, the following parameters are to be utilized
DDR2-667
DDR2-533
DDR2-400
Parameter
5-5-5
5
4-4-4
4
3-3-3
3
Units
CL(IDD)
tCK
t
15
15
15
RCD(IDD)
ns
ns
t
55
55
55
7.5
10
5
RC(IDD)
t
ns
ns
RRD(IDD)-x4/x8
7.5
7.5
t
RRD(IDD)-x16
10
3
10
t
3.75
CK(IDD)
RASmin(IDD)
ns
ns
t
40
15
40
15
40
15
105
t
ns
ns
RP(IDD)
RFC(IDD)-512Mb
t
105
105
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
t
t
All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 3/3/3
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D
-DDR2-533 4/4/4
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-667 5/5/5
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
Rev. 0.91 (Sep. 2003)
Page 30 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Input/Output capacitance
DDR2-400
DDR2-533
DDR2-667
Min Max
Parameter
Symbol
Min
Max
2.0
Units
pF
Input capacitance, CK and CK
CCK
CDCK
CI
1.0
x
1.0
x
2.0
0.25
2.0
Input capacitance delta, CK and CK
0.25
2.0
pF
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
Input/output capacitance delta, DQ, DM, DQS, DQS
1.0
x
1.0
x
pF
CDI
0.25
4.0
0.25
3.5
pF
CIO
2.5
x
2.5
x
pF
CDIO
0.5
0.5
pF
Electrical Characteristics & AC Timing for DDR2-667/533/400
(0 °C < TCASE < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
tRFC
tREFI
75
105
127.5
7.8
195
7.8
tbd
ns
0 °C ≤ T
≤ 85°C
≤ 95°C
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
CASE
Average periodic refresh interval
85 °C < T
3.9
3.9
CASE
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin (CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
DDR2-667(E6)
DDR2-533(D5)
DDR2-400(CC)
Units
5 - 5- 5
4 - 4 - 4
3 - 3 - 3
min
5
max
8
min
5
max
min
5
max
8
8
-
8
8
-
ns
ns
ns
ns
ns
ns
ns
3.75
3
8
3.75
-
5
8
-
15
15
55
40
15
15
55
40
15
15
55
40
tRP
tRC
70000
70000
70000
tRAS
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Symbol
Units
Notes
Parameter
DDR2-667
min max
DDR2-533
min max
DDR2-400
min
max
Rev. 0.91 (Sep. 2003)
Page 31 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
DQ output access time from
CK/CK
tAC
-450
-400
+450
+400
-500
-450
+500
+450
-600
-500
+600
+500
ps
ps
DQS output access time from
CK/CK
tDQSCK
CK high-level width
CK low-level width
CK half period
tCH
tCL
tHP
0.45
0.45
0.55
0.55
x
0.45
0.45
0.55
0.55
x
0.45
0.45
0.55
0.55
x
tCK
tCK
ps
min(tCL,
tCH)
min(tCL,
tCH)
min(tCL,
tCH)
19,20
23
Clock cycle time, CL=x
tCK
tDH
3000
tbd
8000
x
3750
225
8000
x
5000
275
8000
x
ps
ps
DQ and DM input hold time
14,15,
16
DQ and DM input setup time
tDS
tbd
x
100
0.6
x
150
x
ps
tCK
tCK
ps
14,15,
16
Control & Address input
pulse width for each input
tIPW
tDIPW
tHZ
0.6
x
x
x
0.6
x
DQ and DM input pulse width
for each input
0.35
0.35
x
x
0.35
x
Data-out high-impedance
time from CK/CK
x
tAC max
tAC max
tbd
tAC max
tAC max
300
x
tAC max
tAC max
350
Data-out low-impedance time
from CK/CK
tLZ
tAC min
tAC min
x
tAC min
ps
DQS-DQ skew for DQS and
associated DQ signals
tDQSQ
x
x
x
x
ps
21
20
DQ hold skew factor
tQHS
tQH
tbd
x
x
400
x
450
x
ps
ps
DQ/DQS output hold time
from DQS
tHP -
tQHS
tHP - tQHS
tHP -
tQHS
Write command to first DQS
latching transition
tDQSS
WL - 0.25
WL +
0.25
WL - 0.25
WL +
0.25
WL - 0.25
WL +
0.25
tCK
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
x
x
x
0.35
0.35
0.2
x
x
x
0.35
0.35
0.2
x
x
x
tCK
tCK
tCK
DQS falling edge to CK setup
time
DQS falling edge hold time from
CK
tDSH
tMRD
0.2
2
x
x
0.2
2
x
x
0.2
2
x
x
tCK
tCK
Mode register set command
cycle time
Write preamble setup time
Write postamble
tWPRES
tWPST
tWPRE
tIH
0
x
0.6
x
0
x
0.6
x
0
x
0.6
x
ps
tCK
tCK
ps
0.4
tbd
tbd
0.4
0.4
375
0.4
0.4
475
18
Write preamble
Address and control input
hold time
x
x
x
13,15,
17
Address and control input
setup time
tIS
tbd
0.9
x
250
0.9
x
350
0.9
x
ps
13,15,
17
Read preamble
tRPRE
1.1
1.1
1.1
tCK
Rev. 0.91 (Sep. 2003)
Page 32 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
Read postamble
tRPST
tRRD
0.4
7.5
0.6
x
0.4
7.5
0.6
x
0.4
7.5
0.6
x
tCK
ns
Active to active command
period for 1KB page size
products
12
12
Active to active command
period for 2KB page size
products
tRRD
10
x
10
x
10
x
ns
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
15
2
15
2
tCK
ns
x
x
x
x
15
x
x
Auto precharge write
recovery + precharge time
tDAL
tWR+tRP*
tWR+tRP*
tWR+tRP
*
tCK
22
11
Internal write to read
command delay
tWTR
tRTP
7.5
x
7.5
x
10
x
ns
ns
Internal read to precharge
command delay
7.5
7.5
7.5
Exit self refresh to a non-
read command
tXSNR
tXSRD
tXP
tRFC + 10
tRFC + 10
tRFC +
10
ns
Exit self refresh to a read
command
200
2
200
2
200
2
tCK
tCK
tCK
tCK
Exit precharge power down
to any non-read command
x
x
x
x
x
x
Exit active power down to
read command
tXARD
tXARDS
2
2
2
9
Exit active power down to read
command
6 - AL
6 - AL
6 - AL
9, 10
(Slow exit, Lower power)
tCKE
CKE minimum pulse width
(high and low pulse width)
3
3
tCK
3
tAOND
tAON
ODT turn-on delay
ODT turn-on
2
2
2
2
2
2
tCK
ns
tAC(min)
tAC(max)
+0.7
tAC(min)
tAC(max)
+1
tAC(min)
tAC(max)
+1
13, 24
tAONPD
ODT turn-on(Power-Down
mode)
tAC(min)+
2
2tCK+tAC
(max)+1
tAC(min)+
2
2tCK+tAC
(max)+1
tAC(min)
+2
2tCK+tA
C(max)+1
ns
tAOFD
tAOF
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ns
tAC(min)
tAC(max)+
0.6
tAC(max)+
0.6
tAC(min)
tAC(max)
+ 0.6
tAC(min)
25
tAOFPD
ODT turn-off (Power-Down
mode)
tAC(min)+
2
2.5tCK+tA
C(max)+1
tAC(min)+
2
2.5tCK+
tAC(max)
+1
tAC(min)
+2
2.5tCK+
tAC(max)
+1
ns
ODT to power down entry latency
ODT power down exit latency
tANPD
tAXPD
tOIT
3
8
0
3
8
0
3
8
0
tCK
tCK
ns
OCD drive mode output
delay
12
12
12
Minimum time clocks
remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK+tI
H
tIS+tCK+tI
H
tIS+tCK+t
IH
ns
23
General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
Rev. 0.91 (Sep. 2003)
Page 33 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for
single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between
DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not
necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to
VREF + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to
CK - CK = +500 mV
(250mV to -500 mV for falling egdes).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or
between DQS and DQS for differential strobe.
2. DDR2 SDRAM AC timing reference load
Figure AA represents the timing reference load used in defining the relevant timing parameters of the part.
It is not intended to be either a precise representation of the typical system environment nor a depiction of the
actual load presented by a production tester. System designers will use IBIS or other simulation tools to cor-
relate the timing reference load to a system environment. Manufacturers will correlate to their production test
conditions (generally a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ
DQS
DQS
Output
DUT
V
= V
/2
TT
DDQ
RDQS
RDQS
Timing
reference
point
25Ω
Figure AA : AC Timing Reference Load
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output tim-
ing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement
(e.g. DQS) signal.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in Figure.
VDDQ
DUT
DQ
Output
DQS, DQS
V
= V
/2
TT
DDQ
RDQS, RDQS
25Ω
Test point
Slew Rate Test Load
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS
“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM
pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling
edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data
strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm
Rev. 0.91 (Sep. 2003)
Page 34 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
resisor to insure proper operation.
t
t
DQSL
DQSH
DQS
DQS/
DQS
DQS
t
t
WPST
WPRE
VIH(dc)
VIL(dc)
VIH(ac)
DQ
DM
D
D
D
D
t
VIL(ac)
t
t
DH
DH
VIH(dc)
DS
t
DS
VIH(ac)
DMin
DMin
DMin
DMin
VIL(ac)
VIL(dc)
Figure -- Data input (write) timing
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
QH
t
QH
Figure YY-- Data output (read) timing
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
may be guaranteed by device design or tester correlation.
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer-
ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full volt-
age range specified.
Specific Notes for dedicated AC parameters
9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be
used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit
timing where a lower power value is defined by each vendor data sheet.
10. AL = Additive Latency
11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and
tRAS(min) have been satisfied.
Rev. 0.91 (Sep. 2003)
Page 35 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency
13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for
other slew rate values.
14. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0
V/ns. See System Derating for other slew rate values.
15. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS
signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single
ended mode. See System Derating for other slew rate values.
16. tDS and tDH (data setup and hold) derating
1) Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising
signal and VIL(ac) for a falling signal applied to the device under test.
2) Input waveform timing is referenced from the input signal crossing at the VIH(dc) level for a rising
signal and VIL(dc) for a falling signal applied to the device under test.
DQS
DQS
tDH
tDH
tDS
tDS
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF
min
min
max
max
IL(dc)
IL(ac)
SS
17. tIS and tIH (input setup and hold) derating
1) Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising
signal and VIL(ac) for a falling signal applied to the device under test.
2) Input waveform timing is referenced from the input signal crossing at the VIH(dc) level for a rising
signal and VIL(dc) for a falling signal applied to the device under test
Rev. 0.91 (Sep. 2003)
Page 36 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
CK
CK
tIH
tIH
tIS
tIS
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF
min
min
max
max
IL(dc)
IL(ac)
SS
18. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
19. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as pro-
vided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH). For
example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock source, and
less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces.
20. t QH = t HP – t QHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the
next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
21. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the
output drivers for any given cycle.
22. t DAL = (nWR) + ( tRP/tCK):
For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the
application clock period. nWR refers to the t WR parameter stored in the MRS.
Example: For DDR533 at t CK = 3.75 ns with t WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns)
clocks =4 +(4)clocks=8clocks.
23. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In
case of clock frequency change during precharge power-down, a specific procedure is required as described
in section 3.2.9.
Rev. 0.91 (Sep. 2003)
Page 37 of 38
Preliminary
DDR2 SDRAM
512Mb B-die DDR2 SDRAM
24. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
25. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD
Rev. 0.91 (Sep. 2003)
Page 38 of 38
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