K4X56163PE-LGC2 [SAMSUNG]
DDR DRAM, 16MX16, 2ns, CMOS, PBGA60,;
| 型号： | K4X56163PE-LGC2 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 16MX16, 2ns, CMOS, PBGA60, 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总48页 (文件大小：699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4X56163PE-L(F)G
Mobile-DDR SDRAM
16M x16 Mobile DDR SDRAM
FEATURES
• 1.8V power supply, 1.8V I/O power
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• MRS cycle with address key programs
- CAS Latency ( 3 )
- Burst Length ( 2, 4, 8 )
- Burst Type (Sequential & Interleave)
- Partial Self Refresh Type ( Full, 1/2, 1/4 array )
- Internal Temperature Compensated Self Refresh
- Driver strength ( 1, 1/2, 1/4, 1/8 )
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• LDM/UDM for write masking only.
• 7.8us auto refresh duty cycle.
• CSP package.
Operating Frequency
DDR200
DDR133
Speed @CL3
*CL : CAS Latency
100Mhz
66Mhz
Column address configuration
Organization
Row Address
Column Address
16Mx16
A0 ~ A12
A0-A8
DM is internally loaded to match DQ and DQS identically.
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K4X56163PE-L(F)G
Mobile-DDR SDRAM
Package Dimension and Pin Configuration
*1
*2
< Bottom View
>
< Top View
>
E
1
60Ball(6x10) CSP
9
8
7
6
5
4
3
2
1
1
2
3
7
8
9
A
B
C
D
E
F
A
B
C
D
E
F
VSS
DQ15 VSSQ
VDDQ
DQ0
DQ2
DQ4
DQ6
VDD
VDDQ DQ13 DQ14 DQ1
VSSQ DQ11 DQ12 DQ3
VSSQ
VDDQ
VSSQ
VDDQ
DQ9 DQ10 DQ5
VSSQ UDQS DQ8
DQ7 LDQS VDDQ
VSS
CKE
A9
UDM
CK
N.C.
CK
N.C.
WE
CS
LDM
CAS
BA0
VDD
RAS
BA1
A1
G
H
G
H
J
A11
A7
A12
A6
A8 A10/AP A0
A5 A2 A3
J
K
VSS
A4
VDD
K
E
E/2
Ball Name
CK, CK
CS
Ball Function
System Differential Clock
Chip Select
*2: Top View
CKE
Clock Enable
A0 ~ A12
BA0 ~ BA1
RAS
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
A
A1
Max. 0.20
Encapsulant
z
CAS
j b
WE
*1: Bottom View
L(U)DM
L(U)DQS
DQ0 ~ 15
VDD/VSS
VDDQ/VSSQ
Data Input Mask
Data Strobe
*2
< Top View >
Data Input/Output
Power Supply/Ground
#A1 Ball Origin Indicator
Data Output Power/Ground
[Unit:mm]
Symbol
Min
Typ
0.95
0.35
11.0
6.4
Max
A
0.90
1.00
A
0.30
0.40
1
E
-
-
E
-
-
1
D
-
9.0
-
-
D
-
7.2
1
e
-
0.40
-
0.80
0.45
-
-
jb
z
0.50
0.10
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March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Input/Output Function Description
SYMBOL
CK, CK
TYPE
Input
DESCRIPTION
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the
crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from
CK/CK.
CKE
Input
Input
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is
synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input
buffers, excluding CK, CK and CKE , are disabled during power-down and self refresh mode which are
contrived for low standby power consumption.
CS
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder.
All commands are masked when CS is registered HIGH. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
RAS, CAS, WE Input
*1
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
Input
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM
pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM
corresponds to the data on DQ0-DQ7 ; UDM corresponds to the data on DQ8-DQ15.
LDM,UDM
BA0, BA1
A [n : 0]
Input
Input
Bank Address Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE
command is being applied.
Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO
PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only
one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the
op-code during a MODE REGISTER SET command. BA0 and BA1 determines which mode register
( mode register or extended mode register ) is loaded during the MODE REGISTER SET command.
*1
I/O
I/O
Data Input/Output : Data bus
DQ
*1
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write
data. it is used to fetch write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS
corresponds to the data on DQ8-DQ15.
LDQS,UDQS
NC
-
No Connect : No internal electrical connection is present.
DQ Power Supply : 1.7V to 1.95V.
DQ Ground.
VDDQ
VSSQ
VDD
VSS
Supply
Supply
Supply
Supply
Power Supply : 1.7V to 1.95V..
Ground.
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March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Functional Description
Simplified State Diagram
PARTIAL
SELF
REFRESH
SELF
REFRESH
EXTENDED
MODE
REGISTER
SET
REFS
EMRS
REFSX
REFA
MRS
MODE
REGISTER
SET
AUTO
IDLE
ACT
REFRESH
CKEL
CKEH
POWER
DOWN
POWER
DOWN
CKEH
CKEL
ROW
BURST STOP
ACTIVE
WRITE
READ
WRITEA
READA
READ
WRITE
READ
WRITEA
READA
READA
PRE
PRE
PRE
WRITEA
READA
PRE
POWER
APPLIED
POWER
ON
PRE
CHARGE
Automatic Sequence
Command Sequence
Figure.1 State diagram
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K4X56163PE-L(F)G
Mobile-DDR SDRAM
Power Up Sequence for Mobile DDR SDRAM
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
CK
CK
CKE
CS
Hi
RAS
CAS
ADDR
BA0
Key
Key
RAa
BA1
RAa
A10/AP
DQ
Hi-Z
Hi-Z
WE
High level is necessary
tRP
DQM
tARFC
tARFC
Precharge
(All Bank)
Auto
Refresh
Auto
Refresh
Normal
MRS
Row Active
(A-Bank)
Extended
MRS
: Don’t care
Note:
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define PASR or DS operating type of the device after normal MRS.
EMRS cycle is not mandatory and the EMRS command needs to be issued only when either PASR or DS is used.
The default state without EMRS command issued is half driver strength, and Full array refreshed .
The device is now ready for the operation selected by EMRS.
For operating with PASR or DS, set PASR or DS mode in EMRS setting stage.
In order to adjust another mode in the state of PASR or DS mode, additional EMRS set is required but power up sequence is not needed again at this
time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
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K4X56163PE-L(F)G
Mobile-DDR SDRAM
Mode Register Definition
Mode Register Set(MRS)
The mode register is designed to support the various operating modes of DDR SDRAM. It includes CAS latency, addressing mode,
burst length, test mode and vendor specific options to make DDR SDRAM useful for variety of applications. The default value of the
mode register is not defined, therefore the mode register must be written in the power up sequence of DDR SDRAM. The mode reg-
ister is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to
writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going
low is written in the mode register. Two clock cycles are required to complete the write operation in the mode register. Even if the
power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed
with the same command and four clock cycles. This command must be issued only when all banks are in the idle state. If mode reg-
ister is changed, extended mode register automatically is reset and come into default state. So extended mode register must be set
again. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode
uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. BA0 and BA1 must be set to low
for normal DDR SDRAM operation.
Address Bus
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register
0
0
0
0
0
0
0
0
CAS Latency
BT
Burst Length
A3
0
Burst Type
Sequential
Interleave
A6
0
A5
0
A4
0
CAS Latency
Reserve
Reserve
Reserve
3
1
0
0
1
Burst Length
0
1
0
Burst type
0
1
1
A2
A1
A0
Sequential
Reserve
2
Interleave
1
0
0
Reserve
Reserve
Reserve
Reserve
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserve
2
1
0
1
1
1
0
4
4
1
1
1
8
8
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Figure.2 Mode Register Set
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K4X56163PE-L(F)G
Mobile-DDR SDRAM
Burst address ordering for burst length
Burst
Starting Address(A2, A1, A0)
Length
Sequential Mode
Interleave Mode
xx0
0, 1
0, 1
2
xx1
1, 0
1, 0
x00
0, 1, 2, 3
0, 1, 2, 3
x01
1, 2, 3, 0
1, 0, 3, 2
4
x10
2, 3, 0, 1
2, 3, 0, 1
x11
000
001
010
3, 0, 1, 2
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
011
8
100
101
110
111
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March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Extended Mode Register Set(EMRS)
The extended mode register is designed to support partial array self refresh or driver strength. EMRS cycle is not mandatory and
the EMRS command needs to be issued only when either PASR or DS is used. The default state without EMRS command issued is
+85°C, all 4 banks refreshed and the half size of driver strength. The extended mode register is written by asserting low on CS, RAS,
CAS, WE and high on BA1 ,low on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into
the extended mode register). The state of address pins A0 ~ A11 in the same cycle as CS, RAS, CAS and WE going low is written in
the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the
power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed
with the same command and four clock cycles. But this command must be issued only when all banks are in the idle state. A0 - A2
are used for partial array self refresh and A5 - A6 are used for driver strength. "High" on BA1 and"Low" on BA0 are used for EMRS.
All the other address pins except A0,A1,A2, BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for specific
codes.
Extended MRS for PASR(Partial Array Self Refresh) &
TCSR(Internal Temperature Compensated Self Refresh)
Address Bus
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A12
Mode Register
0
0
0
0
0
0
0
DS
PASR
1
0
0
DS
Internal TCSR
PASR
A6
0
A5
Driver Strength
Self refresh cycle is controlled
automatically by internal tem-
perature sensor and control cir-
cuit according to the two
temperature ; Max 40 °C,Max
85 °C
A2
0
A1
A0
0
# of Banks
0
1
0
1
Full
1/2
1/4
1/8
0
0
1
1
0
0
1
1
Full Array
1/2 Array
1/4 Array
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
1
1
0
0
1
0
1
1
0
1
1
1
0
1
1
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March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Internal Temperature Compensated Self Refresh (TCSR)
Note :
1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the
self refresh cycle automatically according to the two temperature range ; Max. 40 °C, Max. 85 °C.
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
Self Refresh Current (Icc 6)
Temperature Range
Unit
Full Array
150
1/2 Array
125
1/4 Array
115
Max. 40 °C
Max. 85 °C
uA
400
300
250
Partial Array Self Refresh (PASR )
Note :
1. In order to save power consumption, Mobile DDR SDRAM includes PASR option.
2. Mobile DDR SDRAM supports three kinds of PASR in self refresh mode; Full Array, 1/2 Array, 1/4 Array.
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
- 1/4 Array
- Full Array
- 1/2 Array
Partial Self Refresh Area
Figure.3 EMRS code and TCSR , PASR
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March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Precharge
The precharge command is used to precharge or close a bank that has been activated. The precharge command is issued when CS,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank
respectively or all banks simultaneously. The bank select addresses(BA0, BA1) are used to define which bank is precharged when
the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from
the precharge, an active command to the same bank can be initiated.
Bank selection for precharge by Bank address bits
A10/AP
BA1
0
BA0
0
Precharge
Bank A Only
Bank B Only
Bank C Only
Bank D Only
All Banks
0
0
0
0
1
0
1
1
0
1
1
X
X
No Operation(NOP) & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs. The
DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS, CAS and WE. Both Device Deselect and NOP com-
mand can not affect operation already in progress. So even if the device is deselected or NOP command is issued under operation,
operation will be complete.
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K4X56163PE-L(F)G
Mobile-DDR SDRAM
Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The
DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command
must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or
write command must meet or exceed the minimum of RAS to CAS delay time(tRCD min). Once a bank has been activated, it must be
precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between inter-
leaved Bank Activation commands(Bank A to Bank B and vice versa) is the Bank to Bank delay time(tRRD min).
Bank Activation Command Cycle
Tn
Tn+1
Tn+2
0
1
2
3
4
5
CK
CK
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank A
Row. Addr.
Address
RAS-CAS delay(tRCD)
RAS-RAS delay time(tRRD)
Bank A
Bank A
Activate
Write A
with Auto
Bank B
Activate
NOP
NOP
NOP
NOP
NOP
Command
Activate
Precharge
ROW Cycle Time(tRC)
: Don′t care
Figure.4 Bank activation command cycle timing
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating
RAS, CS, CAS, and deasserting WE at the same clock sampling(rising) edge as described in the command truth table. The length of
the burst and the CAS latency time will be determined by the values programmed during the MRS cycle.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating
RAS, CS, CAS, and WE at the same clock sampling(rising) edge as described in the command truth table. The length of the burst will
be determined by the values programmed during the MRS cycle.
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K4X56163PE-L(F)G
Mobile-DDR SDRAM
Essential Functionality for DDR SDRAM
The essential functionality that is required for the DDR SDRAM device is described in this chapter
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the SDRAM such that the Burst read command is issued by assert-
ing CS and CAS low while holding RAS and WE high at the rising edge of the clock(CK) after tRCD from the bank activation. The
address inputs (A0~A9) determine the starting address for the Burst. The Mode Register sets type of burst(Sequential or interleave)
and burst length(2, 4, 8). The first output data is available after the CAS Latency from the READ command, and the consecutive data
are presented on the falling and rising edge of Data Strobe(DQS) adopted by DDR SDRAM until the burst length is completed.
< Burst Length=4, CAS Latency= 3 >
0
1
2
3
4
5
6
7
8
CK
CK
Command
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tSAC
tRPST
tRPRE
DQS
Postamble
Preamble
CAS Latency=3
DQs
Dout 0 Dout 1 Dout 2 Dout 3
Figure.5 Burst read operation timing
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K4X56163PE-L(F)G
Mobile-DDR SDRAM
Burst Write Operation
The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The
address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The
first data of a burst write cycle must be applied on the DQ pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS
from the rising edge of the clock(CK) that the write command is issued. The remaining data inputs must be supplied on each subse-
quent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data
supplied to the DQ pins will be ignored.
< Burst Length=4 >
0
1
2
3
4
5
6
7
8
*1
CK
CK
Command
DQS
NOP
WRITEA
NOP
WRITEB
NOP
NOP
NOP
NOP
NOP
tDQSSmax
tWPRES*1
*1
Din 3
Din 0 Din 1 Din 2
Din 3
DQs
Din 0 Din 1 Din 2
Figure.6 Burst write operation timing
1. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown
(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus.
If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
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K4X56163PE-L(F)G
Mobile-DDR SDRAM
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read com-
mand continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data
from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.
< Burst Length=4, CAS Latency=3 >
0
1
2
3
4
5
6
7
8
CK, CK
Command
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tSAC
DQS
tRPRE
CAS Latency=3
DQs
Preamble
Dout A0 Dout A1 Dout B0 Dout B1 Dout B2 Dout B3
Figure.7 Read interrupted by a read timing
Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by
placing the DQs(Output drivers) in a high impedance state. To insure the DQs are tri-stated one cycle before the beginning of the
write operation, Burst stop command must be applied at least 2 clock cycles for CL=2 and at least 3 clock cycles for CL=3 before the
Write command.
< Burst Length=4, CAS Latency=3 >
0
1
2
3
4
5
6
7
8
CK, CK
NOP
NOP
WRITE
Command
READ
Burst Stop
NOP
NOP
NOP
tDQSS
tWPREH
tWPRES
tSAC
tRPRE
DQS
CAS Latency=3
DQs
Preamble
Din 0 Din 1 Din 2 Din 3
Dout 0 Dout 1
Figure.8 Read interrupted by a write and burst stop timing.
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the
DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command
= RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
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K4X56163PE-L(F)G
Mobile-DDR SDRAM
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge
intervals. A precharge command to output disable latency is equivalent to the CAS latency.
< Burst Length=8, CAS Latency=3 >
0
1
2
3
4
5
6
7
8
CK, CK
1tCK
Precharge
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tSAC
tRPRE
DQS
CAS Latency=3
DQs
Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7
Interrupted by precharge
Figure.9 Read interrupted by a precharge timing
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read
burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when
a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate
command may be issued to the same bank after tRP (RAS Precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge
which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data
word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after
tRP.
3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP
begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. During
Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external
Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between
a Precharge command and a new Bank Activate command to the same bank equals tRP/tCK (where tCK is the clock cycle time)
with the result rounded up to the nearest integer number of clock cycles. (Note that rounding to X.5 is not possible since the
Precharge and Bank Activate commands can only be given on a rising clock edge).In all cases, a Precharge operation cannot
be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with
autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same
timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst.
15
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that
separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are
overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
< Burst Length=4 >
0
1
2
3
4
5
6
7
8
CK
CK
1tCK
Command
NOP
WRITE A
WRITE b
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQs
Din A
0
Din A
1
Din B
0
Din B
1
Din B
2
Din B
3
Figure.10 Write interrupted by a write timing
16
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access
is allowed. A write recovery time(tWR) is required from the last data to precharge command. When precharge command is
asserted, any residual data from the burst write cycle must be masked by DM.
< Burst Length=8 >
0
1
2
3
4
5
6
7
8
CK, CK
NOP
tWR
Command
NOP
WRITE A
NOP
tDQSSmax
NOP
NOP
Precharge
WRITE B
NOP
tDQSSmax
tWPREH
tWPRES
DQS
tWPREH
tWPRES
Max tDQSS
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
Dinb0 Dinb1
DQs
DM
tWR
tDQSSmin
tDQSSmin
DQS
Min tDQSS
DQs
tWPRES
tWPREH
Dinb0 Dinb1
tWPRES
tWPREH
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6
Dinb2
Dina7
DM
Figure.11 Write interrupted by a precharge and DM timing
Precharge timing for Write operations in DRAMs requires enough time to allow ’’write recovery’’ which is the time required by a DRAM
core to properly store a full ’’0’’ or ’’1’’ level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used to
indicate the required amount of time between the last valid write operation and a Precharge command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled
by the input clock. Inside the SDRAM, the data path is eventually synchronized with the address path by switching clock domains
from the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated
after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal
write operation, i.e., the input clock domain.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and ends on the rising clock
edge that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write
recovery is defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time
between the last valid write data and the rising clock edge on which the Precharge command is given. During this time, the DQS
input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR.
17
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where
tWR+tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the
Bank Activate command. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the
earliest possible external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with
autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which
does not interrupt the burst.
5. Refer to "3.3.2 Burst write operation"
Burst Stop
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock(CK). The burst
stop command has the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has
been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS(Data Strobe) go to a
high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is
not supported during a write burst operation.
< Burst Length=4, CAS Latency= 3 >
0
1
2
3
4
5
6
7
8
CK, CK
Command
READ A
Burst Stop
NOP
NOP
NOP
NOP
NOP
NOP
NOP
The burst read ends after a delay equal to the CAS latency.
DQS
CAS Latency=3
DQs
Dout 0 Dout 1
Figure.12 Burst stop timing
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required:
1. The BST command may only be issued on the rising edge of the input clock, CK.
2. BST is only a valid command during Read bursts.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with autoprecharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued L
(“BST Latency”) clock cycles before the clock
BST
edge at which the output buffers are tristated, where L
equals the CAS latency for read operations.
BST
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s).
18
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read cycle. When the data mask
is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data.(DM to data-mask latency is
zero).
DM must be issued at the rising or falling edge of data strobe.
< Burst Length=8 >
0
1
2
3
4
5
6
7
8
CK, CK
Command
WRITE
NOP
tDQSSmax
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQs
DM
tWPREH
Din 0
tWPRES
Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din7
masked by DM=H
Figure.13 DM masking timing
19
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Read With Auto Precharge
If a read with auto-precharge command is issued, the DDR SDRAM automatically enters the precharge operation BL/2 clock later
from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed
until tRAS(min) is satisfied. Once the precharge operation has started, the bank cannot be reactivated and the new command can not
be asserted until the precharge time(tRP) has been satisfied.
< Burst Length=4, CAS Latency= 3>
0
1
2
3
4
5
6
7
8
9
10
11
CK, CK
BANK A
ACTIVE
READ A
Auto Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
* Bank can be reactivated at
completion of tRP
tRP
DQS
CAS Latency=3
DQs
Dout0Dout1Dout2Dout3
Auto-Precharge starts*1
tRAS(min)
Figure.14 Read with auto precharge timing
*Note : 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal
20
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Write with Auto Precharge
If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new command to the same
bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min).
< Burst Length=4 >
0
1
2
3
4
5
6
7
8
9
10
11
CK, CK
BANK A
ACTIVE
WRITE A
Auto Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
DQS
DQs
* Bank can be reactivated at
completion of tRP
Din 0 Din 1 Din 2 Din 3
tWR
tRP
Internal precharge start *1
Figure 15. Write with auto precharge timing
*Note : 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal
21
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CK).
All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address
pins is required once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks
will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh com-
mand must be greater than or equal to the tARFC(min).
CK
CK
Auto
Refresh
PRE
CMD
Command
CKE = High
tRP
tARFC(min)
Figure.16 Auto refresh timing
Self Refresh
A Self Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once
the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1 clock cycle from the self
refresh command, all of the external control signals including system clock(CK, CK) can be disabled except CKE. The clock is inter-
nally disabled during Self Refresh operation to reduce power. To exit the Self Refresh mode, supply stable clock input before return-
ing CKE high, assert deselect or NOP command and then assert CKE high. In case that the system uses burst auto refresh during
normal opreation, it is recommended to use burst 8192 auto refresh cycle immediately before entering self refresh mode and after
exiting in self refresh mode. On the other hand, if the system uses the distributed auto refresh, the system only has to keep the
refresh duty cycle.
CK, CK
Stable Clock
Self
Active
NOP
Command
Refresh
tSRFX(min)
CKE
tIS
tIS
Figure.17 Self refresh timing
22
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Power down
The device enters power down mode when CKE Low,and it exits when CKE High. Once the power down mode is initiated, all of the
receiver circuits except CK and CKE are gated off to reduce power consumption. The both bank should be in idle state prior to enter-
ing the precharge power down mode and CKE should be set high at least 1 tCK+tIS prior to Row active command. During power
down mode, refresh operations cannot be performed, therefore the device cannot remain in power down mode longer than the
refresh period(tREF) of the device.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CK, CK
Precharge
power
Precharge
power
Active
power
down
Active
power
down
Exit
Command
Precharge
Active
Read
down
down
Entry
Entry
Exit
(NOP)
tPDEX
CKE
tIS
tIS
tIS
tIS
Figure.18 Power down entry and exit timing
23
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Command Truth Table(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
A11,
A9 ~ A0
COMMAND
Mode Register Set
CKEn-1 CKEn CS
RAS
CAS
WE BA0,1 A10/AP
Note
Register
Refresh
H
H
X
H
L
L
L
L
L
L
OP CODE
1, 2
3
Auto Refresh
L
L
H
X
X
Entry
Exit
3
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
L
H
H
H
X
X
3
Bank Active & Row Addr.
V
V
Row Address
Read &
Auto Precharge Disable
Auto Precharge Enable
L
Column
Address
(A0~A8)
4
4
L
H
L
H
Column Address
H
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
L
Column
Address
(A0~A8)
4
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
4, 6
Burst Stop
Precharge
X
7
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
L
H
L
Active Power Down
X
X
Exit
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
DM
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2.EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
24
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Functional Truth Table
Current State
CS
L
RAS CAS
WE
L
Address
Command
Action
PRECHARGE
STANDBY
H
H
L
H
L
X
Burst Stop
READ/WRITE
Active
ILLEGAL*2
ILLEGAL*2
L
X
BA, CA, A10
L
H
H
L
H
L
BA, RA
Bank Active, Latch RA
ILLEGAL*4
L
L
BA, A10
PRE/PREA
Refresh
L
L
H
L
X
AUTO-Refresh*5
Mode Register Set*5
NOP
L
L
L
Op-Code, Mode-Add
X
MRS
ACTIVE
L
H
H
L
Burst Stop
STANDBY
Begin Read, Latch CA,
Determine Auto-Precharge
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ/READA
Begin Write, Latch CA,
Determine Auto-Precharge
WRITE/WRITEA
L
L
L
L
L
L
L
L
L
H
H
H
L
H
L
BA, RA
Active
Bank Active/ILLEGAL*2
Precharge/Precharge All
ILLEGAL
BA, A10
PRE/PREA
Refresh
MRS
H
L
X
L
Op-Code, Mode-Add
X
ILLEGAL
READ
H
L
Burst Stop
Terminate Burst
Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3
L
H
L
H
BA, CA, A10
READ/READA
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
BA, CA, A10
BA, RA
BA, A10
X
WRITE/WRITEA
Active
ILLEGAL
Bank Active/ILLEGAL*2
Terminate Burst, Precharge
ILLEGAL
PRE/PREA
Refresh
H
L
L
Op-Code, Mode-Add MRS
ILLEGAL
25
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Functional truth table
Current State
CS
RAS CAS WE
Address
Command
Burst Stop
Action
WRITE
L
H
H
L
X
ILLEGAL
Terminate Burst With DM=High, Latch CA,
Begin Read, Determine Auto-Precharge*3
L
L
H
L
H
BA, CA, A10
BA, CA, A10
READ/READA
Terminate Burst, Latch CA,
Begin new Write, Determine Auto-Pre-
charge*3
H
L
L
WRITE/WRITEA
L
L
L
L
H
H
H
L
BA, RA
BA, A10
X
Active
Bank Active/ILLEGAL*2
Terminate Burst With DM=High,
Precharge
PRE/PREA
Refresh
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
ILLEGAL
ILLEGAL
ILLEGAL
*6
Op-Code, Mode-Add MRS
READ with
AUTO
H
H
H
L
H
L
L
X
Burst Stop
READ/READA
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
*6
PRECHARGE
(READA)
L
WRITE/WRITEA ILLEGAL
H
H
L
H
L
Active
*6
L
PRE/PREA
Refresh
*6
L
H
L
ILLEGAL
ILLEGAL
ILLEGAL
*7
L
L
Op-Code, Mode-Add MRS
WRITE with
AUTO
H
H
H
L
H
L
L
X
Burst Stop
READ/READA
WRITE/WRITEA *7
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
*7
RECHARGE
(WRITEA)
L
H
H
L
H
L
Active
*7
L
PRE/PREA
Refresh
*7
L
H
L
ILLEGAL
ILLEGAL
L
L
Op-Code, Mode-Add MRS
26
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Functional truth table
Current State
CS
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
H
H
L
CAS
H
L
WE
L
Address
Command
Action
ILLEGAL*2
PRECHARGING
(DURING tRP)
X
Burst Stop
READ/WRITE
Active
X
H
L
BA, CA, A10
ILLEGAL*2
ILLEGAL*2
NOP*4(Idle after tRP)
ILLEGAL
H
H
L
BA, RA
L
BA, A10
PRE/PREA
Refresh
MRS
L
H
L
X
L
L
Op-Code, Mode-Add
ILLEGAL
ROW
ACTIVATING
H
H
L
H
L
L
X
Burst Stop
READ/WRITE
Active
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL
X
H
L
BA, CA, A10
(FROM ROW
ACTIVE TO
tRCD)
H
H
L
BA, RA
BA, A10
L
PRE/PREA
Refresh
MRS
L
H
L
X
L
L
Op-Code, Mode-Add
ILLEGAL
WRITE
RECOVERING
H
H
H
L
H
L
L
X
Burst Stop
READ
ILLEGAL*2
ILLEGAL*2
WRITE
H
L
BA, CA, A10
BA, CA, A10
BA, RA
(DURING tWR
OR tCDLR)
L
WRITE
H
H
L
H
L
Active
ILLEGAL*2
ILLEGAL*2
ILLEGAL
L
BA, A10
PRE/PREA
Refresh
MRS
L
H
L
X
L
L
Op-Code, Mode-Add
ILLEGAL
27
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Functional truth table
Current State
CS
L
RAS
H
H
L
CAS
H
L
WE
L
Address
Command
Action
RE-
FRESHING
X
Burst Stop
READ/WRITE
Active
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
L
X
H
L
BA, CA, A10
L
H
H
L
BA, RA
L
L
BA, A10
PRE/PREA
Refresh
L
L
H
L
X
L
L
L
Op-Code, Mode-Add
MRS
MODE
REGISTER
SETTING
L
H
H
L
H
L
L
X
Burst Stop
READ/WRITE
Active
L
X
H
L
BA, CA, A10
BA, RA
L
H
H
L
BA, A10
L
L
PRE/PREA
Refresh
L
L
H
L
X
L
L
L
Op-Code, Mode-Add
MRS
28
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Functional truth table
CKE
n-1
CKE
n
Current State
CS
RAS
CAS
WE
Add
Action
SELF-
L
L
H
H
H
H
H
L
H
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Exit Self-Refresh
*8
REFRESHING
Exit Self-Refresh
L
L
ILLEGAL
L
L
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
X
X
L
ILLEGAL
L
X
X
X
X
L
X
X
X
X
L
NOPeration(Maintain Self-Refresh)
Exit Power Down(Idle after tPDEX)
NOPeration(Maintain Power Down)
Refer to Function True Table
Enter Self-Refresh
POWER
DOWN
L
H
L
L
ALL BANKS
H
H
H
H
H
H
H
L
H
L
*9
IDLE
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
Enter Power Down
ILLEGAL
L
L
L
L
L
X
X
X
X
ILLEGAL
L
L
X
X
X
ILLEGAL
X
H
X
X
X
X
Refer to Current State=Power Down
Refer to Function Truth Table
ANY STATE
other than
H
listed above
ABBREVIATIONS :
H=High Level, L=Low level, X=Don′t Care
Note :
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around and write recovery requirements.
4. NOP to bank precharging or in idle sate. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
6. Refer to "3.3.10 Read with Auto Precharge" for detailed information.
7. Refer to "3.3.11 Write with Auto Precharge" for detailed information.
8. CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any
command other than EXIT.
9. Power-Down and Self-Refresh can be entered only from All Bank Idle state.
ILLEGAL = Device operation and/or data integrity are not guaranteed.
29
March 2004
Table 10. Absolute maximum ratings
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Absolute maximum ratings
Parameter
Symbol
, V
OUT
Value
Unit
Voltage on any pin relative to V
V
-0.5 ~ 2.7
-0.5 ~ 2.7
-0.5 ~ 2.7
-55 ~ +150
1.0
V
SS
IN
Voltage on V supply relative to V
V
DD
V
V
DD
SS
Voltage on V
supply relative to V
V
DDQ
DDQ
SS
Storage temperature
Power dissipation
Short circuit current
T
°C
W
STG
P
D
I
50
mA
OS
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Conditions & Specifications
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA= -25°C to 85°C)
Parameter
Supply voltage(for device with a nominal VDD of 1.8V)
I/O Supply voltage
Symbol
VDD
Min
Max
Unit
Note
1.7
1.95
VDDQ
VIH(DC)
VIL(DC)
VOH(DC)
VOL(DC)
II
1.7
1.95
V
V
Input logic high voltage
0.7 x VDDQ
VDDQ+0.3
1
Input logic low voltage
-0.3
0.3 x VDDQ
V
1
Output logic high voltage
Output logic low voltage
0.9 x VDDQ
-
V
IOH = -0.1mA
IOL = 0.1mA
-
0.1 x VDDQ
V
Input leakage current
-2
-5
2
5
uA
uA
Output leakage current
IOZ
Notes : 1. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation.
30
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, Temp = -25 to 85°C)
Parameter
Symbol
Test Condition
DDR200
DDR133
Unit
t RC = t RCmin ; t CK = t CKmin ; CKE is HIGH; CS is HIGH
between valid commands;
address inputs are SWITCHING; data bus inputs are STA-
BLE
Operating Current
(One Bank Active)
ICC0
30
30
mA
all banks idle, CKE is LOW; CS is HIGH, t CK = t CKmin ;
address and control inputs are SWITCHING; data bus inputs
are STABLE
0.3
0.3
ICC2P
Precharge Standby Current in
power-down mode
mA
mA
mA
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK =
HIGH; address and control inputs are SWITCHING; data
bus inputs are STABLE
ICC2PS
ICC2N
all banks idle, CKE is HIGH; CS is HIGH, t CK = t CKmin
;address and control inputs are SWITCHING; data bus
inputs are STABLE
8
4
8
4
Precharge Standby Current
in non power-down mode
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK =
HIGH; address and control inputs are SWITCHING; data
bus inputs are STABLE
ICC2NS
one bank active, CKE is LOW; CS is HIGH, t CK = t CKmin
;address and control inputs are SWITCHING; data bus
inputs are STABLE
3
1
ICC3P
ICC3PS
ICC3N
Active Standby Current
in power-down mode
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK
= HIGH;address and control inputs are SWITCHING; data
bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, t CK = t CKmin
;address and control inputs are SWITCHING; data bus
inputs are STABLE
10
6
10
6
mA
mA
Active Standby Current
in non power-down mode
(One Bank Active)
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK
= HIGH;
ICC3NS
ICC4R
address and control inputs are SWITCHING; data bus inputs
are STABLE
one bank active; BL = 4; CL = 3; t CK = t CKmin ; continuous
read bursts; I OUT = 0 mA
65
55
mA
mA
address inputs are SWITCHING; 50% data change each
burst transfer
Operating Current
(Burst Mode)
one bank active; BL = 4; t CK = t CKmin ; continuous write
bursts;address inputs are SWITCHING; 50% data change
each burst transfer
ICC4W
ICC5
65
80
55
80
Refresh Current
t RC = t RFCmin ; t CK = t CKmin ; burst refresh; CKE is
HIGH;address and control inputs are SWITCHING; data bus
inputs are STABLE
mA
TCSR Range
Full Array
1/2 Array
Max 40
150
Max 85
400
°C
CKE is LOW; t CK = t CKmin ;
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
Self Refresh Current
ICC6
uA
125
300
1/4 Array
115
250
Notes:
1. IDD specifications are tested after the device is properly intialized.
2. Input slew rate is 1V/ns.
31
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
3. Definitions for IDD:
LOW is defined as V IN ≤ 0.1 * V DDQ ;
HIGH is defined as V IN ≥ 0.9 * V DDQ ;
STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as:
- address and command: inputs changing between HIGH and LOW once per two clock cycles
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
AC Operating Conditions & Timming Specification
Max
Parameter/Condition
Symbol
Min
Unit
Note
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
Input Crossing Point Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VIX(AC)
0.8 x VDDQ
-0.3
VDDQ+0.3
0.2 x VDDQ
0.6 x VDDQ
V
V
V
1
1
2
0.4 x VDDQ
Note : 1. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
32
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
AC Timming Parameters & Specifications
DDR200
DDR133
Parameter
Symbol
Unit
Note
Min
10
80
50
30
30
15
15
Max
Min
15
Max
Clock cycle time
Row cycle time
CL=3.0
tCK
tRC
ns
ns
1
90
Row active time
RAS to CAS delay
Row precharge time
tRAS
tRCD
tRP
60
ns
30
ns
30
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
15
ns
30
ns
Last data in to Active delay
Last data in to Read command
Col. address to Col. address delay
Clock high level width
tDAL
tCDLR
tCCD
tCH
tWR+tRP
tWR+tRP
1
-
2
1
tCK
tCK
tCK
tCK
ns
1
1
0.45
0.45
2.0
0.55
0.55
7.0
0.45
0.45
2.0
0.55
0.55
7.0
Clock low level width
tCL
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
CL=3.0
tSAC
tDQSQ
tRPRE
tRPST
3
1
0.7
0.9
ns
0.9
0.4
1.1
0.9
0.4
1.1
tCK
Read Postamble
0.6
0.6
tCK
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
tDQSS
tWPRES
tWPREH
tDQSH
0.75
0
1.25
0.75
0
1.25
tCK
ns
4
0.25
0.4
0.4
0.25
0.4
0.4
tCK
tCK
DQS-in high level width
DQS-in low level width
0.6
0.6
1.1
0.6
0.6
1.1
tDQSL
tCK
DQS-in cycle time
tDSC
tIS
0.9
1.5
1.5
1.1
0.9
2.0
2.0
1.5
tCK
ns
Address and Control Input setup time
Address and Control Input hold time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
1
1
tIH
ns
tDS
tDH
ns
5,6
ns
1.1
1.5
5,6
DQ & DM input pulse width
DQS write postamble time
Refresh interval time
tDIPW
tWPST
tREF
2.2
0.4
7.8
2
3.0
ns
tCK
us
0.6
0.4
0.6
256Mb
7.8
Mode register set cycle time
Power down exit time
tMRD
2
1*tCK +tIS
80
tCK
ns
tPDEX 1*tCK +tIS
Auto refresh cycle time
tARFC
tSRFX
80
ns
Exit self refresh to active command
120
120
ns
tHPmin -
1.0ns
tHPmin -
1.0ns
Data hold from DQS to earliest DQ edge
Clock half period
tQH
tHP
ns
ns
tCLmin or
tCHmin
tCLmin or
tCHmin
33
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
1. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
∆tIS
(ps)
0
∆tIH
(ps)
0
(V/ns)
1.0
0.8
+50
+100
+50
+100
0.6
This derating table is used to increase t /t in the case where the input slew rate is below 1.0V/ns.
IS IH
2. Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP.
3. tSAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C).
tSAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85°C).
tSAC is measured in the device with half driver strength and under the AC output load condition (Fig.2 in next Page).
4. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
5. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
∆tDS
(ps)
0
∆tDH
(ps)
0
(V/ns)
1.0
0.8
+75
+150
+75
+150
0.6
This derating table is used to increase t /t in the case where the I/O slew rate is below 1.0V/ns.
DS DH
6. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
∆tDS
(ps)
0
∆tDH
(ps)
0
(ns/V)
0
±0.25
±0.5
+50
+100
+50
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall
Rate =-0.25ns/V.
34
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
AC Operating Test Conditions(VDD = 1.7V - 1.95V, TA = -25 to 85°C)
Parameter
AC input levels (Vih/Vil)
Value
Unit
0.8 x VDDQ / 0.2 x VDDQ
0.5 x VDDQ
1.0
V
V
Input timing measurement reference level
Input signal minimum slew rate
V/ns
V
Output timing measurement reference level
Output load condition
0.5 x VDDQ
See Fig. 2
1.8V
Vtt=0.5 x VDDQ
13.9KΩ
VOH (DC) = 0.9 x VDDQ, IOH = -0.1mA
VOL (DC) = 0.1 x VDDQ, IOL = 0.1mA
30pF
Output
50Ω
10.6KΩ
Output
Z0=50Ω
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
CIN1
1.5
3.0
pF
Input capacitance( CK, CK )
CIN2
COUT
CIN3
1.5
3.0
3.0
3.0
5.0
5.0
pF
pF
pF
Data & DQS input/output capacitance
Input capacitance(DM)
35
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Basic Timing (Setup, Hold and Access Time @BL=4, CL=3)
tCH tCL
tCK
tCH tCL
tCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CK
CK
HIGH
CKE
CS
tIS
tIH
RAS
CAS
BA0, BA1
BAa
BAa
BAb
Ra
Ra
A10/AP
ADDR
(A0~An)
Ca
Cb
WE
tDQSS tDSC
tDQSL
tRPS
Hi-Z
tRPRE
tWPST
DQS
tDQSH
tDQSQ
tWPRES
HtiH-ZZQ
tDS tDH
tSAC
Qa0
Qa1
Qa2
Qa3
Db0 Db1 Db2 Db3
DQ
DM
ACTIVE
READ
WRITE
COMMAND
: Don’t care
36
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Multi Bank Interleaving READ (@BL=4, CL=3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CK
CK
CKE
HIGH
CS
RAS
CAS
BAa
BAb
BAa
BAb
BA0,BA1
A10/AP
Ra
Ra
Rb
Rb
ADDR
(A0~An)
Ca
Cb
WE
tRRD
tCCD
DQS
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
DQ
DM
tRCD
ACTIVE
ACTIVE
READ
READ
COMMAND
: Don’t care
37
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Multi Bank Interleaving WRITE (@BL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CK
CK
CKE
HIGH
CS
RAS
CAS
BAa
BAb
BAa
BAb
BA0,BA1
A10/AP
Ra
Ra
Ra
Ca
ADDR
(A0~An)
Rb
Cb
WE
tRRD
tCCD
DQS
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
DQ
DM
tRCD
ACTIVE
ACTIVE
WRITE
WRITE
COMMAND
: Don’t care
38
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Read with Auto Precharge (@BL=8)
0
1
2
3
4
5
6
7
8
9
10
CK
CK
CKE
CS
HIGH
RAS
CAS
BA0,BA1
BAa
BAb
A10/AP
Ra
Cb
ADDR
(A0~An)
Ca
WE
Auto precharge start
tRP
Note 1
DQS
(CL=3)
DQ
(CL=3)
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
DM
COMMAND
READ
ACTIVE
: Don’t care
Note: The row active command of the precharge bank can be issued after tRP from this point
The new read/write command of another activated bank can be issued from this point
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
39
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Write with Auto Precharge (@BL=8)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CK
CK
CKE
HIGH
CS
RAS
CAS
BAa
BAb
BA0,BA1
A10/AP
Ra
Cb
ADDR
(A0~An)
Ca
WE
Auto precharge start
tWR
tRP
Note 1
DQS
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
DQ
DM
WRITE
ACTIVE
COMMAND
: Don’t care
Note: 1. The row active command of the precharge bank can be issued after tRP from this point
The new read/write command of another activated bank can be issued from this point
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
40
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Write followed by Precharge (@BL=4)
0
1
2
3
4
5
6
7
8
9
10
CK
CK
CKE
CS
HIGH
RAS
CAS
BA0,BA1
BAa
BAa
A10/AP
ADDR
(A0~An)
Ca
WE
tWR
DQS
DQ
Da0 Da1 Da2 Da3
DM
PRE
CHARGE
COMMAND
WRITE
: Don’t care
41
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Write Interrupted by Precharge & DM (@BL=8)
0
1
2
3
4
5
6
7
8
9
10
CK
CK
CKE
CS
HIGH
RAS
CAS
BA0,BA1
BAa
BAa
BAb
BAc
A10/AP
ADDR
(A0~An)
Ca
Cb
Cc
WE
DQS
DQ
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
Db0 Db1 Dc0 Dc1 Dc2 Dc3
DM
tWR
tCCD
PRE
CHARGE
COMMAND
WRITE
WRITE
WRITE
: Don’t care
42
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Write Interrupted by a Read (@BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
CK
CK
CKE
CS
HIGH
RAS
CAS
BA0,BA1
BAa
BAb
A10/AP
ADDR
(A0~An)
Ca
Cb
WE
DQS
DQ
Da0 Da1 Da2 Da3 Da4 Da5
Qb0 Qb1 Qb2 Qb3
Masked by DM
DM
tCDLR
COMMAND
WRITE
READ
: Don’t care
43
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Read Interrupted by Precharge (@BL=8)
0
1
2
3
4
5
6
7
8
9
10
CK
CK
CKE
CS
HIGH
RAS
CAS
BA0,BA1
BAa
BAa
A10/AP
ADDR
(A0~An)
Ca
WE
DQS(CL=3)
2 tCK Valid
4
DQ(CL=3)
DM
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5
PRE
CHARGE
COMMAND
READ
: Don’t care
44
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Read Interrupted by a Write & Burst Stop (@BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
CK
CK
CKE
CS
HIGH
RAS
CAS
BA0,BA1
BAa
BAb
A10/AP
ADDR
(A0~An)
Ca
Cb
WE
DQS
DQ
Qa0 Qa1
Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7
DM
Burst
Stop
COMMAND
READ
WRITE
: Don’t care
45
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Read Interrupted by a Read (@BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
CK
CK
CKE
CS
HIGH
RAS
CAS
BA0,BA1
BAa
BAb
A10/AP
ADDR
(A0~An)
Ca
Cb
WE
DQS
DQ
Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7
DM
tCCD
READ
COMMAND
READ
: Don’t care
46
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
DM Function (@BL=8) only for write
0
1
2
3
4
5
6
7
8
9
10
CK
CK
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
A10/AP
ADDR
(A0~An)
Ca
WE
DQS
DQ
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
DM
COMMAND
WRITE
: Don’t care
47
March 2004
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Mode Register Set
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CK
CK
CKE
CS
tCK
RAS
CAS
WE
BA0,BA1
A10/AP
ADDRESS KEY
ADDR
(A0~An)
DM
tRP
4 Clock
High-Z
High-Z
DQ
DQS
Precharge
Command
All Bank
Mode Resister Set
Command
Any
Command
: Don’t care
Note : Power & Clock must be stable for 200us before precharge all bankes
48
March 2004
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