K4X56323PI-7EC6 [SAMSUNG]
DDR DRAM, 8MX32, 5.5ns, CMOS, PBGA90;
| 型号： | K4X56323PI-7EC6 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 8MX32, 5.5ns, CMOS, PBGA90 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总20页 (文件大小：564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
8M x32 Mobile DDR SDRAM
1. FEATURES
• VDD/VDDQ = 1.8V/1.8V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• MRS cycle with address key programs
- CAS Latency ( 2, 3 )
- Burst Length ( 2, 4, 8, 16 )
- Burst Type (Sequential & Interleave)
• EMRS cycle with address key programs
- Partial Array Self Refresh ( Full, 1/2, 1/4 Array )
- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )
• Internal Temperature Compensated Self Refresh
• Deep Power Down Mode
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• DM0 - DM3 for write masking only.
• Auto refresh duty cycle
- 15.6us for -25 to 85 °C
2. Operating Frequency
DDR333
DDR266
83Mhz
Speed @CL21)
83Mhz
Speed @CL31)
166Mhz
133Mhz
NOTE:
1) CAS Latency
3. Address configuration
Organization
Bank Address
Row Address
Column Address
8M x 32
BA0,BA1
A0 - A11
A0 - A8
- DM is internally loaded to match DQ and DQS identically.
4. Ordering Information
Part No.
Max Freq.
Interface
LVCMOS
Package
K4X56323PI-7(8)E/GC6
K4X56323PI-7(8)E/GC3
166MHz(CL=3),83MHz(CL=2)
133MHz(CL=3),83MHz(CL=2)
90FBGA
Pb (Pb Free)
- 7(8)E : 90FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25 °C ~ 85 °C)
- 7(8)G : 90FBGA Pb(Pb Free), Low Power, Extended Temperature(-25 °C ~ 85 °C)
- C6/C3 : 166MHz(CL=3) / 133MHz(CL=3)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTH-
ING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY
INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS"
BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in
loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
June 2007
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K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
5. FUNCTIONAL BLOCK DIAGRAM
LWE
LDM
32
CK, CK
Data Input Register
Serial to parallel
Bank Select
64
1Mx64
1Mx64
1Mx64
1Mx64
64
32
X32
DQi
CK, CK
ADD
Column Decoder
Latency & Burst Length
Data Strobe
Programming Register
LWCBR
LCKE
LRAS LCBR
LWE
LCAS
LDM
Timing Register
DM Input Register
CK, CK
CKE
CS
RAS
CAS
WE
DM
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K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
6. Package Dimension and Pin Configuration
< Bottom View*1
>
< Top View*2
>
E1
90Ball(6x15) FBGA
9
8
7
6
5
4
3
2
1
1
2
3
7
VDDQ
DQ17
DQ19
DQ21
DQ23
NC
8
9
A
B
C
D
E
F
A
B
C
D
E
F
VSS
DQ31
DQ29
DQ27
DQ25
DQS3
DM3
CK
VSSQ
DQ30
DQ28
DQ26
DQ24
NC
DQ16
DQ18
DQ20
DQ22
DQS2
DM2
CAS
BA0
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CKE
A9
VSSQ
VDDQ
VSSQ
VDDQ
VSS
G
H
J
G
H
J
CK
WE
RAS
BA1
A1
A11
NC
CS
A6
A7
A8
A10/AP
A2
A0
K
L
K
L
A4
DM1
DQS1
DQ9
DQ11
DQ13
DQ15
A5
DM0
DQS0
DQ6
DQ4
DQ2
DQ0
A3
VSSQ
VDDQ
VSSQ
VDDQ
VSS
DQ8
DQ10
DQ12
DQ14
VSSQ
DQ7
DQ5
DQ3
DQ1
VDDQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
M
N
P
R
M
N
P
R
E
*2: Top View
Ball Name
CK, CK
CS
Ball Function
System Differential Clock
Chip Select
CKE
Clock Enable
A
A0 ~ A11
BA0 ~ BA1
RAS
Address
A1
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
z
b
*1: Bottom View
CAS
< Top View*2
>
WE
DM0~3
DQS0~3
DQ0 ~ 31
VDD/VSS
VDDQ/VSSQ
Data Input Mask
Data Strobe
#A1 Ball Origin Indicator
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
[Unit::mm]
Symbol
Min
Typ
-
Max
1.00
-
A
A1
E
-
0.25
-
7.90
8.00
6.40
13.00
11.20
0.80
0.50
-
8.10
-
E1
D
-
12.90
13.10
-
D1
e
-
-
0.45
-
-
b
0.55
0.10
z
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K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
7. Input/Output Function Description
Symbol
Type
Description
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the cross-
ing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK.
CK, CK
Input
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buff-
ers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any banks). CKE is synchronous for all
functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and
CKE , are disabled during power-down and self refresh mode which are contrived for low standby power con-
sumption.
CKE
Input
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder.
All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems
with multiple banks. CS is considered part of the command code.
CS
Input
Input
RAS, CAS, WE
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH
along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include
dummy loading internally, to match the DQ and DQS loading. For the x32, DM0 corresponds to the data on
DQ0-DQ7 ; DM1 corresponds to the data on DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, DM3
corresponds to the data on DQ24-DQ31
DM0,DM1,
DM2,DM3
Input
Input
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE com-
mand is being applied.
BA0, BA1
Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRE-
CHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective
bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one
bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1
determines which mode register( mode register or extended mode register ) is loaded during the MODE REG-
ISTER SET command.
A [n : 0]
Input
DQ
I/O
I/O
-
Data Input/Output : Data bus
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data.
it is used to fetch write data. For the x32, DQS0 corresponds to the data on DQ0-DQ7 ; DQS1 corresponds to
the data on DQ8-DQ15,DQS2 corresponds to the data on DQ16-DQ23, DQS3 corresponds to the data on
DQ24-DQ31
DQS0,DQS1,
DQS2,DQS3
NC
No Connect : No internal electrical connection is present.
VDDQ
VSSQ
VDD
Supply DQ Power Supply : 1.7V to 1.95V
Supply DQ Ground.
Supply Power Supply : 1.7V to 1.95V
Supply Ground.
VSS
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K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
8. Functional Description
Figure 1. State diagram
DEEP
POWER
DOWN
CKEH
POWER
ON
POWER
APPLIED
PARTIAL
SELF
REFRESH
SELF
REFRESH
DEEP
POWER
DOWN
PRECHARGE
ALL BANKS
REFS
REFSX
REFA
IDLE
ALL BANKS
PRECHARGED
MRS
AUTO
REFRESH
EMRS
MRS
CKEL
CKEH
ACT
POWER
DOWN
CKEH
POWER
DOWN
ROW
BURST STOP
ACTIVE
CKEL
WRITE
READ
WRITEA
READA
READ
WRITE
READ
WRITEA
READA
READA
PRE
PRE
WRITEA
READA
PRE
PRE
PRECHARGE
PREALL
Automatic Sequence
Command Sequence
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K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
9. Mode Register Definition
9.1. Mode Register Set(MRS)
The mode register is designed to support the various operating modes of DDR SDRAM. It includes Cas latency, addressing mode, burst
length, test mode and vendor specific options to make DDR SDRAM useful for variety of applications. The default value of the mode register
is not defined, therefore the mode register must be written in the power up sequence of DDR SDRAM. The mode register is written by assert-
ing low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register).
The states of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the mode register.
Two clock cycles are required to complete the write operation in the mode register. Even if the power-up sequence is finished and some read
or write operation is executed afterward, the mode register contents can be changed with the same command and two clock cycles. This com-
mand must be issued only when all banks are in the idle state. If mode register is changed, extended mode register automatically is reset and
come into default state. So extended mode register must be set again. The mode register is divided into various fields depending on function-
ality. The burst length uses A0 ~ A2, addressing mode uses A3, Cas latency(read latency from column address) uses A4 ~ A6, A7 ~ A11 is
used for test mode. BA0 and BA1 must be set to low for proper MRS operation.
Figure 2. Mode Register Set
Address Bus
BA1
BA0
A11 ~ A10/AP
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
0
0
RFU1)
0
0
0
CAS Latency
Burst Length
Mode Register
A3
Burst Type
Sequential
Interleave
0
1
A6
0
A5
0
A4
0
CAS Latency
Reserved
Reserved
2
A2
0
A1
0
A0
0
Burst Type
Reserved
0
0
1
0
0
1
2
0
1
0
0
1
0
4
0
1
1
3
0
1
1
8
1
0
0
Reserved
Reserved
Reserved
Reserved
1
0
0
16
1
0
1
1
0
1
Reserved
Reserved
Reserved
1
1
0
1
1
0
1
1
1
1
1
1
NOTE :
1) RFU(Reserved for future use) should stay "0" during MRS cycle
June 2007
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K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
Table 1. Burst address ordering for burst length
Sequential Mode
Starting
Burst
Address
Interleave Mode
Length
(A3, A2, A1, A0)
xxx0
0, 1
0, 1
2
xxx1
1, 0
1, 0
xx00
0, 1, 2, 3
0, 1, 2, 3
xx01
1, 2, 3, 0
1, 0, 3, 2
4
xx10
2, 3, 0, 1
2, 3, 0, 1
xx11
x000
x001
x010
3, 0, 1, 2
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
x011
8
x100
x101
x110
x111
0000
0001
0010
0011
0100
0101
0110
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2
4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3
5, 6, 7,8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4
6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5
7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6
8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7
9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7, 8
10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,12
14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15
1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11,10,13,12,15,14
2, 3, 0, 1, 6, 7, 4, 5,10,11, 8, 9, 14,15,12,13
3, 2, 1, 0, 7, 6, 5, 4,11,10, 9, 8, 15,14,13,12
4, 5, 6, 7, 0, 1, 2, 3,12,13,14,15, 8, 9, 10,11
5, 4, 7, 6, 1, 0, 3, 2,13,12,15,14, 9, 8,11,10
6, 7, 4, 5, 2, 3, 0, 1,14,15,12,13,10,11, 8, 9
7, 6, 5, 4, 3, 2, 1, 0, 15,14,13,12,11,10, 9, 8
8, 9,10,11,12,13,14,15, 0, 1, 2, 3, 4, 5, 6, 7
9, 8, 11,10,13,12,15,14,1, 0, 3, 2, 5, 4, 7, 6
10,11, 8, 9, 14,15,12,13, 2, 3, 0, 1, 6, 7, 4, 5
11,10, 9, 8, 15,14,13,12, 3, 2, 1, 0, 7, 6, 5, 4
12,13,14,15, 8, 9, 10,11, 4, 5, 6, 7, 0, 1, 2, 3
13,12,15,14, 9, 8,11,10, 5, 4, 7, 6, 1, 0, 3, 2
14,15,12,13,10,11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1
15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
0111
16
1000
1001
1010
1011
1100
1101
1110
1111
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K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
9.2. Extended Mode Register Set(EMRS)
The extended mode register is designed to support partial array self refresh or driver strength control. EMRS cycle is not mandatory and the
EMRS command needs to be issued only when either PASR or DS is used. The default state without EMRS command issued is half driver
strength, and Full array refreshed. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA1 ,low on
BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of
address pins A0 ~ A11 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. Two clock cycles are
required to complete the write operation in the extended mode register. Even if the power-up sequence is finished and some read or write
operations is executed afterward, the mode register contents can be changed with the same command and two clock cycles. But this com-
mand must be issued only when all banks are in the idle state. A0 - A2 are used for partial array self refresh and A5 - A6 are used for driver
strength control. "High" on BA1 and"Low" on BA0 are used for EMRS. All the other address pins except A0,A1,A2,A5,A6, BA1, BA0 must be
set to low for proper EMRS operation. Refer to the table for specific codes.
Figure 3. Extended Mode Register Set
Address Bus
A11 ~ A10/AP
BA1
BA0
A9
A8
A7
0
A6
A5
A4
A3
A2
A1
A0
RFU1)
0
0
DS
RFU1)
PASR
Mode Register
1
0
DS
PASR
A6
0
A5
0
Driver Strength
A1
0
A2
A0
0
Refreshed Area
Full Array
1/2 Array
Full
1/2
1/4
1/8
0
0
0
0
1
1
1
1
0
1
0
1
1
0
1/4 Array
1
0
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
1
1
0
1
1
NOTE :
1) RFU(Reserved for future use) should stay "0" during EMRS cycle
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K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
9.3. Internal Temperature Compensated Self Refresh (TCSR)
1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the self
refresh cycle automatically according to the two temperature ranges ; 45 °C and 85 °C.
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
Self Refresh Current (IDD6)
- E
1/2 Array
160
- G
1/2 Array
135
Temperature Range
Unit
Full Array
200
1/4 Array
140
Full Array
150
1/4 Array
130
45 °C1)
85 °C
uA
450
300
250
300
250
225
NOTE :
1) It has +/- 5 °C tolerance.
9.4. Partial Array Self Refresh (PASR)
1. In order to save power consumption, Mobile DDR SDRAM includes PASR option.
2. Mobile DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, 1/2 Array, 1/4 Array.
Figure 4. EMRS code and TCSR , PASR
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
- 1/4 Array
- Full Array
- 1/2 Array
Partial Self Refresh Area
June 2007
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K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
10. Absolute maximum ratings
Parameter
Symbol
Value
-0.5 ~ 2.7
-0.5 ~ 2.7
-0.5 ~ 2.7
-55 ~ +150
1.0
Unit
V
Voltage on any pin relative to VSS
VIN, VOUT
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Storage temperature
VDD
VDDQ
TSTG
PD
V
V
°C
W
Power dissipation
IOS
Short circuit current
50
mA
NOTE :
1) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
2) Functional operation should be restricted to recommend operation condition.
3) Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
11. DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, Tc = -25°C to 85°C)
Parameter
Supply voltage(for device with a nominal VDD of 1.8V)
I/O Supply voltage
Symbol
VDD
Min
Max
Unit
V
Note
1.7
1.95
1
VDDQ
VIH(DC)
VIL(DC)
VOH(DC)
VOL(DC)
II
1.7
1.95
V
1
Input logic high voltage
0.7 x VDDQ
VDDQ+0.3
V
2
Input logic low voltage
-0.3
0.3 x VDDQ
V
2
IOH = -0.1mA
IOL = 0.1mA
Output logic high voltage
Output logic low voltage
0.9 x VDDQ
-
V
-
0.1 x VDDQ
V
Input leakage current
-2
-5
2
5
uA
uA
Output leakage current
IOZ
NOTE :
1) Under all conditions, VDDQ must be less than or equal to VDD.
2) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.
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K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
12. DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C)
Parameter
Symbol
Test Condition
DDR333 DDR266 Unit Note
Operating Current
(One Bank Active)
tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands;
address inputs are SWITCHING; data bus inputs are STABLE
IDD0
60
55
mA
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
0.3
0.3
IDD2P
Precharge Standby Current
in power-down mode
mA
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD2PS
IDD2N
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
15
8
12
8
Precharge Standby Current
in non power-down mode
mA
mA
mA
mA
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD2NS
IDD3P
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
5
2
Active Standby Current
in power-down mode
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3PS
IDD3N
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
25
20
25
20
Active Standby Current
in non power-down mode
(One Bank Active)
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3NS
IDD4R
one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I
=0 mA
OUT
140
120
145
110
90
address inputs are SWITCHING; 50% data change each burst transfer
Operating Current
(Burst Mode)
one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
IDD4W
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
130
Refresh Current
IDD5
IDD6
IDD8
mA
1)
85
°C
Parameter
CKE is LOW; t CK = t CKmin ;
45
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
Full Array
200
160
140
150
135
130
450
300
250
300
250
225
1/2 Array
1/4 Array
Full Array
1/2 Array
1/4 Array
- E
- G
Self Refresh Current
uA
uA
Deep Power Down Current
Deep Power Down Mode Current
10
2
NOTE :
1) It has +/- 5°C tolerance.
2) DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.
Please contact Samsung for more information.
3) IDD specifications are tested after the device is properly intialized.
4) Input slew rate is 1V/ns.
5) Definitions for IDD: LOW is defined as V IN ≤ 0.1 * VDDQ ;
HIGH is defined as V IN ≥ 0.9 * VDDQ ;
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
June 2007
- 14 -
K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
13. AC Operating Conditions & Timming Specification
Parameter/Condition
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
Input Crossing Point Voltage, CK and CK inputs
Symbol
VIH(AC)
VIL(AC)
VIX(AC)
Min
Max
Unit
V
Note
0.8 x VDDQ
-0.3
VDDQ+0.3
0.2 x VDDQ
0.6 x VDDQ
1
1
2
V
0.4 x VDDQ
V
NOTE :
1) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.
2) The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
June 2007
- 15 -
K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
14. AC Timming Parameters & Specifications
DDR333
DDR266
Parameter
Symbol
Unit
Note
Min
Max
Min
12.0
7.5
Max
CL=2
CL=3
12.0
Clock cycle time
tCK
ns
6
Row cycle time
Row active time
RAS to CAS delay
tRC
tRAS
tRCD
tRP
60
67.5
45
ns
ns
ns
ns
ns
ns
-
42
70,000
70,000
18
22.5
22.5
15
Row precharge time
18
Row active to Row active delay
Write recovery time
tRRD
tWR
12
12
15
Last data in to Active delay
Last data in to Read command
tDAL
tCDLR
2tCK+tRP
2tCK+tRP
1
2
3
1
1
tCK
1
Col. address to Col. address delay
tCCD
tCK
Clock high level width
Clock low level width
tCH
tCL
0.45
0.45
2
0.55
0.55
8
0.45
0.45
2
0.55
0.55
8
tCK
tCK
CL=2
CL=3
CL=2
CL=3
DQ Output data access time
from CK/CK
tAC
ns
2
5.5
8
2
6
2
2
8
DQS Output data access time
from CK/CK
tDQSCK
tDQSQ
tRPRE
ns
ns
2
5.5
0.5
1.1
1.1
0.6
1.25
2
6
Data strobe edge to ouput data edge
Read Preamble
0.6
1.1
1.1
0.6
1.25
CL=2
CL=3
0.5
0.9
0.4
0.75
0
0.5
0.9
0.4
0.75
0
tCK
Read Postamble
tRPST
tDQSS
tWPRES
tWPREH
tDQSH
tDQSL
tDSS
tCK
tCK
ns
CK to valid DQS-in
DQS-in setup time
4
DQS-in hold time
0.25
0.4
0.4
0.2
0.2
0.9
1.1
1.1
2.2
0.6
0.25
0.4
0.4
0.2
0.2
0.9
1.3
1.3
2.6
0.8
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS-in high level width
0.6
0.6
0.6
0.6
DQS-in low level width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS-in cycle time
tDSH
tDSC
1.1
1.1
Address and Control Input setup time
Address and Control Input hold time
Address & Control input pulse width
DQ & DM setup time to DQS
tIS
1
1
tIH
ns
tIPW
1
tDS
ns
ns
5,6
DQ & DM hold time to DQS
DQ & DM input pulse width
tDH
0.6
0.8
5,6
tDIPW
tLZ
1.2
1.0
1.8
1.0
ns
ns
DQ & DQS low-impedence time from CK/CK
DQ & DQS high-impedence time from CK/CK
DQS write postamble time
tHZ
5.5
0.6
6.0
0.6
ns
tWPST
tWPRE
tREF
0.4
0.4
tCK
tCK
ms
tCK
tCK
DQS write preamble time
0.25
0.25
Refresh interval time
64
64
Mode register set cycle time
Power down exit time
tMRD
tPDEX
2
1
2
1
June 2007
- 16 -
K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
DDR333
DDR266
Parameter
Symbol
Unit
Note
Min
2
Max
Min
2
Max
CKE min. pulse width(high and low pulse width)
Auto refresh cycle time
tCKE
tRFC
tXSR
tCK
ns
72
80
7
Exit self refresh to active command
120
120
ns
tHPmin -
tQHS
tHPmin -
tQHS
Data hold from DQS to earliest DQ edge
Data hold skew factor
tQH
tQHS
tHP
ns
ns
ns
0.65
0.75
tCLmin or
tCHmin
tCLmin or
tCHmin
Clock half period
NOTE :
1) Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
∆tIS
∆tIH
(V/ns)
1.0
(ps)
0
(ps)
0
0.8
+50
+100
+50
+100
0.6
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 1.0V/ns.
2) Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP.
3) tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C).
tAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85°C).
tAC is measured in the device with half driver strength and under the AC output load condition (Fig.6 in next Page).
4) The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
5) I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
∆tIS
(ps)
0
∆tIH
(ps)
0
(V/ns)
1.0
0.8
+75
+150
+75
+150
0.6
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 1.0V/ns.
6) I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Data Rise/Fall Rate
∆tIS
(ps)
0
∆tIH
(ps)
0
(ns/V)
0
±0.25
±0.5
+50
+100
+50
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as
1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall Rate =-0.25ns/V.
7) Maximum burst refresh cycle : 8
June 2007
- 17 -
K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
15. AC Operating Test Conditions (VDD = 1.7V to 1.95V, Tc = -25 to 85°C)
Parameter
Value
0.8 x VDDQ / 0.2 x VDDQ
0.5 x VDDQ
Unit
V
AC input levels (Vih/Vil)
Input timing measurement reference level
Input signal minimum slew rate
Output timing measurement reference level
Output load condition
V
1.0
V/ns
V
0.5 x VDDQ
See Figure 6
1.8V
13.9KΩ
VOH (DC) = 0.9 x VDDQ , IOH = -0.1mA
VOL (DC) = 0.1 x VDDQ , IOL = 0.1mA
Output
20pF
10.6KΩ
Figure 5. DC Output Load Circuit
Vtt=0.5 x VDDQ
50Ω
Output
Z0=50Ω
20pF
Figure 6. AC Output Load Circuit
16. Input/Output Capacitance(VDD=1.8, VDDQ=1.8V, T = 25°C, f=1MHz)
C
Parameter
Symbol
Min
Max
Unit
Input capacitance
(A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
CIN1
1.5
3.0
pF
Input capacitance( CK, CK )
CIN2
COUT
CIN3
1.5
2.0
2.0
3.5
4.5
4.5
pF
pF
pF
Data & DQS input/output capacitance
Input capacitance(DM)
June 2007
- 18 -
K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
17. AC Overshoot/Undershoot Specification for Address & Control Pins
Parameter
Specification
0.9V
Maximum peak Amplitude allowed for overshoot area
Maximum peak Amplitude allowed for undershoot area
Maximum overshoot area above VDD
0.9V
3V-ns
3V-ns
Maximum undershoot area below VSS
Maximum Amplitude
Overshoot Area
VDD
Volts
(V)
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 7. AC Overshoot and Undershoot Definition for Address and Control Pins
18. AC Overshoot/Undershoot Specification for CLK, DQ, DQS and DM Pins
Parameter
Specification
Maximum peak Amplitude allowed for overshoot area
Maximum peak Amplitude allowed for undershoot area
Maximum overshoot area above VDDQ
0.9V
0.9V
3V-ns
3V-ns
Maximum undershoot area below VSSQ
Maximum Amplitude
Overshoot Area
VDDQ
VSSQ
Volts
(V)
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 8. AC Overshoot and Undershoot Definition for CLK, DQ, DQS and DM Pins
June 2007
- 19 -
K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
19. Command Truth Table
A11,
A9~A0
Command
CKEn-1 CKEn
CS
RAS
CAS
WE
BA0,1 A10/AP
Note
Register
Refresh
Mode Register Set
Auto Refresh
H
H
X
H
L
L
L
L
L
OP CODE
X
1, 2
3
L
L
L
H
Entry
Self
3
L
H
L
H
X
L
H
X
H
H
X
H
3
Refresh
Exit
L
H
H
H
X
X
X
3
Bank Active & Row Addr.
V
V
Row Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Entry
L
H
L
Column
Address
(A0~A8)
4
4
Read &
Column Address
L
L
H
H
L
L
H
L
Column
Address
(A0~A8)
4
Write &
Column Address
H
X
V
H
4, 6
H
L
L
H
X
L
H
L
H
X
H
H
X
H
L
X
L
Deep Power Down
X
Exit
Burst Stop
H
X
L
7
5
Bank Selection
All Banks
V
X
Precharge
H
X
L
L
H
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
L
H
L
Active Power Down
X
X
Exit
X
H
L
Entry
H
Precharge Power Down
H
L
Exit
L
H
H
H
X
DM
No operation (NOP) : Not defined
X
X
8
9
9
H
L
X
H
X
H
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
NOTE :
1) OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2) EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3) Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4) BA0 ~ BA1 : Bank select addresses.
5) If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6) During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7) Burst stop command is valid at every burst length.
8) DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9) This combination is not defined for any function, which means "No Operation(NOP)" in Mobile DDR SDRAM.
June 2007
- 20 -
K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
20. Functional Truth Table
Current State
CS
L
RAS
H
CAS
H
WE
L
Address
Command
Burst Stop
Action
ILLEGAL2)
X
ILLEGAL2)
L
H
L
X
BA, CA, A10
READ/WRITE
Active
L
L
H
H
L
BA, RA
Bank Active, Latch RA
PRECHARGE
STANDBY
ILLEGAL4)
L
L
H
BA, A10
PRE/PREA
Refresh
AUTO-Refresh5)
L
L
L
H
L
X
Mode Register Set5)
NOP
L
L
L
Op-Code, Mode-Add
X
MRS
L
H
H
L
Burst Stop
Begin Read, Latch CA,
Determine Auto-Precharge
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ/READA
Begin Write, Latch CA,
Determine Auto-Precharge
WRITE/WRITEA
ACTIVE
STANDBY
Bank Active/ILLEGAL2)
Precharge/Precharge All
L
L
L
L
H
H
H
L
BA, RA
Active
BA, A10
PRE/PREA
L
L
L
L
L
L
L
H
L
L
X
Refresh
MRS
ILLEGAL
Op-Code, Mode-Add
X
ILLEGAL
H
H
Burst Stop
Terminate Burst
Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge3)
L
H
L
H
BA, CA, A10
READ/READA
L
L
H
L
L
L
BA, CA, A10
BA, RA
BA, A10
X
WRITE/WRITEA
Active
ILLEGAL
READ
Bank Active/ILLEGAL2)
H
H
Terminate Burst, Precharge10)
ILLEGAL
L
L
L
L
L
L
H
L
L
H
L
PRE/PREA
Refresh
L
L
Op-Code, Mode-Add MRS
Burst Stop
ILLEGAL
H
H
L
X
ILLEGAL
Terminate Burst With DM=High,
Latch CA, Begin Read, Determine
Auto-Precharge3)
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ/READA
Terminate Burst, Latch CA,
Begin new Write, Determine Auto-
Precharge3)
WRITE/WRITEA
WRITE
Bank Active/ILLEGAL2)
L
L
L
L
H
H
H
L
BA, RA
Active
Terminate Burst With DM=High,
Precharge10)
BA, A10
PRE/PREA
L
L
L
L
L
L
L
L
L
L
H
L
X
Refresh
ILLEGAL
ILLEGAL
ILLEGAL
6)
Op-Code, Mode-Add
X
MRS
H
H
H
L
H
L
L
Burst Stop
READ/READA
WRITE/WRITEA
Active
H
L
BA, CA, A10
BA, CA, A10
BA, RA
READ with
AUTO
PRECHARGE6)
L
ILLEGAL
6)
H
H
(READA)
BA, A10
L
L
H
L
PRE/PREA
6)
L
L
L
L
L
L
H
L
X
Refresh
MRS
ILLEGAL
ILLEGAL
Op-Code, Mode-Add
June 2007
- 21 -
K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
Current State
CS
L
RAS CAS
WE
L
Address
Command
Burst Stop
READ/READA
Action
H
H
H
L
H
L
X
ILLEGAL
7)
L
H
L
BA, CA, A10
BA, CA, A10
BA, RA
WRITE with
AUTO
RECHARGE7)
L
L
WRITE/WRITEA 7)
L
H
H
L
H
L
Active
7)
(WRITEA)
L
L
BA, A10
X
PRE/PREA
Refresh
7)
L
L
H
L
ILLEGAL
ILLEGAL
L
L
L
Op-Code, Mode-Add MRS
X Burst Stop
ILLEGAL2)
ILLEGAL2)
ILLEGAL2)
L
H
H
L
L
L
H
L
L
X
H
BA, CA, A10
BA, RA
BA, A10
X
READ/WRITE
Active
H
PRECHARGING
(DURING tRP)
NOP4)(Idle after tRP)
ILLEGAL
L
L
L
L
L
L
H
L
L
H
L
PRE/PREA
Refresh
L
L
Op-Code, Mode-Add MRS
ILLEGAL
ILLEGAL2)
ILLEGAL2)
ILLEGAL2)
H
H
L
X
Burst Stop
ROW
ACTIVATING
L
L
L
H
L
L
L
H
H
X
H
L
BA, CA, A10
BA, RA
BA, A10
READ/WRITE
Active
(FROM ROW
ACTIVE TO
tRCD)
ILLEGAL2)
ILLEGAL
ILLEGAL
PRE/PREA
Refresh
L
L
L
L
L
L
L
H
L
L
X
Op-Code, Mode-Add MRS
ILLEGAL2)
H
H
X
Burst Stop
ILLEGAL2)
WRITE
L
L
L
H
H
L
L
L
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
READ
WRITE
RECOVERING
WRITE
Active
ILLEGAL2)
H
H
(DURING tWR
OR tCDLR)
ILLEGAL2)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
PRE/PREA
Refresh
L
L
Op-Code, Mode-Add MRS
H
H
L
H
L
L
X
Burst Stop
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ/WRITE
Active
RE-
FRESHING
H
H
L
L
PRE/PREA
Refresh
L
H
L
L
L
Op-Code, Mode-Add MRS
H
H
L
H
L
L
X
Burst Stop
X
H
BA, CA, A10
BA, RA
BA, A10
READ/WRITE
Active
MODE
REGISTER
SETTING
H
L
L
H
L
PRE/PREA
Refresh
ILLEGAL
L
L
L
L
L
L
H
L
X
ILLEGAL
ILLEGAL
Op-Code, Mode-Add MRS
June 2007
- 22 -
K4X56323PI - 7(8)E/G
Mobile DDR SDRAM
CKE
n-1
CKE
n
Current State
CS
RAS
CAS
WE
Add
Action
L
L
H
H
H
H
H
L
H
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Exit Self-Refresh
Exit Self-Refresh
ILLEGAL
L
L
SELF-
REFRESHING8)
L
L
X
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
X
L
ILLEGAL
L
X
X
X
H
X
X
L
X
X
X
X
X
X
L
NOP (Maintain Self-Refresh)
Exit Power Down(Idle after tPDEX)
NOP (Maintain Power Down)
L
H
L
POWER
DOWN
L
Exit Deep Power Down10)
NOP (Maintain Deep Power Down)
Refer to Function Truth Table
Enter Self-Refresh
L
H
L
DEEP POWER
DOWN
L
H
H
H
H
H
H
H
H
L
H
L
L
H
L
X
H
H
H
H
L
X
H
H
H
L
Enter Power Down
L
Enter Power Down
ALL BANKS
IDLE9)
L
L
Enter Deep Power Down
ILLEGAL
L
L
L
L
L
X
X
X
ILLEGAL
L
L
X
X
ILLEGAL
X
X
X
Refer to Current State=Power Down
(H=High Level, L=Low level, X=Don′t Care)
NOTE :
1) All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2) ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank.
(ILLEGAL = Device operation and/or data integrity are not guaranteed.)
3) Must satisfy bus contention, bus turn around and write recovery requirements.
4) NOP to bank precharging or in idle sate. May precharge bank indicated by BA.
5) ILLEGAL if any bank is not idle.
6) Refer to "Read with Auto Precharge Timing Diagram" for detailed information.
7) Refer to "Write with Auto Precharge Timing Diagram" for detailed information.
8) CKE Low to High transition will re-enable CK, CK and other inputs asynchronously.
A minimum setup time must be satisfied before issuing any command other than EXIT.
9) Power-Down, Self-Refresh and Deep Power Down Mode can be entered only from All Bank Idle state.
10) The Deep Power Down Mode is exited by asserting CKE high and full initialization is required after exiting Deep Power Down Mode.
June 2007
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