K4Y54084UF-JCB30 [SAMSUNG]
Rambus DRAM, 32MX8, CMOS, PBGA104;
| 型号： | K4Y54084UF-JCB30 |
| 厂家： | 
SAMSUNG |
| 描述： | Rambus DRAM, 32MX8, CMOS, PBGA104 动态存储器 内存集成电路 |
| 文件： | 总75页 (文件大小：3449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4Y5416(/08/04)4UF
XDR DRAM
256Mbit XDR DRAM(F-die)
2M x 16(/8/4) bit x 8s Banks
Version 1.0
Jan. 2005
Version 1.0 Jan. 2005
Page-1
K4Y5416(/08/04)4UF
Change History
XDR DRAM
Version 0.1( July 2004) - Preliminary
- First Copy
- Based on the Rambus XDR DRAMTM Datasheet Version 0.81
Version 1.0( Jan. 2005)
- Delete “Preliminary”
- Based on the Rambus XDR DRAMTM Datasheet Version 0.85
Version 1.0 Jan. 2005
Page 0
K4Y5416(/08/04)4UF
XDR DRAM
Overview
The Rambus XDR DRAM device is a general-purpose high-performance memory device suitable for use in a broad range of
applications, including computer memory, graphics, video, and any other application where high bandwidth and low latency are
required.
The 256Mb XDR DRAM device is a CMOS DRAM organized as 16M words by 16bits. The use of Differential Rambus Signaling
Level(DRSL) technology permits 4000/3200/2400 Mb/s transfer rates while using conventional system and board design tech-
nologies. XDR DRAM devices are capable of sustained data transfers up to 8000 MB/s.
XDR DRAM device architecture allows the highest sustained bandwidth for multiple, interleaved randomly addressed memory
transactions. The highly-efficient protocol yields over 95% utilization while allowing fine access granuarity. The device’s eight
banks support up to four interleaved transactions.
Features
♦ Highest pin bandwidth available
- 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling
♦ Bi-directional differential RSL(DRSL)
- Flexible read/write bandwidth allocation
- Minimum pin count
♦ Programmable on-chip termination
- Adaptive impedance matching
- Reduced system cost and routing complexity
♦ Highest sustained bandwidth per DRAM device
- Up to 8000 MB/s sustained data rate
- Eight banks : bank-interleaved transaction at full bandwidth
- Dynamic request scheduling
- Early-read-after-write support for maximum efficiency
- Zero overhead refresh
♦ Low Latency
- 2.0/2.5/3.33ns request packets
- Point-to-point data interconnect for fastest possible flight time
- Support for low-latency, fast-cycle cores
♦ Low Power
- 1.8V VDD
- Programmable small-swing I/O signaling(DRSL)
- Low power PLL/DLL design
- Powerdown self-refresh support
- Per pin I/O powerdown for narrow-width operation
♦ 0.98us refresh intervals(16K/16ms refresh)
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Key Timing Parameters/Part Numbers
a
b
Binc,d
Organization
Part Number
Bandwidth (1/tBIT
)
Latency(tRAC)
2400
3200
3200
4000
2400
3200
3200
4000
2400
3200
3200
4000
36
35
35
28
36
35
35
28
36
35
35
28
A
B
C
C
A
B
C
C
A
B
C
C
K4Y54164UF-JCA2
K4Y54164UF-JCB3
K4Y54164UF-JCC3
K4Y54164UF-JCC4
K4Y54084UF-JCA2
K4Y54084UF-JCB3
K4Y54084UF-JCC3
K4Y54084UF-JCC4
K4Y54044UF-JCA2
K4Y54044UF-JCB3
K4Y54044UF-JCC3
K4Y54044UF-JCC4
16Mx16
32Mx8
64Mx4
a. Data rate measured in Mbit/s per DQ differential pair. See “Timing Conditions” on page 55 and “ Timing Characteristics” on page 58.
Note that tBIT=t
/8
CYCLE
b. Read access time t
(= t
+t
) measured in ns. See “Timing Parameters” on page 59.
RAC
RCD-R CAC
c. Timing parameter bin. See “Timing Parameters” on page 59. This is a measure of the number of interleaved read transactions needed
for maximum efficiency (the value Ceiling(t
d. Bin support is vendor dependent.
/t
). For bin A, t
/t
=4, and for bin B, t
/t
=5.
RC-R RR-D
RC-R RR-D
RC-R RR-D
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets of pins used for
normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins. The “N”
appended to a signal name denotes the complementary signal of a differential pair.
A transaction is a collection of packets needed to complete a memory access. A packet is a set of bit windows on the signals of
a bus. There are two buses that carry packets: the RQ bus and DQ bus. Each packet on the RQ bus uses a set of 2 bit-windows
on each signal, while the DQ bus uses a set of 16 bit-windows on each signal.
In the write transaction shown in Figure 1, a request packet (on the RQ bus) at clock edge T0 contains an activate (ACT) com-
mand. This causes row Ra of bank Ba in the memory component to be loaded into the sense amp array for the bank. A second
request packet at clock edge T1 contains a write (WR) command. This causes the data packet D(a1) at edge T4 to be written to
column Ca1 of the sense amp array for bank Ba. A third request packet at clock edge T3 contains another write (WR) command.
This causes the data packet D(a2) at edge T6 to also be written to column Ca2. A final request packet at clock edge T13 contains
a precharge (PRE) command.
The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD-W , tCC , and
tWRP . In addition, the spacing between the request packets and data packets is constrained by the tCWD parameter. The spacing
of the CFM/CFMN clock edges is constrained by tCYCLE
.
Figure 1 : XDR DRAM Device Write and Read Transactions
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
tCYCLE
ACTWR
WR
a2
PRE
a3
RQ11..0
a0 a1
tWRP
tCC
tCWD
Transaction a: WR
tRCD-W
DQ15..0
D(a1) D(a2)
DQN15..0
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Write Transaction
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
tCYCLE
ACT
RD
a1
RD
a2
PRE
a3
RQ11..0
a0
tRDP
tRCD-R
tCC
DQ15..0
DQN15..0
Q(a1) Q(a2)
a1 = {Ba,Ca1}
tCAC
a0 = {Ba,Ra}
Transaction a: RD
a2 = {Ba,Ca2}
a3 = {Ba}
Read Transaction
The read transaction shows a request packet at clock edge T0 containing an ACT command. This causes row Ra of bank Ba of
the memory component to load into the sense amp array for the bank. A second request packet at clock edge T5 contains a
read (RD) command. This causes the data packet Q(a1) at edge T11 to be read from column Ca1 of the sense amp array for
bank Ba. A third request packet at clock edge T7 contains another RD command. This causes the data packet Q(a2) at edge T13
to also be read from column Ca2. A final request packet at clock edge T10 contains a PRE command.
The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD-R , tCC , and
tRDP . In addition, the spacing between the request and data packets are constrained by the tCAC parameter.
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Pinouts and Definitions
The following table shows the pin assignment of the center-bonded fanout XDR DRAM Package. The mechanical dimensions of
this package are shown on page 71. Note - Pin #1 is at the A1 postion.
Table 1: 104ball XDR DRAM Package(Top View)
16
DQ10
DQN10 DQN0
DQ6 DQ12
DQN6 DQN12
DQ0
SDO
RST
GND
VDD
VDD
GND
VDD
VDD
GND
SCK
CMD
VDD
DQ1
DQN1 DQN11
DQ13 DQ7
DQN13 DQN7
DQ11
15
14
RQ2
RQ1
RQ5
RQ6
RQ7
RQ8
RQ9
13
VREF
12
VDD
GND
GND
VDD
GND
GND
VDD
11
GND
VTERM
VDD
GND
GND
VDD
GND
VTERM
GND
10
9
8
7
6
GND
VDD
GND
VDD
VDD
VDD
GND
VDD
GND
GND
GND
VDD
GND
VDD
5
VTERM
GND
RQ0
GND
SDI
VTERM
GND
VDD
VDD
VDD
J
4
DQ14
DQ4
RQ3
RQ4
RSRV
RSRV
CFMN
CFM
RQ11
RQ10
DQ5
DQ15
3
DQN14 DQN4
DQN5 DQN15
2
1
DQ2
DQN2
A
DQ8
DQN8
B
DQ9
DQN9
K
DQ3
DQN3
L
VDD
D
GND
E
VDD
G
GND
H
Top View
C
F
ROW
COL
Top View
450
SAMSUNG
K4Y54164UF -JCB3
Chip
The pin #1(ROW1, COLA) is located at the A1
position on the top side and the A1 position is
marked by the marker “ ”.
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Pin Description
Table2 summarizes the pin functionality of the XDR DRAM device. The first group of pins provide the necessary supply voltages.
These include VDD and GND for the core and interface logic, VREF for receiving input signals, and VTERM for the driving output
signals.
The next group of pins are used for high bandwidth memory accesses. These include DQ15 ... DQ0 and DQN15 ... DQN0 for
carrying read and write data signals, RQ11 ... RQ0 for carrying request signals, and CFM and CFMN for carrying timing informa-
tion used by the DQ, DQN and RQ signals.
The final set of pins comprise the serial interface that is used for control register accesses. These include RST for initializing the
state of the device, CMD for carrying command signals, SDI and SDO for carrying register read data, and SCK for carrying the
timing information used by the RST, SDI, SDO, and CMD signals.
Table 2 : Pin Description
Signal
VDD
I/O
Type
No. of pins
Description
22a
-
-
-
-
-
Supply voltage for the core and interface logic of the device.
Ground reference for the core and interface logic of the device.
Logic threshold reference voltage for RSL signals.
24a
1
GND
-
-
VREF
VTERM
4a
16
16
12
-
Termination voltage for DRSL signals.
DRSLb
DRSLb
RSLb
DQ15..0
DQN15..0
RQ11..0
I/O
I/O
I
Positive data signals that carry write or read data to and from the device.
Negative data signals that carry write or read data to and from the device.
Request signals that carry control and address information to the device.
Clock from master — Positive interface clock used for receiving RSL signals,
and receiving and transmitting DRSL signals from the Channel.
DIFFCLKb
CFM
I
1
Clock from master — Negative interface clock used for receiving RSL signals,
and receiving and transmitting DRSL signals from the Channel.
DIFFCLKb
RSLb
CFMN
RST
I
I
I
1
1
1
Reset input — This pin is used to initialize the device.
Command input — This pin carries command, address, and control register
write data into the device.
RSLb
CMD
Serial clock input — Clock source used for reading from and writing to the con-
trol registers.
RSLb
RSLb
CMOSb
-
SCK
SDI
I
I
1
1
1
Serial data input — This pin carries control register read data through the
device. This pin is also used to initialize the device.
Serial data output — This pin carries control register read data from the device.
This pin is also used to initialize the device.
SDO
RSRV
O
-
Reserved pins — Follow Rambus XDR system design guidelines for connect-
ing RSRV pins
2
Total pin count per package
104
a. The exact number of VDD/GND/VTERM pins may vary between XDR DRAM vendors.
b. All DQ and CFM signals are high-true; low voltage is logic 0 and high voltage is logic 1.
All DQN, CFMN, RQ, RSL, and CMOS signals are low-true; high voltage is logic 0 and low voltage is logic 1.
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Block Diagram
A block diagram of the XDR DRAM device is shown in Figure2. It shows all interface pins and major internal blocks.
The CFM and CFMN clock signals are received and used by the clock generation logic to produce three virtual clock signals :
1/tCYCLE, 2/tCYCLE, and 16/tCC. The frequency of these signals are 1x, 2x, and 8x that of the CFM and CFMN signals. These
virtual signals show the effective data rate of the logic blocks to which they connect; they are not necessarily present in the actual
memory component.
The RQ11 ... RQ0 pins receive the request packet. Two 12-bit words are received in one tCYCLE interval. This is indicated by the
2/tCYCLE clocking signal connected to the 1:2 Demux Block that assembles the 24-bit request packet. These 24bits are loaded
into a register(clocked by the 1/tCYCLE clocking signal) and decoded by the Decode Block. The VREF pin supplies a reference
voltage used by the RQ receivers.
Three sets of control signals are produced by the Decode Block. These include the bank(BA) and row(R) addresses for an acti-
vate(ACT) command, the bank(BR) and row(REFr) addresses for a refresh activate(REFA) command, the bank(BP) address for
a precharge(PRE) command, the bank(BR) adddress for a refresh precharge(REFP) command, and the bank(BC) and column(C
and SC) addresses for a read(RD) or write(WR or WRM) command. In addition, a mask(M) is used for a masked write(WRM)
command.
These commands can all be optionally delayed in increments of tCYCLE under control of delay fields in the request. The control
signals of the commands are loaded into registers and presented to the memory core. These registers are clocked at maximum
rates determined by core timing parameters, in this case 1/tRR, 1/tPP, and 1/tCC(1/4, 1/4, and 1/2 the frequency of CFM in the -
3200 component). These registers may be loaded at any tCYCLE rising edge. Once loaded, they should not be changed until a
tRR, tPP, or tCC time later because timing paths of the memory core need time to settle.
A bank address is decoded for an ACT command. The indicated row of the selected bank is sensed and placed into the associ-
ated sense amp array for the bank. Sensing a row is also referred to as “Opening a page”for the bank.
Another bank address is decoded for a PRE command. The indicated bank and associated sense amp array are precharged to
a state in which a subsequent ACT command can be applied. Precharging a bank is also called “closing the page” for the bank.
After a bank is given an ACT command and before it is given a PRE command, it may receive read(RD) and write(WR) column
commands. These commands permit the data in the bank’s associated sense amp array to be accessed.
For a WR command, the bank address is decoded. The indicated column of the associated sense amp array of the selected bank
is written with the data received from the DQ15 ... DQ0 pins.
The bank address is decoded for a RD command. The indicated column of the selected bank’s associated sense amp array is
read. The data is transmitted onto the DQ15 ... DQ0 pins.
The DQ15 ... DQ0 pins receive the write data packet(D) for a write transaction. 16 sixteen-bit words are received in one tCC in-
terval. This is indicated by the 16/tCC clocking signal connected to the 1:16 Demux Block that assembles the 16x16-bit write data
packet. The write data is then driven to the selected Sense Amp Array Bank.
16 sixteen-bit words are accessed in the selected Sense Amp Array Bank for a read transaction. The DQ15 ... DQ0 pins transmit
the read data packet(Q) in one tCC interval. This is indicated by the 16/tCC clocking signal connected to the 16:1 Mux Block. The
VTERM pin supplies a termination voltage for the DQ pins.
The RST, SCK, and CMD pins connect to the Control Register block. These pins supply the data, address and conrol needed to
write the control registers. The read data for these registers is accessed through the SDO/SDI pins. These pins are also used to
initialize the device.
The control registers are used to transition between power modes, and are also used for calibrating the high speed transmit and
receive circuits of the device. The control registers also supply bank(REFB) and row(REFr) address for refresh operations.
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Figure 2 : 256Mb (8x2Mx16) XDR DRAM Block Diagram
RQ11..0
12
VREF
1
RST,SCK,CMD,SDI SDO
CFM CFMN
4
1
2/t
CYCLE
12
1:2 Demux
reg
1/t
CYCLE
Control Registers
2/t
CYCLE
12
12
16/ t
CC
1/t
CYCLE
12
Power Mode Logic
Calibration Logic
Refresh Logic
Decode
PRE logic
3
WIDTH
REFB,REFr
COL logic
ACT logic
11
Initialization Logic
7
6+4
3
3
RD,WR
delay
{0..1}*tCYCLE
PRE delay
{0..3}*tCYCLE
ACT delay
{0..1}*tCYCLE
1/t
RR
Bank Array
3
2
1
1
6
11
ACT
16x16*2 *2
3
BA,BR,REFB
R,REFr
ACT
ROW
11
ROW
1/t
PP
3
2
1
1
PRE
Bank 0
3
BP,BR,REFB
3
PRE
(2 - 1)
Bank
6
6
16x16*2
16x16*2
1/t
CC
3
2
1
1
Sense Amp Array
R/W
COL
6
16x16*2
BC
C
R/W
COL
3
Sense Amp 0
6
3
Sense Amp(2 - 1)
SC
M
4
16x16
16x16
16x16
8
S[15:0][15:0]
16x16
WIDTH
Byte Mask (WR)
Dynamic Width Demux (WR)
Dynamic Width Mux (RD)
16x16. . .
16x16
D[15:0][15:0]
Q[15:0][15:0]
16
. . .
16
16/t
. . .
. . .
1:16 Demux
16
16:1 Mux
16
16/t
CC
CC
termination
16
DQ15..0
16
2
VTERM
DQN15..0
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Request Packets
A request packet carries address and control information to the memory device. This section contains tables and diagrams for
packet formats, field encodings and packet interactions.
Request Packet Formats
There are five types of request packets:
1. ROWA — specifies an ACT command
2. COL — specifies RD and WR commands
3. COLM — specifies a WRM command
4. ROWP — specifies PRE and REF commands
5. COLX — specifies the remaining commands
Table 3 describes fields within different request packet types. Various request packet type formats are illustrated in Figure3.
Each packet type consists of 24 bits sampled on the RQ11..0 pins on two successive edges of the CFM/CFMN clock. The
request packet formats are distinguished by the OP3..0 field. This field also specifies the operation code of the desired com-
mand.
In the ROWA packet, a bank address (BA), row address (R), and command delay (DELA) are specified for the activate (ACT)
command.
In the COL packet, a bank address (BC), column address (C), sub-column address (SC), command delay (DELC), and sub-
opcode (WRX) are specified for the read (RD) and write (WR) commands.
In the COLM packet, a bank address (BC), column address (C), sub-column address (SC), and mask field (M) are specified for
the masked write (WRM) command.
In the ROWP packet, two independent commands may be specified. A bank address (BP) and sub-opcode (POP) are specified
for the precharge (PRE) commands. An address field (RA) and sub-opcode (ROP) are specified for the refresh (REF) com-
mands.
In the COLX packet, a sub-operation code field (XOP) is specified for the remaining commands.
Table 3 : Request Field Description
Field
OP3..0
Packet Types
Description
4-bit operation code that specifies packet format.
(Encoded commands are in Table 4 on page 10.)
ROWA/ROWP
/COL/COLM/COLX
Delay the associated row activate command by 0 or 1 tCYCLE
.
DELA
BA2..0
R10..0
WRX
ROWA
ROWA
3-bit bank address for row activate command.
11-bit row address for row activate command.
Specifies RD (=0) or WR (=1) command.
ROWA
COL
Delay the column read or write command by 0 or 1 tCYCLE
.
DELC
BC2..0
C9..4
COL
COL/COLM
COL/COLM
COL/COLM
COLM
3-bit bank address for column read or write command.
6-bit column address for column read or write command.
SC3..0
M7..0
4-bit sub-column address for dynamic width (see “Dynamic Width Control” on page 46).
8-bit mask for masked-write command WRM.
3-bit operation code that specifies row precharge command with a delay of 0 to 3 tCYCLE
(Encoded commands are in Table 6 on page 11).
.
POP2..0
BP2..0
ROWP
ROWP
ROWP
ROWP
COLX
3-bit bank address for row precharge command.
3-bit operation code that specifies refresh commands.
(Encoded commands are in Table 5 on page 10).
ROP2..0
RA7..0
8-bit refresh address field (specifies BR bank address, delay value, and REFr load value)
4-bit extended operation code that specifies calibration and powerdown commands.
(Encoded commands are in Table 7 on page 11).
XOP3..0
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Figure 3 : Request Packet Formats
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
CFM
C
CFMN
tCYCLE
RQ11..0
ACT
a0
RD
a1
WRM
a2
PRE
a3
PDN
-
DQ15..0
DQN15..0
ROWA Packet
COL Packet
COLM Packet
ROWP Packet
COLX Packet
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
CFM
CFMN
OP DEL
OP DEL
OP
3
M
7
OP POP
OP rsrv
3
RQ11
RQ10
RQ9
RQ8
RQ7
RQ6
RQ5
RQ4
RQ3
RQ2
RQ1
RQ0
3
A
3
C
3
2
OP
2
R
8
OP rsrv
2
M
3
M
6
OP ROP
OP rsrv
2
2
2
R
9
R
7
rsrv
M
5
ROP
1
OP rsrv
1
OP
1
M
2
OP
1
R
10
R
6
OP rsrv
0
M
1
M
4
OP ROP
OP rsrv
0
0
0
rsrv
rsrv
rsrv
rsrv
rsrv
R
5
WR
X
C
7
M
0
C
7
POP RA
rsrv rsrv
rsrv rsrv
rsrv rsrv
rsrv rsrv
1
7
C
8
C
8
R
4
C
6
C
6
POP RA
0
6
C
9
C
9
rsrv
R
3
C
5
C
5
RA
5
rsrv
rsrv
rsrv
rsrv
R
2
C
4
C
4
RA
4
rsrv SC
3
rsrv SC
3
R
1
RA
3
XOP rsrv
3
BA
2
BC
2
SC
2
BC
2
SC
2
BP
2
R
0
RA
2
XOP rsrv
2
SC
1
SC
1
rsrv
rsrv
BC
1
BP
1
RA
1
XOP rsrv
1
BA
1
BC
1
SC
0
SC
0
BC
0
BP
0
RA
0
XOP rsrv
0
BA
0
BC
0
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Request Field Encoding
Operation code fields are encoded within different packet types to specify commands. Table4 through Table7 provides packet
type and encoding summaries.
Table4 shows the OP field encoding for five packet types. The COLM and ROWA packets each specify a single command : ACT
and WRM. The COL, COLX, and ROWP packets each use additional fields to specify multiple commands : WRX, XOP, and
POP/ROP, respectively. The COLM packet specifies the masked write command WRM. This is like the WR unmasked write
command, except that a mask field M7...0 indicates whether each byte of the write data packet is written or not written. The
ROWA packet specifies the row activate command ACT. The COL packet uses the WRX field to specify the column read and
column write(unmasked) commands.
Table 4 : OP Field Encoding Summary
OP [3:0] Packet Command
Description
0000
-
NOP
RD
No operation.
Column read (WRX=0). Column C9..4 of sense amp in bank BC2..0 is read to DQ bus after
DELC*tCYCLE
Column write (WRX=1). Write DQ bus to column C9..4 of sense amp in bank BC2..0 after
DELC*tCYCLE
.
0001
COL
WR
.
0010
0011
COLX CALy
XOP3..0 specifies a calibrate or powerdown command — see Table 7 on page 11.
POP2..0 specifies a row precharge command — see Table 6 on page 11.
PREx
ROWP
ROP2..0 specifies a row refresh command or load REFr register command — see Table 5
on page 10.
REFy,LRRr
Row activate command. Row R10..0 of bank BA2..0 is placed into the sense amp of the
01xx
1xxx
ROWA ACT
COLM WRM
bank after DELA*tCYCLE
.
Column write command (masked) — mask M7..0 specifies which bytes are written.
Encoding of the ROP field in the ROWP packet is shown in Table5. The first encoding specifies a NOPR (no operation)
command. The REFP command uses the RA field to select a bank to be precharged. The REFA and REFI commands use the
RA field and REFH/M/L registers to select a bank and row to be activated for refresh. The REFI command also increments the
REFH/M/L register. The REFP, REFA, and REFI commands may also be delayed by up to 3*tCYCLE using the RA[7:6] field. The
LRR0, LRR1, and LRR2 commands load the REFH/M/L registers from the RA[7:0] field.
Table 5 : ROP Field Encoding Summary
ROP[2:0] Command
Description
000
001
NOPR
REFP
No operation
Refresh precharge command. Bank RA2..0 is precharged.
This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]).
Refresh activate command. Row R[10:0] (from REFH/M/L register) of bank RA2..0 is placed into
sense amp.
010
011
REFA
REFI
This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]).
Refresh activate command. Row R[10:0] (from REFH/M/L register) of bank RA2..0 is placed into
sense amp.
This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]).
R[10:0] field of REFH/M/L register is incremented after the activate command has completed.
Load Refresh Low Row register (REFL). RA[7:0] is stored in R[7:0] field.
Load Refresh Middle Row register (REFM). RA[2:0] is stored in R[10:8] field.
Load Refresh High Row register — not used with this device.
Reserved
100
101
110
111
LRR0
LRR1
LRR2
-
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The REFH/M/L registers are also refreshed to as the REFr registers. Note that only the bits that are needed for specifying the
refresh row(11 bits in all) are implemented in the REFr registers - the rest are reserved. Note also that the RA2 ... RA0 field that
specifies the refresh bank address is also referred to as BR2...0. See “Refresh Transactions” on page37.
Table6 shows the POP field encoding in the ROWP packet. The first encoding specifies a NOPP(no operation) command. There
are four variations of PRE(precharge) command. Each uses the BP field to specify the bank to be precharged. Each also speci-
fies a different delay of up to 3*tCYCLE using the POP[1:0] field. A precharge command may be specified in addition to a refresh
command using the ROP field.
Table 6 : POP Field Encoding Summary
POP[2:0] Command
Description
000
001
010
011
100
NOPP
No operation.
Reserved.
Reserved.
Reserved.
-
-
-
PRE0
Row precharge command — Bank BP2..0 is precharged. This command is delayed by 0*tCYCLE
Row precharge command — Bank BP2..0 is precharged. This command is delayed by 1*tCYCLE
Row precharge command — Bank BP2..0 is precharged. This command is delayed by 2*tCYCLE
Row precharge command — Bank BP2..0 is precharged. This command is delayed by 3*tCYCLE
.
.
.
.
101
110
111
PRE1
PRE2
PRE3
Table7 shows the XOP field encoding in the COLX packet. This field encodes the remaining commands.
The CALC and CALE commands perform calibration operations to ensure signal integrity on the Channel. See “Calibration
Transactions” on page 39.
The PDN command causes the device to enter a power-down state. See”Power State Management” on page 40.
Table 7 : XOP Field Encoding Summary
XOP
[3:0]
XOP
[3:0]
Command
Command and Description
Command
Command and Description
0000
0001
0010
0011
0100
0101
0110
0111
-
-
-
-
-
-
-
-
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
1000
1001
1010
1011
1100
1101
1110
1111
CALC
Current calibration command.
Impedance calibration command.
End calibration command (CALC).
Reserved.
CALZ
CALE
-
PDN
Enter powerdown power state.
Reserved.
-
-
-
Reserved.
Reserved.
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Request Field Interactions
A summary of request packet interaction is Table8. Each case is limited to request packets with commands that perform memory
operations(including refresh commands). This includes all commands in ROWA, ROWP, COL, and COLM packets. The
commands in COLX packets are described in later sections. See “Maintenance Operations” on page38.
Request packet/command “a” is followed by request/ command “b”. The minimum possible spacing between these two
packet/command is 0*tCYCLE. However, a larger time interval may be needed because of a resource interaction between the two
packet/commands. If the minimum possible sapcing is 0*tCYCLE, then an entry of “No limit” is shown in the table.
Note that the spacing values shown in the table are relative to the effective beginning of a packet/command. The use of the
delay field with a command will delay the position of the effective packet/command from the position of the actual
packet/command. See “Dynamic Request Scheduling” on page18 .
Any of the packet/command encoding under one of the four operation types is equivalent in terms of the resource constraints.
Therefore. both the horisontal columns(packet “a”) and vertical rows(packet “b”) of the interaction table are divided into four
major groups.
The four possible operation types for request packet a and b include :
: [A] Active Row
ROWA/ACT
ROWP/REFA
ROWP/REFI
: [R] Read Column COL/RD
: [W] Write Column COL/WR
COLM/WRM
: [P] Precharge Row ROWP/PRE
ROWP/REFP
Table 8 : Packet Interaction Summary
Second packet/command to bank Bb
Read Column [R] Write Column [W] Precharge Row [P]
Activate Row [A]
First packet/command to bank
Ba
ROWA - ACT Bb
ROWP - REFA Bb
ROWP - REFI Ba
COL - WR Bb
ROWP - PRE Bb
ROWP - REFP Bb
COL - RD Bb
COLM - WRM Bb
Case AAd: tRR
Ba,Bb different
Ba,Bb same
Case ARd: No limit Case AWd: No limit
Case APd: No limit
Case APs: tRAS
Activate Row [A]
ROWA - ACT Ba
ROWP - REFA Ba
ROWP - REFI Ba
Case AAs: tRC
Case ARs: tRCD-R
Case AWs: tRCD-W
Case RWd:a t∆RW
Case RWs: a t∆RW
Case WWd: tCC
Case RRd: tCC
Case RRs: tCC
Case WRd:c t∆WR
Ba,Bb different Case RAd: No limit
Case RPd: No limit
Case RPs: tRDP
Read Column [R]
COL - RD Ba
Case RAs:b tRDP+tRP
Ba,Bb same
Write Column [W] Ba,Bb different Case WAd: No limit
COL - WR Ba
Ba,Bb same
Case WPd: No limit
Case WPs: tWRP
Case PPd: tPP
Case WAsb:tWRP+tRP Case WRs:c t∆WR
Case WWs: tCC
COLM - WRM Ba
Ba,Bb different Case PAd: No limit
Case PRd: No limit Case PWd: No limit
Precharge Row [P]
ROWP - PRE Ba
ROWP - REFP Ba
Case PRs:d
Case PWs:d tRP+tRCD-W
Case PAs: tRP
Figure 4
Case PPs: tRC
Figure 7
Ba,Bb same
tRP+tRCD-R
See Examples:
Figure 5
Figure 6
a. t
is equal to t + t
+ t
- t
and is defined in Table 18. This also depends upon propagation delay - See “Prop-
RW
∆
CC
RW-BUB,XDRDRAM CAC CWD
agation Delay” on page 27.
b. A PRE command is needed between the RD and ACT/REFA commands or the WR/WRM and ACT/REFA commands.
c. t is defined in Table 18.
RW
∆
d. An ACT command is needed between the PRE/REFP and RD commands or the PRE/REFP and WR/WRM commands.
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The first request is shown along the vertical axis on the left of the table. The second request is shown along the horizontal axis
at the top of the table. Each request includes a bank specification “Ba” and “Bb”. The first and second banks may be the same,
or they may be different. These two subcases for each interaction are shown along the vertical axis on the letf.
There are 32 possible interaction cases altogether. The table gives each case a label of the form “xyz”, where “x” and “y” are one
of the four operation types(“A” for Activate, “R” for Read, “W” for Write, or “P” for Precharge) for the first and second request,
respectively, and “z” indicates the same bank(“s”) or different bank(“d”).
Along the horizontal axis at the bottom of the table are cross references to four figures(Figure4 through Figure7). Each figure
illustrates the eight cases in the corresponding vertical column. Thus, Figure4 shows the eight cases when the second request
is an activate operation(“A”). In the following discussion of the cases, only those in which the interaction interval is greater than
tCYCLE will be described.
Request Interactions Cases
In Figure4. the interaction interval for the AAd case is tRR. This parameter is the row-to-row time and is the minimum interval
between activate commands to different banks of a device.
The interaction interval for the AAs case is tRC. This is the row cycle time parameter and is the minimum interval between acti-
vate commands to same banks of a device. A precharge operation must be inserted between the two activate operations.
The interaction interval for the RAs case is tRDP + tRP. A precharge operation must be inserted between the read and activate
operation. The minimum interval between a read and a precharge operation to a bank is tRDP. The minimum interval between a
precharge and an activate operation to a bank is tRP
.
The interaction interval for the WAs case is tWDP + tRP. A precharge operation must be inserted between the read and the acti-
vate operation. The minimum interval between a write and a precharge operation to a bank is tWDP. The minimum interval
between a precharge and an activate operation to a bank is tRP
The interaction interval for the PAs case is tRP. The minimum interval between a precharge and an activate operation to a bank
is tRP
.
.
In Figure5, the interaction interval for the ARs case is tRCD-R. This is the row-to-column-read time parameter and represents the
minimum interval between an activate operation and a read operation to a bank.
The interaction interval for the RRd and RRs cases is tCC. This is the column-to-column time parameter and represents the
minimum interval between two read operations.
The interaction interval for the WRd and WRs cases is t∆WR. This is the write-to-read time parameter and represents the
minimum interval between a write and a read operation to any banks. See “Read/Write Interaction” on page 26.
The interaction interval for the PRs case is tRP + tRCD-R. An activate operation must be inserted between the precharge and the
read operation. The minimum interval between a precharge and an activate operation to a bank is tRP. The minimum interval
between an activate and a read operation to a bank is tRCD-R
.
In Figure6. the interaction interval for the AWs case is tRCD-W. This is the row-to-column-write timing parameter and represents
the minimum interval between an activate operation and a write operation to a bank.
The interaction interval for the RWd and RWs cases is t∆RW. This is the read-to-write time parameter and represents the
minimum interval between a read and a write operation to any banks. See “Read/Write Interaction” on page26.
The interaction interval for the WWd and WWs cases is tCC. This is the column-to-column time parameter and represents the
minimum interval between two write operations.
The interaction interval for the PWs case is tRP + tRCD-W. An activate operation must be inserted between the precharge and the
write operation. The minimum interval between a precharge and an activate operation to a bank is tRP. The minimum interval
between an activate and a write operation to a bank is tRCD-W
.
In Figure7, the interaction interval for the APs case is tRAS. This parameter is the minimum activate-to-precharge time to a bank.
The interaction interval for the RPs and WPs cases are tRDP and tWDP, respectively. These are the read-or write-to-precharge
time parameters to a bank.
Ths interaction interval for the PPd case is tPP. This parameter is the precharge-to-precharge time and the minimum interval
between precharge commands to different banks of a device.
The interaction interval for the PPs case is tRC. This is the row cycle time parameter and the minimum interval between
precharge commands to same banks of a device. An activate operation must be inserted between the two activate operations.
This activate operation must be placed a time tRP after the first, and a time tRAS before the second precharge.
Version 1.0 Jan. 2005
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Figure 4 : ACT-, RD-, WR-, PRE-to-ACT Packet Interactions
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
6
7
8
8
8
8
9
9
9
9
10
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
23
23
23
CFM
CFMN
tRP
tRAS
RQ11..0
ACT
a
ACT
b
ACT
a
PRE
a
ACT
b
R
tRR
tRC
DQ15..0
D
DQN15..0
AAd Case (activate-activate-different bank)
a: ROWA Packet with ACT,Ba,Ra
AAs Case (activate-activate-same bank)
a: ROWA Packet with ACT,Ba,Ra
b: ROWA Packet with ACT,Bb,Rb
=
Ba Bb
Ba = Bb
/
b: ROWA Packet with ACT,Bb,Rb
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
21 22
0
1
2
3
4
6
7
11
12
13
14
15
16
17
18
19
20
CFM
CFMN
tRP
tRDP+tRP
tRDP
RQ11..0
RD ACT
RD
a
PRE
a
ACT
b
a
b
DQ15..0
No limit
DQN15..0
RAd Case (read-activate-different bank)
RAs Case (read-activate-same bank)
a: COL Packet with RD,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
a: COL Packet with RD,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
=
Ba Bb
Ba = Bb
/
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
21 22
0
1
2
4
5
6
7
11
12
13
14
15
16
17
18
19
20
CFM
CFMN
tRP
tWRP
tWRP+tRP
PRE
a
ACT
b
WR ACT
WR
a
RQ11..0
a
b
No limit
DQ15..0
0
DQN15..0
WAd Case (write-activate-different bank)
WAs Case (write-activate-same bank)
a: COL Packet with WR,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
a: COL Packet with WR,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
=
Ba Bb
Ba = Bb
/
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
21 22
0
1
2
3
4
6
7
10
11
12
13
14
15
16
17
18
19
20
CFM
CFMN
PRE ACT
PRE
a
ACT
b
RQ11..0
a
b
tRP
No limit
DQN15..0
DQ15..0
PAd Case (precharge-activate-different bank)
a: ROWP Packet with PRE,Ba
PAs Case (precharge-activate-same bank)
a: ROWP Packet with PRE,Ba
b: ROWA Packet with ACT,Bb,Rb
=
Ba Bb
Ba = Bb
/
b: ROWA Packet with ACT,Bb,Rb
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Figure 5 : ACT-, RD-, WR-, PRE-to-RD Packet Interactions
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
6
6
6
6
7
8
8
8
8
9
9
9
10
10
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
23
23
23
CFM
CFMN
RQ11..0
ACT RD
ACT
a
RD
b
DQ15..0
a
b
tRCD-R
No limit
DQN15..0
ARd Case (activate-read different bank)
ARs Case (activate-read same bank)
a: ROWA Packet with ACT,Ba,Ra
b: COL Packet with RD,Bb,Cb
a: ROWA Packet with ACT,Ba,Ra
b: COL Packet with RD,Bb,Cb
=
/
Ba Bb
Ba = Bb
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
7
11
12
13
14
15
16
17
18
19
19
19
20
21 22
CFM
CFMN
RD
a
RD
a
RD
b
RD
b
RQ11..0
tCC
tCC
DQ15..0
DQN15..0
RRd Case (read-read different bank)
RRs Case (read-read same bank)
a: COL Packet with RD,Ba,Ca
b: COL Packet with RD,Bb,Cb
a: COL Packet with RD,Ba,Ca
b: COL Packet with RD,Bb,Cb
=
/
Ba Bb
Ba = Bb
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
7
12
13
14
15
16
17
18
20
21 22
CFM
CFMN
WR
a
RD
b
WR
a
RD
b
RQ11..0
t∆WR
t∆WR
DQ15..0
DQN15..0
WRd Case (write-read different bank)
WRs Case (write-read same bank)
a: COL Packet with WR,Ba,Ca
b: COL Packet with RD,Bb,Cb
a: COL Packet with WR,Ba,Ca
b: COL Packet with RD,Bb,Cb
=
Ba / Bb
Ba = Bb
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
7
9
11
12
13
14
15
16
17
18
20
21 22
CFM
CFMN
tRCD-R
tRP
tRP+tRCD-R
PRE RD
PRE
a
ACT
B
RQ11..0
RD
b
a
b
No limit
DQ15..0
DQN15..0
PRd Case (precharge-read different bank)
a: ROWP Packet with PRE,Ba
PRs Case (precharge-read same bank)
a: ROWP Packet with PRE,Ba
b: COL Packet with RD,Bb,Cb
=
Ba Bb
Ba = Bb
/
b: COL Packet with RD,Bb,Cb
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Figure 6 : ACT-, RD-, WR-, PRE-to-WR Packet Interactions
T T T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
22 23
0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CFM
CFMN
ACT WR
ACT WR
a
RQ11..0
a
b
b
tRCD-W
No limit
DQ15..0
DQN15..0
AWd Case (activate-write different bank)
AWs Case (activate-write same bank)
a: ROWA Packet with ACT,Ba,Ra
b: COL Packet with WR,Bb,Cb
a: ROWA Packet with ACT,Ba,Ra
b: COL Packet with WR,Bb,Cb
=
Ba / Bb
Ba = Bb
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
22 23
0
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
CFM
CFMN
t∆
t∆
RW
RW
RD
a
RD
a
WR
b
WR
b
RQ11..0
tCWD
tCWD
DQ15..D0
Q(a)
D(b)
Q(a)
D(b)
DQN15..0
t
t
CAC
CAC
tCC tCYCLE
tCC tCYCLE
RWd Case (read-write-different bank)
RWs Case (read-write-same bank)
a: COL Packet with RD,Ba,Ca
b: COL Packet with WR,Bb,Cb
a: COL Packet with RD,Ba,Ca
b: COL Packet with WR,Bb,Cb
=
/
Ba Bb
Ba = Bb
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
22 23
0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CFM
CFMN
WR
a
WR
a
WR
b
WR
b
RQ11..0
tCC
tCC
DQ15..0
DQN15..0
WWd Case (write-write different bank)
WWs Case (write-write same bank)
a: COL Packet with WR,Ba,Ca
b: COL Packet with WR,Bb,Cb
a: COP Packet with WR,Ba,Ca
b: COL Packet with WR,Bb,Cb
=
Ba / Bb
Ba = Bb
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
22 23
0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CFM
CFMN
tRCD-W
tRP
tRP+tRCD-W
PRE WR
PRE
a
ACT
B
WR
b
RQ11..0
a
b
No limit
DQ15..0
DQN15..0
PWd Case (precharge-write different bank)
a: ROWP Packet with PRR,Ba
PWs Case (precharge-write same bank)
a: ROWP Packet with PRE,Ba
b: COP Packet with WR,Bb,Cb
=
/
Ba Bb
Ba = Bb
b: COL Packet with WR,Bb,Cb
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
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Figure 7 : ACT-, RD-, WR-, PRE-to-PRE Packet Interactions
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
6
7
8
8
8
8
9
9
9
9
10
11
11
11
12
13
14
15
16
17
18
19
20
21
22
23
23
23
23
CFM
CFMN
PRE
b
ACT PRE
ACT
a
RQ11..0
a
b
tRAS
No limit
DQ15..0
DQN15..0
APd Case (activate-precharge different bank)
a: ROWA Packet with ACT,Ba,Ra
APs Case (activate-precharge same bank)
a: ROWA Packet with ACT,Ba,Ra
=
Ba Bb
/
Ba = Bb
b: ROWP Packet with PRE,Bb
b: ROWP Packet with PRR,Bb
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
6
7
10
10
10
12
13
14
15
16
17
18
19
20
21 22
CFM
CFMN
PRE
b
RD PRE
RD
a
RQ11..0
a
b
tRDP
No limit
DQ15..0
DQN15..0
RPd Case (read-precharge different bank)
RPs Case (read-precharge same bank)
a: COL Packet with RD,Ba,Ca
b: ROWP Packet with PRE,Bb
a: COL Packet with RD,Ba,Ca
b: ROWP Packet with PRR,Bb
=
Ba Bb
/
Ba = Bb
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
6
7
12
13
14
15
16
17
18
19
20
21 22
CFM
CFMN
WR PRE
WR
a
PRE
b
RQ11..0
a
b
t
WRP
No limit
DQ15..0
DQN15..0
WPd Case (write-precharge different bank)
a: COL Packet with WR,Ba,Ca
WPs Case (write-precharge same bank)
a: COL Packet with WR,Ba,Ca
b: ROWP Packet with PRE,Bb
=
Ba/Bb
Ba = Bb
b: ROWP Packet with PRE,Bb
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
6
7
11
12
13
14
15
16
17
18
19
20
21 22
CFM
CFMN
tRAS
tRP
PRE
a
PRE
b
ACT
b
RQ11..0
PRE
a
PRE
b
tPP
tRC
DQ15..0
DQN15..0
PPd Case (precharge-precharge different bank)
a: ROWP Packet with PRE,Ba
PPs Case (precharge-precharge same bank)
a: ROWP Packet with PRE,Ba
Ba # Bb
Ba = Bb
b: ROWP Packet with PRE,Bb
b: ROWP Packet with PRE,Bb
Version 1.0 Jan. 2005
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Dynamic Request Scheduling
Delay fields are present in the ROWA, COL, and ROWP packet. They permit the associated command to optionally wait for a
time of one (or more) tCYCLE before taking effect. This allows a memory controller more scheduling flexibility when issuing
request packets. Figure8 illustrates the use of the delay fields.
In the first timing diagram, a ROWA packet with an ACT command is present at cycle T0. The DELA field is set to “1”. This
request packet will be equivalent to a ROWA packet with an ACT command at cycle T1 with the DELA field is set to “0”. This
equivalence should be used when analyzing request packet interactions.
In the second timing diagram, a COL packet with a RD command is present at cycle T0. The DELC field is set to “1”. This
request packet will be equivalent to a COL packet with an RD command at cycle T1 with the DELC field is set to “0”. This equiv-
alence should be used when analyzing request packet interactions.
In a similar fashion, a COL packet with a WR command is present at cycle T12. The DELC field is set to”1”. This request packet
will be equivalent to a COL packet with a WR command at cycle T13 with the DELC field is set to “0”. This equivalence should be
used when analyzing request packet interactions.
In the COL packet with a RD command example, the read data delay, tCAC is measured between the Q read data packet and the
virtual COL packet at cycle T1.
Likewise, for the example with the COL packet with a WR command, the write data delay, tCWD is measured between the D write
data packet and the virtual COL packet at cycle T13
.
In the third timing diagram, a ROWP packet with a PRE command is present at cycle T0. The DEL field(POP[1:0]) is set to “11”.
This request packet will be equivalent to a ROWP packet with a PRE command at cycle T1 with the DEL field is set to “10”, it will
be equivalent to a ROWP packet with a PRE commmand at cycle T2 with the DEL field is set to “01”, and it will be equivalent to
a ROWP packet with a PRE command at cycle T3 with the DEL field is set to “00”. This equivalence should be used when
analyzing request packet interactions.
In the fourth timing diagram, a ROWP packet with a REFP command is present at cycle T0. The DEL field(RA[7:6] ) is set to “11”.
This request packet will be equivalent to a ROWP packet with a REFP command at cycle T1 with the DEL field is set to “10”, it
will be equivalent to a ROWP packet with a REFP command at cycle T2 with the DEL field is set to “01”, and it will be equivalent
to a ROWP packet with a REFP command at cycle T3 with the DEL field is set to “00”. This equivalence should be used when
analyzing request packet interactions.
The two examples for the REFA and REFI commands are identical to the example just described for the REFP command.
The ROWP packet allows two independent operations to be specified. A PRE precharge command uses the POP and BP fields,
and the REFP, REFA, or REFI commands use the ROP and RA fields. Both operations have an optional delay field(the POP
field for the PRE command and the RA field with the REFP, REFA, or REFI commands). The two delay mechanisms are inde-
pendent of one another. The POP field does not affect the timing of the REFP, REFA, or REFI commands, and the RA field does
not affect the timing of the PRE command.
When the interactions of a ROWP packet are analyzed, it must be remembered that there are two independent commands
specified, both of which may affect how soon the next request packet can be issued. The constraints from both commands in a
ROWP packet must be considered, and the one that requires the longer time interval to the next request packet must be used by
the memory controller. Furthermore, the two commands within a ROWP packet may not reference the same bank in the BP and
RA fields.
Version 1.0 Jan. 2005
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Figure 8 : Request Scheduling Examples
ACT w/DEL=1 at T is equivalent
0
to ACT w/DEL=0 at T
1
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
10
10
10
11
11
11
12
13
14
15
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
ACT ACT
DEL1 DEL0
RQ11..0
DQ15..0
DQN15..0
Note DEL value is specified by DELA field.
ROWA/ACT Command
WR w/DEL=1 at T is equivalent
12
to WR w/DEL=0 at T
RD w/DEL=1 at T is equivalent
0
to RD w/DEL=0 at T
13
1
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
RD RD
DEL1 DEL0
WR WR
DEL1 DEL0
RQ11..0
DQ15..0
DQN15..0
Q
D
tCAC
tCWD
Note DEL value is specified by DELC field.
COL/RD and COL/WR Commands
PRE w/DEL=3 at T is equivalent to PRE w/DEL
=2 at T or PRE w/DEL=1 at T or PRE w/DEL=0 at T
0
1
2
3
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
PRE PRE
DEL3 DEL2
PRE PRE
DEL1 DEL0
RQ11..0
DQ15..0
DQN15..0
Note DEL value is specified by {POP1, POP0} field.
ROWP/PRE Command
REFP w/DEL=3 at T is equivalent to REFP w/DEL=2
REFI w/DEL=3 at T is equivalent to REFI w/DEL=2
13
0
at T or REFP w/DEL=1 at T or REFP w/DEL=0 at T
at T or REFI w/DEL=1 at T or REFI w/DEL=0 at T
1
2
3
14 15 16
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
3
4
5
6
7
8
9
10
12
13
14
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
REFA REFA REFA REFA
DEL3 DEL2 DEL1 DEL0
REFP REFP
DEL1 DEL0
REFI REFI REFI REFI
DEL3 DEL2 DEL1 DEL0
REFP REFP
DEL3 DEL2
RQ11..0
DQ15..0
REFA w/DEL=3 at T is equivalent to REFA w/DEL=2
DQN15..0
6
at T or REFA w/DEL=1 at T or REFA w/DEL=0 at T
7
8
9
Note DEL value is specified by {RA7, RA6} field.
ROWP/REFP,REFA,REFI Commands
Version 1.0 Jan. 2005
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Memory Operations
Write Transactions
Figure9 shows four examples of memory write transactions. A transaction is one or more request packets (and the associated
data packets) needed to perform a memory access. The state of the memory core and the address of the memory access deter-
mine how many request packets are needed to perform the access.
The first timing diagram shows a page-hit write transaction. In this case, the selected bank is already open (a row is already
present in the sense amp array for the bank). In addition, the selected row for the memory access matches the address of the
row already sensed (a page hit). This comparison must be done in the memory controller. In this example, the access is made to
row Ra of bank Ba.
In this case, write data may be directly written into the sense amp array for the bank, and row operations(activated or precharge)
are not needed. A COL packet with WR command to column Ca1 of bank Ba is presented on edge T0, and a second COL
packet with WR command to column Ca1 of bank Ba is presented on edge T2. Two write data packets D(a1) and D(a2) follow
these COL packets after the write data delay tCWD. The two COL packets are separated by the column-cycle time tCC. This is
also the length of each write data packet.
The second timing diagram shows an example of a page-miss write transaction. In this case, the selected bank is already open
(a row is already present in the sense amp array for the bank). However, the selected row for the memory access does not
match the address of the row already sensed (a page miss). This comparsion must be done in the memory controller. In this
example, the access is made to row Ra of bank Ba, and the bank contains a row other than Ra.
In this case, write data may not be directly written into the sense amp array for the bank. It is necessary to close the present row
(precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is presented on edge T0. An
activate command (ACT to row Ra of bank Ba) is presented on edge T6 a time tRP later. A COL packet with WR command to
column Ca1 of bank Ba is presented on edge T7 a time tRCD-W later. A second COL packet with WR command to column Ca2 of
bank Ba is presented on edge T9. Two write data packets D(a1) and D(a2) follow these COL packets after the write data delay
tCWD. The two COL packets are separated by the column-cycle time tCC. This is also the length of each write data packet.
The third timing diagram shows an example of a page-empty wirte transaction. In this case, the selected bank is already closed
(no row is present in the sense amp array for the bank). No row comparison is necessary for this case; however, the memory
controller must still remember that bank Ba has been left closed. In this example, the access is made to row Ra of bank Ba.
In this case, write data may not be directly written into the sense amp array for the bank. It is necessary to access the requested
row (activate). An activate command (ACT to row Ra of bank Ba) is presented on edge T0. A COL packet with WR command to
column Ca1 of bank Ba is presented on edge T1 a time tRCD-W later. A second COL packet with WR command to column Ca2 of
bank Ba is presented on edge T3. Two write data packets D(a1) and D(a2) follow these COL packets after the write data delay
tCWD. The two COL packets are separated by the column-cycle time tCC. This is also the length of each write data packet. After
the final write command, it may be necessary to close the present row (precharge). A precharge command (PRE to bank Ba) is
presented on edge T14 a time tWRP after the last COL packet with a WR command. The decision whether to close the bank or
leave it open is made by memory controller and its page policy.
The fourth timing diagram shows another example of a page-empty write transaction. This is similar to the previous example
except that only a single write command is presented, rather than two write commands. This example shows that even with a
minimum length write transaction, tRAS parameter will not be a constraint. The tRAS measures the minimum time between an
activate command and a precharge command to a bank. This time interval is also constrained by the sum tRCD-W + tWRP which
will be larger for a write transaction. These two constraints (tRAS and tRCD-W + tWRP) will be a function of the memory device’s
speed bin and the data transfer length (the number of write commands issued between the activate and precharge commands),
and the tRAS parameter could become a constraint for future speed bins. In this example, the sum tRCD-W + tWRPs is greater
than tRAS by the amount ∆tRAS.
Version 1.0 Jan. 2005
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Figure 9 : Write Transactions
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
10
10
10
10
11
12
13
14
14
14
15
15
15
15
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
WR
a1
WR
a2
RQ11..0
tCC
DQ15..0
DQN15..0
D(a1)
D(a2)
t
CWD
Page-hit Write Example
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
11
12
13
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
PRE
a3
ACT WR
a0 a1
WR
a2
RQ11..0
tRP
tRCD-W tCC
DQ15..0
DQN15..0
D(a1)
D(a2)
tCWD
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-miss Write Example
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
11
12
13
16
17
18
19
20
21
22 23
CFM
CFMN
tCWD
tDP
tCYCLE
ACT WR
a0 a1
WR
a2
PRE
a3
RQ11..0
tWRP
tCC
tRCD-W
DQ15..0
DQN15..0
D(a1)
D(a2)
tCWD
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-empty Write Example
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
11
12
13
14
16
17
18
19
20
21
22 23
CFM
CFMN
tRAS
tRP
∆tRAS
tCYCLE
ACT WR
PRE
a3
ACT
b0
RQ11..0
a0
a1
tWRP
tRCD-W
DQ15..0
DQN15..0
D(a1)
t
CWD
Transaction a: WR
Transaction b: WR
a0 = {Ba,Ra}
b0 = {Bb,Rb}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
a3 = {Ba}
b3 = {Bb}
Bb = Ba
Page-empty Write Example - Core Limited
Version 1.0 Jan. 2005
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XDR DRAM
Read Transactions
Figure10 shows four examples of memory read transactions. A transaction is one or more request packets (and the associated
data packets) needed to perform a memory access. The state of the memory core and the address of memory access determine
how many request packets are needed to perform the access.
The first timing diagram shows a page-hit read transaction. In this case, the selected bank is already open (a row is already
present in the sense amp array for the bank). In addition, the selected row for the memory access matches the address of the
row already sensed (a page hit). This comparison must be done in the memory controller. In this example, the access is made to
row Ra of bank Ba.
In this case, read data may be directly read from the sense amp array for the bank and no row operations (actiavate or
precharge) are needed. A COL packet with RD command to column Ca1 of bank Ba is presented on edge T0 and a second COL
packet with RD command to column Ca2 of bank Ba is presented on edge T2. Two read data packets Q(a1) and Q(a2) follow
these COL packets after the read data delay tCAC. The two COL packets are separated by the column-cycle time tCC. This is
also the length of each read data packet.
The second timing diagram shows an example of a page-miss read transaction. In this case, the selected bank is already open
(a row is already present in the sense amp array for the bank). However, the selected row for the memory access does not
match the address of the row already sensed(a page miss). This comparison must be done in the memory controller. In this
example, the access is made to row Ra of bank Ba, and the bank contains a row other than Ra.
In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to close the present row
(precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is presented on edge T0. An
activate command (ACT to row Ra of bank Ba) is presented on edge T6 a time tRP later. A COL packet with RD command to
column Ca1 of bank Ba is presented on edge T11 a time tRCD-R later. A second COL packet with RD command to column Ca2 of
bank Ba is presented on edge T13. Two read data packets Q(a1) and Q(a2) follow these COL packets after the read data delay
tCAC. The two COL packets are separated by the column-cycle time tCC. This is also the length of each read data packet.
The third timing diagram shows an example of a page-empty write transaction. In this case, the selected bank is already closed
(no row is present in the sense amp array for the bank). No row comparison is necessary for this case; however, the memory
controller must still remember that bank Ba has been left closed. In this example, the access is made to row Ra of bank Ba.
In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to access the requested
row (activated). An activate command (ACT to row Ra of bank Ba) is presented on edge T0. A COL packet with RD command to
column Ca1 of bank Ba is presented on edge T5 a time tRCD-R later. A second COL packet with RD command to column Ca2 of
bank Ba is presented on edge T7. Two read data packets Q(a1) and Q(a2) follow these COL packets after the read data delay
tCAC. The two COL packets are separated by the column-cycle time tCC. This is also the length of each read data packet. After
the final read command, it may be necessary to close the present row (precharge). A precharge command - PRE to bank Ba - is
presented on edge T10 a time tRDP after the last COL packet with a RD command. Whether the bank is closed or left open
depends on the memory controller and its page policy.
The fourth timing diagram shows another example of a page-empty read transaction. This is similar to the previous example
except that it uses one read command instead of two read commands. In this case, the core parameter tRAS may also be a
constraint upon when the precharge command may be issued.
The tRAS measures the minimum time between an activate command and a precharge command to a bank. This time interval is
also constrained by the sum tRCD-R + tRDP and must be set to whichever is larger. These two constraints (tRAS and tRCD-R
RDP) will be a function of the memory device’s speed bin and the data transfer length (the number of read commands issued
+
t
between the activate and precharge commands). In this example, the tRAS is greater than the sum tRCD-R + tRDP by the amount
∆tRDP.
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Figure 10 : Read Transactions
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
22 23
0
1
2
3
4
5
6
7
8
9
10
10
10
11
12
13
14
15
15
15
15
16
17
18
19
20
21
CFM
CFMN
tCYCLE
RD
a1
RD
a2
RQ11..0
tCC
DQ15..0
DQN15..0
Q(a1)
Q(a2)
tCAC
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-hit Read Example
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
22 23
0
1
1
1
2
3
4
5
6
7
8
9
11
12
13
14
16
17
18
19
20
21
CFM
CFMN
tCYCLE
PRE
a3
ACT
a0
RD
a1
RD
a2
RQ11..0
tRP
tRCD-R
tCC
DQ15..0
DQN15..0
Q(a1)
Q(a2)
tCAC
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-miss Read Example
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
22 23
0
2
3
4
5
6
7
8
9
11
12
13
14
16
17
18
19
20
21
CFM
CFMN
tCYCLE
ACT
a0
RD
a1
RD
a2
PRE
a3
RQ11..0
tRDP
tRCD-R
tCC
DQ15..0
DQN15..0
Q(a1)
Q(a2)
tCAC
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-empty Read Example
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
22 23
0
2
3
4
5
6
7
8
9
10
11
12
13
14
16
17
18
19
20
21
CFM
CFMN
tRAS
tRP
tCYCLE
ACT
a0
RD
a1
PRE
a3
ACT
b0
RQ11..0
tRDP
∆tRDP
tRCD-R
DQ15..0
Q(a1)
tCAC
DQN15..0
Transaction a: RD
Transaction b: RD
a0 = {Ba,Ra}
b0 = {Bb,Rb}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
a3 = {Ba}
b3 = {Bb}
Bb = Ba
Page-empty Read Example - Core Limited
Version 1.0 Jan. 2005
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Interleaved Transactions
Figure11 shows two examples of interleaved transactions. Interleaved transactions are overlapped with one another; a transac-
tion is started before an earlier one is completed.
The timing diagram at the top of the figure shows interleaved write transactions. Each transaction assumes a page-empty
access; that is, a bank is in a closed state prior to an access and is precharged after the access. With this assumption, each
transaction requires the same number of request packets at the same relative positions. If bank were allowed to be in an open
state, then each transaction would require a different number of request packets depending upon whether the transaction was
page-empty, page-hit or page-miss. This situation is more complicated for the memory controller and will not be analyzed in this
document.
In the interleaved page-empty write example, there are four sets of request pins RQ11...0 shown along the left side of the timing
diagram. The first three show the timing slots used by each of the three requests packet types (ACT, COL and PRE), and the
fourth set (ALL) shows the previous three merged together. This allows the pattern used for allocating request slots for the
different packets to be seen more clearly.
The slots at {T0, T4, T8, T12 ...} are used for ROWA packets with ACT commands. This spacing is determined by the tRR param-
eter. There should not be interference between the interleaved transactions due to resource conflicts because each bank
address - Ba, Bb, Bc, Bd and Be - is assumed to be different from another. If two of the bank addresses are the same, the later
transaction would need to wait until the earlier transaction had completed its precharge operation. Five different banks are
needed because the effective tRC (tRC + ∆tRC) is 20*tCYCLE
.
The slots at {T1, T3, T5, T7, T9, T11, ...} are used for COL packets with WR commands. This frequency of the COL packet
spacing is determined by the tCC parameter and by the fact that there are two column accesses per row access. The phasing of
the COL packet spacing is determined by the tRCD-W parameter. If the value of tRCD-W required the COL packets to occupy the
same request slots as the ROWA packets (this case is not shown), the DELC field in the COL packet could be used to place the
COL packet one tCYCLEs earlier.
The DQ bus slots at {T7, T9, T11, T13, ...} carry the write data packets {D(a1), D(a2), D(b1), D(b2), ...}. Two write data packets are
written to a bank in each transaction. The DQ bus is completely filled with write data; no idle cycles need to be introduced
because there are no resource conflicts in this example.
The slots at {T14, T18, T22, ...} are used for ROWP packets with PRE commands. This frequency of ROWP packet spacing is
determined by the tPP parameter. The phasing of the ROWP packet spacing is determined by the tWRP paramter. If the value of
tWRP required the ROWP packets to occupy the same request slots as the ROWA or COL packets already assigned (this case is
not shown), the delay field in the ROWP packet could be used to place the ROWP packet one or more tCYCLE earlier.
There is an example of an interleaved page-empty read at the bottom of the figure. As before, there are four sets of request pins
RQ11...0 shown along the left side of the timing diagram, allowing the pattern used for allocating request slots for the different
packets to be seen more clearly.
The slots at {T0, T4, T8, T12, ...} are used for ROWA packets with ACT command. This spacing is determined by the tRR param-
eter. There should not be interference between the interleaved transactions due to resource conflicts because each bank
address - Ba, Bb, Bc and Bd - is assumed to be different from another. Four different banks are needed because the effective
tRC is 16 * tCYCLE.
The slots at {T5, T7, T9, T11, ...} are used for COL packets with RD commands. This frequency of the COL packet spacing is
determined by the tCC paramter and by the fact that there are two column accesses per row access. The phasing of the COL
packet spacing is determined by the tRCD-R parameter. If the value of tRCD-R required the COL packets to occupy the same
request slots as the ROWA packets (this case is not shown), the DELC field in the COL packet could be used to place the packet
one tCYCLE earlier.
The DQ bus slots at {T11, T13, T15, T17, ...} carry the read data packets {Q(a1), Q(a2), Q(b1), Q(b2), ...}, Two read data packets
are read from a bank in each transaction. The DQ bus is completely filled with read data - That is, no idle cycles need to be intro-
duced because there are no resource conflicts in this example.
The slots at {T10, T14, T18, T22, ...} are used for ROWP packets with PRE commands. This frequency of the ROWP packet
spacing is determined by the tPP parameter. The phasing of the ROWP packet spacing is determined by the tRDP parameter. If
the value of tRDP required the ROWP packets to occupy the same request slots as the ROWA or COL packets already assigned
(this case is not shown), the delay field in the ROWP packet could be used to place the ROWP packet one or more tCYCLEs
earlier.
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Figure 11 : Interleaved Transactions
The effective t time is increased by 4 t
RC
CYCLE
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
CFM
CFMN
tRC
∆tRC
tCYCLE
RQ11..0
(ACT)
ACT
a0
ACT
b0
ACT
c0
ACT
d0
ACT
e0
ACT
f0
tRR
RQ11..0
(COL)
WR
a1
WR
a2
WR
b1
WR
b2
WR
c1
WR
c2
WR
d1
WR
d2
WR
e1
WR
e2
WR
f1
WR
f2
tRCD-W
tCC
DQ15..0
DQN15..0
D(d2)
D(e1)
D(e1)
D(a1)
D(a2)
D(b1)
D(b2)
D(c1)
D(c2)
D(d1)
tWRP
∆tWRP
tRP
RQ11..0
(PRE)
PRE
a3
PRE
b3
PRE
c3
t
CWD
RQ11..0
(ALL)
ACT WR
a0 a1
WR ACT WR
a2 b0 b1
WR ACT WR
b2 c0 c1
WR ACT WR PRE WR ACT WR PRE WR ACT WR PRE WR
f1 f2
c2
d0
d1
a3
d2
e0
e1
b3
e2
f0
c3
Transaction a: WR
Transaction b: WR
Transaction c: WR
Transaction d: WR
Transaction e: WR
Transaction f: WR
a0 = {Ba,Ra}
b0 = {Bb,Rb}
c0 = {Bc,Rc}
d0 = {Bd,Rd}
e0 = {Be,Re}
e0 = {Bf,Rf}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
c1 = {Bc,Cc1}
d1 = {Bd,Cd1}
e1 = {Be,Ce1}
f1 = {Bf,Cf1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
c2 = {Bc,Cc2}
a2 = {Bd,Cd2}
e2 = {Be,Ce2}
f2 = {Bf,Cf2}
a3 = {Ba}
b3 = {Bb}
c3 = {Bc}
d3 = {Bd}
e3 = {Be}
f3 = {Bf}
Ba,Bb,Bc,Bd,Be
are different
banks.
Bf = Ba
Interleaved Page-empty Write Example
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
CFM
CFMN
RQ11..0
(ACT)
tRC
tCYCLE
ACT
a0
ACT
b0
ACT
c0
ACT
d0
ACT
e0
ACT
f0
RQ11..0
(COL)
tRR
tRCD-R
RD
a1
RD
a2
RD
b1
RD
b2
RD
c1
RD
c2
RD
d1
RD
d2
RD
e1
RD
e2
DQ15..0
DQN15..0
tCAC
tCC
Q(a1)
Q(a2)
Q(b1)
Q(b2)
Q(c1)
Q(c2)
tRDP
tRP
RQ11..0
(PRE)
PRE
a3
PRE
b3
PRE
c3
PRE
d3
RQ11..0
(ALL)
ACT
a0
ACT RD
b0 a1
RD ACT RD PRE RD ACT RD PRE RD ACT RD PRE RD ACT RD PRE RD
a2 c0 b1 a3 b2 d0 c1 b3 c2 e0 d1 c3 d2 f0 e1 d3 e2
Transaction a: RD
Transaction b: RD
Transaction c: RD
Transaction d: RD
Transaction e: RD
a0 = {Ba,Ra}
b0 = {Bb,Rb}
c0 = {Bc,Rc}
d0 = {Bd,Rd}
e0 = {Be,Re}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
c1 = {Bc,Cc1}
d1 = {Bd,Cd1}
e1 = {Be,Ce1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
c2 = {Bc,Cc2}
a2 = {Bd,Cd2}
e2 = {Be,Ce2}
a3 = {Ba}
b3 = {Bb}
c3 = {Bc}
d3 = {Bd}
e3 = {Be}
Ba,Bb,Bc,Bd are
different banks.
Be = Ba
Interleaved Page-empty Read Example
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Read/Write Interaction
The previous section described overlapped read transactions and overlapped write transactions in isolation. This section will
describe the interaction of read and write transactions and the spacing required to avoid channel and core resource conflicts.
Figure12 shows a timing diagram (top) for the first case, a write transaction followed by a read transaction. Two COL packets
with WR commands are presented on cycles T0 and T2. The write data packets are presented a time tCWD later on cycles T4 and
T6. The device requires a time t∆WR after the second COL packet with a WR command before a COL packet with a RD
command may be presented. Two COL packets with RD commands are presented on cycles T11 and T13. The read data
packets are returned a time tCAC later on cycles T17 and T19. The time t∆WR is required for turning around internal bi-directional
interconnections (inside the device). This time must be observed regardless of whether the write and read commands are
directed to same banks or different banks. A gap tWR-BUB XDRDRAM will appear on the DQ bus between the end of the D(a2)
,
packet and the beginning of the Q(b1) packet (measured at the appropriate packet reference points). The size of this gap can be
evaluated by calculating the difference between cycles T2 and T17 using the two timing paths :
tWR-BUB XDRDRAM
In this example, the value of tWR-BUB XDRDRAM
and tCAC are equal to their minimum values.
,
= t∆WR + tCAC - tCWD - tCC
,
is greater than its minimum value of tWR-BUB,XDRDRAM,MIN. The values of t∆WR
In the second case, the timing diagram displayed at the bottom of Figure12 illustrates a read transaction followed by a write
transaction. Two COL packets with RD commands are presented on cycles T0 and T2. The read data packets are returned a
time tCAC later on cycles T6 and T8. The device requires a time t∆RW after the second COL packet with a RD command before a
COL packet with a WR command may be presented. Two COL packets with WR commands are presented on cycles T10 and
T12. The write data packets are presented a time tCWD later on cycles T13 and T15. The time t∆RW is required for turning around
the external DQ bi-directional interconnections (outside the device). This time must be observed regardless whether the read
and write commands are directed to the same banks or different banks. The time t∆RW depends upon four timing parameters.
and may be evaluated by calculating the difference between cycles T2 and T11 using the two timing paths :
t∆RW + tCWD = tCAC + tCC + tRW-BUB, XDRDRAM or t∆RW = (tCAC - tCWD) + tCC + tRW-BUB,
XDRDRAM
In this example, the values of t∆RW, tCAC, tCWD, tCC, and tWR-BUB
,
XDRDRAM are equal to their minimum values.
Figure 12 : Write/Read Interaction
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
tCWD
tDR
tCYCLE
WR
a1
WR
a2
RD
b1
RD
b2
RQ11..0
t
tCAC
∆
WR
DQ15..0
DQN15..0
D(a1)
D(a2)
Q(b1)
Q(b2)
tWR-BUB,
tCWD
tCC
XDRDRAM
Transaction a: WR
Transaction b: RD
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
Write/Read Turnaround Example
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
tCYCLE
RD
a1
RD
a2
WR
b1
WR
b2
RQ11..0
t
tCWD
∆RW
DQ15..0
DQN15..0
Q(a1)
Q(a2)
D(b1)
D(b2)
tCAC
tCC
tRW-BUB,
XDRDRAM
Transaction a: WR
Transaction b: RD
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
Read/Write Turnaround Example
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Propagation Delay
Figure 13 shows two timing diagrams that display the system-level timing relationships between the memory component and the
memory controller.
The timing diagram at the top of the figure shows the case of a write-read-write command and data at the memory component.
In this case, the timing will be identical to what has already been shown in the previous sections; i,e. with all timing measured at
the pins of the memory component. This timing diagram was produced by merging portions of the top and bottom timing
diagrams in Figure12.
The example shown is that of a single COL packet with a write command, followed by a single COL packet with a read
command, followed by a second COL packet with a write command. These accesses all assume a page-hit to an open bank.
A timing interval t∆WR is required between the first WR command and the RD command, and a timing interval t∆RW is required
between the RD command and the second WR command. There is a write data delay tCWD between each WR command and
the associated write data packet D. There is a read data delay tCAC between the RD command and the associated read data
packet Q. In this example, all timing parameters have assumed their minimum values except tWR-BUB XDRDRAM.
,
The lower timing diagram in the figure shows the case where timing skew is present between the memory controller and the
memory component. This skew is the result of the propagation delay of signal wavefronts on the wire carrying the signals.
The example in the lower diagram assumes that there is a propagation delay of tPD-RQ along both the RQ wires and the
CFM/CFMN clock wires between the memory controller and the memory component (the value of tPD-RQ used here is 1*tCYCLE).
Note that in an actual system the tPD-RQ value will be different for each memory component connected to the RQ wires.
In addition, it is assumed that there is a propagation delay tPD-D along the DQ/DQN wires between the memory controller and
the memory component (the direction in which write data travels, and it is assumed that there is the same propagation delay tPD-
along the DQ/DQN wires between the memory component and the memory controller (the direction in which read data
Q
travels). The sum of these two propagation delays is also denoted by the timing parameter tPD,CYC = tPD-D + tPD-Q
.
As a result of these propagation delays, the position of packets will have timing skews that depend upon whether they are
measured at the pins of the memory controller or the pins of memory component. For example, the CFM/CFMN signals at the
points of the memory component are tPD-RQ later than at the pins of the memory controller. This is shown by the cycle
numbering of the CFM/CFMN signals at the two locations - in this example cycle T1 at the memory controller.
All the request packets on the RQ wires will have a tPD-RQ skew at the memory component relative to the memory controller in
this example. Because the tPD-D propagation delay of write data matches the tPD-RQ propagation delay of the write command,
the controller may issue the write data packet D(a0) relative to the COL packet with the first write command “WR(a0)” with
normal write data delay tCWD. If the propagation delays between the memory controller and memory component were different
for the RQ and DQ buses (not shown in this example), the write data delay at the memory controller would need to be adjusted.
A propagation delay is seen by the read command - that is, the read command will be delayed by a tPD-RQ skew at the memory
component relative to the memory controller. The memory componet will return the read data packet Q(b0) relative to this read
command with the normal read data delay tCAC (at the pins of the memory componet).
The read data packet will be skewed by an additional propagation delay of tPD-Q as it travels from the memory component back
to the memory controller. The effective read data delay measured between the read command and the read data at the memory
controller will be tCAC + tPD-RQ + tPD-Q
.
tPD-RQ factor is casued by the propagaion delay of the request packets as they travel from memory controller to memory compo-
nent. The tPD-Q factor is casued by the propagation delay of the read data packets as they travel from memory componet to
memory controller.
All timing parameters will be equal to their minimum values except tWR-BUB XDRDRAM
parameters tRW-BUB XDRDRAM and t∆RW. These will be larger than their minimum values by the amount (tPD CYC
where tPD CYC = tPD-D + tPD-Q. This may be seen by evaluating the two timing paths between cycle T9 at th controller and cycle
21 at the XDR DRAM:
,
(as in the top diagram), and the timing
,
,
- tPD CYC MIN),
,
,
,
T
t
∆RW + tPD-RQ + tCWD = tPD-RQ + tCAC + tCC + tRW-BUB XDRDRAM
,
or t∆RW = (tCAC - tCWD) + tCC + tRW-BUB,XDRDRAM
The following relationship was shown for Figure12.
t∆RW
,
MIN = (tCAC - tCWD) + tCC + tRW-BUB
,
or (t∆RW - t∆RW
,
MIN) = (tRW-BUB
and t∆RW will change together. The relationship of this change to
(=tPD-D + tPD-Q) can be derived by looking at the two timing paths from T15 to T21 at the XDR
,
XDRDRAM - tRW-BUB, XDRDRAM
,
)
XDRDRAM, MIN
MIN
In other words, the two timing parameters tRW-BUB XDRDRAM
the propagation delay tPD CYC
DRAM:
,
,
tPD-Q + tCC + tRW-BUB XIO
,
+ tPD-D = tCC + tRW-BUB,XDRDRAM or tRW-BUB XDRDRAM
,
= tRW-BUB,XIO + tPD-D + tPD-Q or
tRW-BUB XDRDRAM = tRW-BUB XIO
,
,
+ tPD CYC
,
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
in a system with minimum propagation delays:
tRW-BUB XDRDRAM MIN
and since tRW-BUB XIO
(tPD CYC - tPD CYC MIN) = (tRW-BUB XDRDRAM
In other words, the values of the tRW-BUB XDRDRAM MIN
for the system (this is equal to one tCYCLE). As tPD CYC
increase from their minimum values by an equivalent amount.
Figure 13 : Propagation Delay
,
,
= tRW-BUB XIO
is equal to tRW-BUB XIO MIN
- tRW-BUB XDRDRAM MIN
and t∆RW,MIN timing parameters correspond to the value of tPD CYC MIN
,
+ tPD CYC,MIN
in the both cases, the following is true:
) = (t∆RW - t∆RW MIN
,
,
,
,
,
,
,
,
,
,
,
)
,
,
,
,
,
is increased from this minimum value, tRW-BUB XDRDRAM
,
and t∆RW
XDR DRAM
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
WR
a0
RD
b0
WR
c0
RQ11..0
t∆WR
t∆RW
tCWD
DQ15..0
DQN15..0
D(a0)
Q(b0)
D(c0)
tCWD
tCAC
tCC
tCC
tRW-BUB,XDRDRAM
tWR-BUB,XDRDRAM
Transaction a: WR
Transaction b: RD
Transaction c: WR
a0 = {Ba,Ca0}
b0 = {Bb,Cb0}
c0 = {Bc,Cc0}
Write-Read-Write at XDR DRAM
(portions of top and bottom timing diagrams of Figure 12 merged)
Controller
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
CFM
CFMN
tDRW
tCYCLE
tRW-BUB,XIO
WR
a0
RD
b0
WR
c0
tCC
RQ11..0
tDWR
DQ15..0
DQN15..0
D(a0)
Q(b0)
D(c0)
tPD-Q
XDR DRAMT
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
19
20
21 22
-1
CFM
CFMN
tPD-D
tCWD
tPD-RQ
WR
a0
RD
b0
WR
c0
tCYCLE
tPD-D
RQ11..0
tPD-RQ
tPD-RQ
DQ15..0
DQN15..0
D(a0)
Q(b0)
D(c0)
tRW-BUB,XDRDRAM
tCAC
tCWD
tCC
Transaction a: WR
Transaction b: RD
Transaction c: WR
a0 = {Ba,Ca0}
b0 = {Bb,Cb0}
c0 = {Bc,Cc0}
Write-Read-Write at Controller and XDR DRAM
w/ tPD-RQ = tPD-Q = tPD-D = 1*tCYCLE
t
PD-RQ
RQ
Controller
RQ
t
PD-D
XDR DRAM
DQ
DQ
t
PD-Q
Version 1.0 Jan. 2005
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XDR DRAM
Register Operations
Serial Transactions
The serial interface consists of five pins. This includes RST, SCK, CMD, SDI and SDO. SDO uses CMOS signaling levels. The
other four pins use RSL signaling levels. RST, CMD, SDI and SDO use a timing window which surrounds the falling edge of
SCK. The RST pin is used for initialization.
Figure14 and Figure15 show examples of a serial write transaction and a serial read transaction. Each transaction starts on
cycle S4 and requires 32 SCK edges. The next serial transaction can begin on cycle S36. SCK does not need to be asserted if
there is no transaction.
Serial Write Transactions
The serial device write transaction in Figure14 begins with the Start [3:0] field. This consists of bits “1100” on the CMD pin. This
indicates to the XDR DRAM that the remaining 28 bits constitute a serial transaction.
The next two bits are the SCMD[1:0] field. This field contains the serial command, the bits 00 in the case of a serial device write
transaction.
The next eight bits are “00” and the SID[5:0] field. This field contains the serial identification of the device being accessed.
The next eight bits are the SADR[7:0] field. This field contains the serial address of the control register being accessed.
A single bit “0” follows next. This bit allows one cycle for the access time to the control register.
The next eight bits on the CMD pin is the SWD[7:0] field. this is the write data that is placed into the selected control register.
A final bit”0” is driven on the CMD pin to finish the serial write transaction.
A serial broadcast write is identical except that the contents of the SID[5:0] field in the transaction is ignored and all devices
perform the register write. The SDI and SDO pins are not used during either serial write transaction.
Serial Read Transactions
The serial device read transaction in Figure15 begins with the Start[3:0] field. This consists of bits “1100” on the CMD pin. This
indicates that the remaining 28 bits constitute a serial transaction.
The next two bits are the SCMD [1:0] field. This field contains the serial command, and the bits “10” in the case of a serial device
read transaction.
The next eight bits are “00” and the SID [5:0] field. This field contains the serial identification of the device being accessed.
The next eight bits are the SADR [7:0] field and contain the serial address of the control register being accessed.
A single bit “0” follows next. This bit allows one cycle for the access time to the control register and time to turn on the SDO
output driver.
The next eight bits on the CMD pin are the sequence “00000000”. At the same time, the eight bits on the SDO pin are the SRD
[7:0] field. This is the read data that is accessed from the selected control register. Note the output timing convention here: bit
SRD [7] is driven from a time tQ,SI,MAX after edge S26 to a time tQ,SI,MIN after edge S27. The bit is sampled in the controller by the
edge S27
.
A final bit “0” is driven on the CMD pin to finish the serial read transaction.
A serial forece read is identical except that the contents of the SID [5:0] field in the transaction is ignored and all devices perform
the register read. This is used for device testing.
Figure16 shows the response of a DRAM to a serial device read transaction when its internal SID [5:0] register field doesn’t
match the SID [5:0] field of the transaction. Instead of driving read data from an internal register for cycle edges S27 through S34
on the SDO output pin, it passes the input data from the SDI input pin to the SDO output pin during this same period.
Table 9: SCMD Field Encoding Summary
SCMD[1:0]
Command
DESCRIPTION
Serial device write-one device is written, the one whose SID[5:0] register matches the
SID[5:0] field of the transaction.
00
SDW
Serial broadcast write - all devices are written, regardless of the contents of the SID [5:0]
register and the SID [5:0] transaction field.
01
10
11
SBW
SDR
SFR
Serial device read - one device is read, the one whose SID[5:0] register matches the
SID[5:0] field of the transaction.
Serial forced read - all devices are read, regardless of the contents of the SID[5:0] regis-
ter and the SID[5:0] transaction field
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Figure 14 : Serial Write Transaction
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
0
0
0
2
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
36
36
38
38
38
40
40
40
42
42
42
44
44
44
46
46
46
48
48
48
SCK
RST
tCYC,SCK
transaction
Start
2’h0,SID[5:0]
5
SADR[7:0]
5
SWD[7:0]
4 3 2 1 0
‘0’
SCMD
CMD
‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’‘0’ ‘0’
4
3
2
1
0
7
6
4
3
2
1
0
7
6
5
‘0’
SDI
(input)
SDO
(output)
Figure 15 : Serial Read Transaction — Selected DRAM
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
SCK
RST
tCYC,SCK
transaction
Start
2’h0,SID[5:0]
5
SADR[7:0]
5
8’h00
‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ’0’ ‘0’ ‘0’
SCMD
CMD
‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘0’‘0’ ‘0’
4
3
2
1
0
7
6
4
3
2
1
0
‘0’
‘0’
SDI
(input)
SDO
(output)
SRD[7:0]
4 3 2 1 0
7
6
5
Figure 16 : Serial Read Transaction — Non-selected DRAM
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
SCK
RST
S
28
tCYC,SCK
SDI
transaction
t
P,SI
Start
2’h0,SID[5:0]
SADR[7:0]
8’h00
SCMD
CMD
‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘0’‘0’ ‘0’
5
4
3
2
1
0
7
6
5
4
3
2
1
0
‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ’0’ ‘0’ ‘0’
‘0’
‘0’
SDO
SDI
(input)
SRD[7:0]
combinational
propagation
from SDI to SDO
7
6
6
5
4
3
2
1
1
0
0
SDO
(output)
SRD[7:0]
5
4 3 2
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Register Summary
Figure17 through Figure42 show the control register in the memory component. The control registers are responsible for config-
uring the component’s operating mode, for managing power state transactions, for managing refresh, and for managing calibra-
tion operations.
A control register may contain up to eight bits. Each figure shows defined bits in white and reserved bits in gray. Reserved bits
must be written as 0 and must be ignored when read. Write-only fields must be ignored when read .
Each figure displays the following register information:
1. Register name
2. Register mnemonic
3. Register address (SADR [7:0] value needed to access it)
4. Read-only, write-only or read-write
5. Initialization state
6. Description of each defined register field
Figure17 shows the Serial Identification register. The register contains the SID [5:0] (serial identification field). This field contains
the serial identification value for the deice. The value is compared to the SID[5:0] field of a serial transaction to determine if the
serial transaction is directed to this device. The serial identification value is set during the initialization sequence.
Figure18 shows the Configuration Register. It contains three fields. The first is the WIDTH field. This field allows the number of
DQ/DQN pins used for memory read and write accesses to be adjusted. The SLE field enables data to be written into the
memory through the serial interface using the WDSL register.
Figure19 shows the Power Management Register. It contains two fields. The first is the PX field. When this field is written with a
“1”, the memory component transactions from powerdown to active state. It is usually unnecessary to write a “0” into this field;
this is done automatically by the PDN command in a COLX packet. The PST field indicates the current power state of the
memory component.
Figure20 shows the Write Data Serial Load Register. It permits data to be written into memory via the Serial Interface.
Figure23 shows the Refresh Bank Control Register. It contains two fields: BANK and MBR. The BANK field is read-write and
contains the bank address used by self-refresh during the powerdown state. The MBR field controls how many banks are
refreshed during each refresh operation. Figure24, Figure25 and Figure26 show different fields of the Refresh Row Register
(high, middle and low). This read-write field contains the row address used by self- and auto-refresh. See”Refresh Transactions”
on page 37 for more details.
Figure28 and Figure29 show the Current Calibration 0 and 1 registers. They contain the CCVALUE0 and CCVALUE1 fields,
respectively. These are read-write fields which control the amount of IOL current driven by the DQ and DQN pins during a read
transaction. The Current Calibration 0 Register controls the even-numbered DQ and DQN pins, and the Current Calibration 1
controls the odd-numbered DQ and DQN pins.
Figure30 and Figure31 show the Impedance Calibration 0 and 1 registers. They contain the ZCVALUE0 and ZCVALUE1 field,
respectively. These are read-write fields that control the impedance of the on-chip termination components in the DQ and DQN
pins. The Impedance Calibration 0 Register controls the even-numbered DQ and DQN pins, and the Impedance Calibration 1
controls the odd-numbered DQ and DQN pins.
Figure 36 through Figure 41 and Figure 43 shows the test registers. This includes the TEST, DLL, PLL0, PLL1, IFT, DA and
PARTn registers. These are used during device testing. They are not to be read or written during normal operation.
Figure42 shows the DLY register. This is used to set the value of tCAC and tCWD used by the component. See “Timing Parame-
ters” on page59.
Figure 17 : Serial Identification (SID) Register
7
6
5
4
3
2
1
0
Serial Identification Register
SADR[7:0]: 000000012
Read-only register
SID[7:0] resets to 000000002
SID[5:0]
reserved
SID[5:0] - Serial Identification field.
This field contains the serial identification value for the device.
The value is compared to the SID[5:0] field of a serial transac-
tion to determine if the serial transaction is directed to this
device. The serial identification value is set during the initializa-
tion sequence.
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Figure 18 : Configuration (CFG) Register
7
6
5
4
3
2
1
0
Configuration Register
SADR[7:0]: 000000102
Read/write register
CFG[7:0] resets to 000001002
SLE
WIDTH[2:0]
rsrv
rsrv
rsrv
WIDTH[2:0] - Device interface width field.
0002 - Reserved.
0012 - Reserved
0102 - x4 device width
0112 - x8 device width
1002 - x16 device width
1012, 1102, 1112 - Reserved
SLE - Serial Load enable field.
02 - WDSL-path-to-memory disabled
12 - WDSL-path-to-memory enabled
Figure 19 : Power Management (PM) Register
7
6
5
4
3
2
1
0
Power Management Register
SADR[7:0]: 000000112
Read/write register
PM[7:0] resets to 000000002
PST[1:0]
PX
reserved
PX - Powerdown exit field.(write-one-only, read=zero)
02 - Powerdown entry - do not write zero - use PDN command
12 - Powerdown exit - write one to exit
PST[1:0] - Power state field (read-only).
002 - Powerdown (with self-refresh)
012 - Active/active-idle
102 - reserved
112 - reserved
Figure 20 : Write Data Serial Load (WDSL) Control Register
7
6
5
4
3
2
1
0
Write Data Serial Load Control Register
Read/write register
SADR[7:0]: 000001002 WDSL[7:0] resets to 000000002
WDSD[7:0]
WDSD[7:0] - Writing to this register places eight bits of data into
the serial-to-parallel conversion logic (the “Demux” block of
Figure 2). Writing to this register “2x16” times accumulates a full
“tCC” worth of write data. A subsequent WR command (with
SLE=1 in CFG register in Figure 1) will write this data (rather
than DQ data) to the sense amps of a memory bank. The shift-
ing order of the write data is shown in Table 11.
Figure 21 : RQ Scan High (RQH) Register
7
6
5
4
3
2
1
0
RQ Scan High Register
SADR[7:0]: 000001102
Read/write register
RQH[7:0] resets to 000000002
RQH[3:0]
reserved
RQH[3:0] - Latched value of RQ[11:8] in RQ wire test mode.
Version 1.0 Jan. 2005
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XDR DRAM
Figure 22 : RQ Scan Low (RQL) Register
7
6
5
4
3
2
1
0
RQ Scan Low Register
SADR[7:0]: 000001112
Read/write register
RQL[7:0] resets to 000000002
RQL[7:0]
RQL[7:0] - Latched value of RQ[7:0] in RQ wire test mode.
Figure 23 : Refresh Bank (REFB) Control Register
7
6
5
4
3
2
1
0
Refresh Bank Control Register
SADR[7:0]: 000010002
Read/write register
REFB[7:0] resets to 000000002
MBR[1:0]
BANK[2:0]
reserved
BANK[2:0] - Refresh bank field.
This field returns the bank address for the next self-refresh
operation when in Powerdown power state.
MBR[1:0] - Multi-bank and multi-row refresh control field.
002 - Single-bank refresh.
012 - Reserved
102 - Reserved
112 - Reserved
Figure 24 : Refresh High (REFH) Row Register
7
6
5
4
3
2
1
0
Refresh High Row Register
SADR[7:0]: 000010012
Read/write register
REFH[7:0] resets to 000000002
reserved
reserved - Refresh row field.
This field contains the high-order bits of the row address that
will be refreshed during the next refresh interval. This row
address will be incremented after a REFI command for auto-
refresh, or when the BANK[2:0] field for the REFB register
equals the maximum bank address for self-refresh.
Figure 25 : Refresh Middle (REFM) Row Register
7
6
5
4
3
2
1
0
Refresh Middle Row Register
SADR[7:0]: 000010102
Read/write register
REFM[7:0] resets to 000000002
R[10:8]
reserved
R[10:8] - Refresh row field.
This field contains the middle-order bits of the row address that
will be refreshed during the next refresh interval. This row
address will be incremented after a REFI command for auto-
refresh, or when the BANK[2:0] field for the REFB register
equals the maximum bank address for self-refresh.
Version 1.0 Jan. 2005
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Figure 26 : Refresh Low (REFL) Row Register
7
6
5
4
3
2
1
0
Refresh Low Row Register
SADR[7:0]: 000010112
Read/write register
REFL[7:0] resets to 000000002
R[7:0]
R[7:0] - Refresh row field.
This field contains the low-order bits of the row address that will
be refreshed during the next refresh interval. This row address
will be incremented after a REFI command for auto-refresh, or
when the BANK[2:0] field for the REFB register equals the max-
imum bank address for self-refresh.
Figure 27 : IO Configuration (IOCFG) Register
7
6
5
4
3
2
1
0
IO Configuration Register
SADR[7:0]: 000011112
Read/write register
IOCFG[7:0] resets to 000000002
ODF[1:0]
reserved
ODF[1:0] - Overdrive Function field.
00 - Nominal VOSW,DQ range
01 - reserved
10 - reserved
11 - reserved
Figure 28 : Current Calibration 0 (CC0) Register
7
6
5
4
3
2
1
0
Current Calibration 0 Register
SADR[7:0]: 000100002
Read/write register
CC0[7:0] resets to vvvvvvvv2
(vendor-dependent reset value)
CCVALUE0[5:0]
reserved
CCVALUE0[5:0] - Current calibration value field.
This field controls the amount of current drive for the even-num-
bered DQ and DQN pins.
Figure 29 : Current Calibration 1 (CC1) Register
7
6
5
4
3
2
1
0
Current Calibration 1 Register
SADR[7:0]: 000100012
Read/write register
CC1[7:0] resets to vvvvvvvv2
CCVALUE1[5:0]
reserved
(vendor-dependent reset value)
CCVALUE1[5:0] - Current calibration value field.
This field controls the amount of current drive for the odd-num-
bered DQ and DQN pins.
Figure 30 : Impedance Calibration 0 (ZC0) Register
7
6
5
5
4
3
2
1
0
Impedance Calibration 0 Register
SADR[7:0]: 000100102
Read/write register
ZC0[7:0] resets to 000000002
reserved
reserved
Figure 31 : Impedance Calibration 1 (ZC1) Register
7
6
4
3
2
1
0
Impedance Calibration 1 Register
SADR[7:0]: 000100112
Read/write register
ZC1[7:0] resets to 000000002
reserved
reserved
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Figure 32 : Current Fuse Setting 0 (FZC0) Register
7
6
5
5
5
4
3
2
1
0
Current Fuse Setting Register
SADR[7:0]: 000101002
Read-only register
FZC0[7:0] resets to vvvvvvvv
reserved
(vendor-dependent reset value)
reserved
Figure 33 : Current Fuse Setting 1 (FZC1) Register
7
6
4
3
2
1
0
Current Fuse Setting Register
SADR[7:0]: 000101012
Read-only register
FZC1[7:0] resets to vvvvvvvv
(vendor-dependent reset value)
reserved
reserved
Figure 34 : Read Only Memory 0 (ROM0) Register
7
6
4
3
3
3
2
1
0
Read Only Memory 0 Register
SADR[7:0]: 000101102
Read-only register
ROM0[7:0] resets to vvvvmmmm
VENDOR[3:0]
MASK[3:0]
MASK[3:0] - Version number of mask (00012 is first version).
VENDOR[3:0] - Vendor number for component:
0000 - reserved
0001 - Toshiba
0010 - Elpida
0011 - SEC
0100-1111-reserved
Figure 35 : Read Only Memory 1 (ROM1) Register
7
6
5
4
2
1
0
Read Only Memory 1 Register
SADR[7:0]: 000101112
Read-only register
ROM0[7:0] resets to bbrrrccc
BB[1:0]
RB[2:0]
CB[2:0]
CB[2:0] - Column address bits: #bits = 6 +CB[2:0]
RB[2:0] - Row address bits:
BB[2:0] - Bank address bits:
These three fields indicate how many column, row, and bank
address bits are present. An offset of {6,10,2} is added to the
field value to give the number of address bits.
#bits = 10 +RB[2:0]
#bits = 2 +BB[2:0]
Figure 36 : TEST Register
7
6
5
4
2
reserved
1
0
TEST Register
SADR[7:0]: 000110002
Read/write register
TEST[7:0] resets to 000000002
WTL WTE
WTE - Wire Test Enable
WTL - Wire Test Latch
Figure 37 : DLL Register
7
6
5
4
3
2
1
0
DLL Register
Read/write register
SADR[7:0]: 000110012
DLL[7:0] resets to 000000002
reserved
TBD
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Figure 38 : PLL0 Register
7
7
7
6
6
6
5
5
5
4
3
2
2
2
1
1
1
1
0
PLL0 Register
SADR[7:0]: 000110102
Read/write register
PLL0[7:0] resets to 000000002
reserved
TBD
Figure 39 : PLL1 Register
4
3
0
PLL1 Register
SADR[7:0]: 000110112
Read/write register
PLL1[7:0] resets to 000000002
reserved
TBD
Figure 40 : IFT Register
4
3
0
IFT Register
SADR[7:0]: 000111002
Read/write register
IFT[7:0] resets to 000000002
reserved
TBD
Figure 41 : DA Register
7
7
6
6
5
5
4
3
2
2
0
DA Register
SADR[7:0]: 000111012
Read/write register
DA[7:0] resets to 000000002
reserved
TBD
Figure 42 : Delay (DLY) Control Register
4
3
1
0
DLY Register
Read/write register
SADR[7:0]: 000111112
DLY[7:0] resets to 001101102
CWD[3:0]
CAC[3:0]
CAC[3:0] - Programmed value of tCAC timing parameter:
01102 - tCAC = 6*tCYCLE 10002 - tCAC = 8*tCYCLE
01112 - tCAC = 7*tCYCLE others - Reserved.
CWD[3:0] - Programmed value of tCWD timing parameter:
00112 - tCWD = 3*tCYCLE
01002 - tCWD = 4*tCYCLE others - Reserved.
Figure 43 : Partner-Definable (PART0-PARTF) Registers
7
7
6
6
5
5
4
3
2
1
0
PART0 Register
SADR[7:0]: 100000002
Read/write register
PART0[7:0] resets to 000000002
reserved
4
3
2
1
0
PART1 Register
SADR[7:0]: 100000012
Read/write register
PART1[7:0] resets to 000000002
reserved
7
6
5
4
3
2
1
0
PARTF Register
SADR[7:0]: 100011112
Read/write register
PARTF[7:0] resets to 000000002
reserved
Note - The partner-definable registers should not be written or read; doing so will produce undefined results.
Version 1.0 Jan. 2005
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XDR DRAM
Maintenance Operations
Refresh Transactions
Figure44 contains two timing diagrams showing examples of refresh transactions. The top timing diagram shows a single
refresh operation. Bank Ba is assumed to be closed (in a precharged state) when a REFA command is received in a ROWP
packet on clock edge T0. The REFA command causes the row addressed by the REFr register (REFH/REFM/REFL) to be
opened (sensed) and placed in the sense amp array for the bank.
Note that the REFA and REFI commands are similar to the ACT command functionally; both specify a bank address and delay
value, and both cause the selected bank to open (to become sensed.). The difference is that the ACT command is accompanied
by a row address in the ROWA packet, while the REFA and REFI commands use a row address in the REFr register
(REFH/REFM/REFL).
After a time tRAS, a ROWP packet with REFP command to bank Ba is presented. This causes the bank to be closed
(precharged), leaving the bank in the same state as when the refresh transaction began.
Note that the REFP command is equivalent to the PRE command functionally; both specify a bank address and delay value, and
both cause the selected bank to close (to become precharged).
After a time tRP, another ROWP packet with REFA command to bank Bb is presented (banks Ba and Bb are the same in this
example). This starts a second refresh cycle. Each refresh transaction requires a total time tRC = tRAS + tRP, but refresh transac-
tions to different banks may be interleaved like normal read and write transactions.
Each row of each bank must be refreshed once in every tREF interval. This is shown with the fourth ROWP packet with a REFA
command in the top timing diagram.
Interleaved Refresh Transaction
The lower timing diagram in Figure44 represents one way a memory controller might handle refresh maintenance in a real
system.
A series of eight ROWP packets with REFA commands (except for the last which is a REFI command) are presented starting at
edge T0. The packets are spaced with intervals of tRR. Each REFA or REFI command is addressed to a different bank (Ba
through Bh) but uses the same row address from the REFr (REFH/REFM/REFL) register. The eighth REFI command uses this
address and then increments it so the next set of eight REFA/REFI commands will refresh the next set of rows in each bank.
A series of eight ROWP packets with REFP commands are presented effectively at edge T10 (a time tRAS after the first ROWP
packet with a REFA command). The packets are spaced with intervals of tPP. Like the REFA/REFI commands, each REFP
command is addressed to a different bank (Ba through Bh).
This burst of eight refresh transactions fully utilizes the memory component. However, other read and write transactions may be
interleaved with the refresh transactions before and after the burst to prevent any loss of bus efficiency. In other words, a ROWA
packet with ACT command for a read or write could have been presented at edge T4 (a time tRR before the first refresh transac-
tion starts at edge T0). Also, a ROWA packet with ACT command for a read or write could have been presented at edge T36 (a
time tRR after the last refresh transaction starts at edge T32). In both cases, the other request packets for the interleaved read or
write accesses (the precharge commands and the read or write commands) could be slotted in among the request packets for
the refresh transaction.
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
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Figure 44 : Refresh Transactions
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
18
19
20
21
22 23
CFM
CFMN
tRP
tRAS
tCYCLE
REFA
a0
REFP
a1
REFA
b0
REFA
c0
RQ11..0
tRC
DQ15..0
DQN15..0
tREF
Transaction a: REF
Transaction b: REF
Transaction c: REF
a0 = {Ba,REFR}
a0 = {Ba,REFR}
c0 = {Bc,REFR}
a1 = {Ba}
b1 = {Bb}
c1 = {Bc}
Refresh Transaction
Bb = Ba
Bc/Rc = Ba/Ra
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
CFM
CFMN
RQ11..0
(ACT)
tRR
REFA
a0
REFA
b0
REFA
c0
REFA
d0
REFA
e0
REFA
f0
RQ11..0
(PRE)
REFP
a1
REFP
b1
REFP
c1
REFP
d1
RQ11..0
(ALL)
REFA
a0
REFA
b0
REFA
c0
REFP
a1
REFA
d0
REFP
b1
REFA
e0
REFP
c1
REFA
f0
REFP
d1
DQ15..0
DQN15..0
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46 47
CFM
This REFI increments REFR
CFMN
RQ11..0
(ACT)
tCYCLE
REFA
g0
REFI
h0
REFA
i0
RQ11..0
(PRE)
REFP
e1
REFP
f1
REFP
g1
REFP
h1
RQ11..0
(ALL)
REFA
g0
REFP
e1
REFA
h0
REFP
f1
REFA
i0
REFP
g1
REFP
h1
DQ15..0
DQN15..0
Interleaved Refresh Example
Transaction a: REF
Transaction b: REF
Transaction c: REF
Transaction d: REF
Transaction e: REF
Transaction f: REF
Transaction g: REF
Transaction h: REF
Transaction i: REF
a0 = {Ba,REFR}
b0 = {Bb,REFR}
c0 = {Bc,REFR}
d0 = {Bd,REFR}
e0 = {Be,REFR}
f0 = {Bc,REFR}
g0 = {Bd,REFR}
h0 = {Be,REFR}
i0 = {Ba,REFR+1}
a1 = {Ba}
b1 = {Bb}
c1 = {Bc}
d1 = {Bd}
e1 = {Be}
f1 = {Bf}
g1 = {Bg}
h1 = {Bh}
i1 = {Bi}
Ba,Bb,Bc,Bd,
Be,Bf,Bg and
Bh are
different banks.
Bi = Ba
Version 1.0 Jan. 2005
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XDR DRAM
Calibration Transactions
Figure45 shows the calibration transaction diagrams for the XDR DRAM device. There is one calibration operation supported:
calibration of the output current level IOL, each DQi and DQNi pin.
The output current calibration sequence is shown in the upper diagram. It begins when a period of tCMD-CALC is observed after
the last RQ packet (with command “CMD a” in this example). No request packets should be issued in this period.
A COLX packet with a “CALC b” command is then issued to start the current calibration sequence. A period of tCALCE is
observed after this packet. No request packets should be issued during this period.
A COLX packet with a “CALE c” command is then issued to end the current calibration sequence. A period of tCALE-CMD is
observed after this packet. No request packets should be issued during this period. The first request packet may then be issued
(with command “CMD d” in this example).
A second current calibration sequence must be started within an interval of tCALC. In this example. the next COLX packet with a
“CALC e” command starts a subsequent sequence.
The dynamic termination calibration sequence is shown in the lower diagram. Note that this memory component does not use
this sequence; termination calibraion is performed during the manufacturing process. However, the termination sequence shown
will be issued by the controller for those memory component which do use a periodic calibration mechanism.
It begins when a period of tCMD-CALZC is observed after the packet edge T0(with command CMDa in this example). No request
packets should be issued in this period.
A COLX packet with a CALZ command is then issued at edge T3 to start the current calibration sequence. A second period of
t
CALZE is ovserved after this packet. No request packets should be issued during this period.
A COLX packet with a CALE command is then issued at dege T6 to end the current calibration sequence. A third period of tCALE-
is observed after this pakets. No request packets should be issued during this period. The first request pakcet may be
CMD
issued at edge T12(with command CMDd in this example).
A second current calibration sequence must be started within an interval of tCALZ. In this example, the next COLX pakcet with a
CALZ command occurs at edge T20
.
Note that the labels for the CFM clock edges(of the form Ti) are not to scale, and are used to identify events in the diagrams.
Figure 45 : Calibration Transactions
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
1
18
19
20
21
22 23
CFM
CFMN
t
CALCE,CALE
c
tCALE-CMD,
tCYCLE
CMD
a
CMD
d
CALC
e
CALC
b
RQ11..0
R
tCMD-CALC
DQ15..0
DQN15..0
tCALC
Packet a: Any CMD
Packet b: CALC
Packet c: CALE
Current Calibration Transaction
Packet d: Any CMD
Packet e: CALC
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
1
18
19
20
21
22 23
CFM
CFMN
t
CALZE,CALE
c
tCALE-CMD,
tCYCLE
CMD
a
CMD
d
CALZ
b
CALZ
e
RQ11..0
tCMD-CALZ
DQ15..0
DQN15..0
tCALZ
Packet a: Any CMD
Packet b: CALZ
Packet c: CALE
Termination Calibration Transaction
Packet d: Any CMD
Packet e: CALZ
Version 1.0 Jan. 2005
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XDR DRAM
Power State Management
Figure46 shows power state transition diagrams for the XDR DRAM device. There are two power states in the XDR DRAM:
Powerdown and Active. Powerdown state is to be used in applications in which it is necessary to shut down the CFM/CFMN
clock signals. In this state, the contents of the storage cells of the XDR DRAM will be retained by an internal state machine
which performs periodic refresh operations using the REFB and REFr control registers.
The upper diagram shows the sequence needed for Powerdown entry. Prior to starting the sequence, all banks of XDR DRAM
must be precharged so they are left in a closed state. Also, all 23 banks must be refreshed using the current value of the REFr
registers, and the REFr registers must not be incremented with the REFI command at the end of this special set of refresh trans-
actions. This ensures that no matter what value has been left in the REFB register, no row of any bank will be skipped when
automatic refresh is first started in Powerdown. There may be some banks at the current row value in the REFr registers that are
refreshed twice during the Powerdown entry process.
After the last request packet (with the command CMDa in the upper diagram of the figure), an interval of tCMD-PDN is observed.
No request packets should be issued during this period.
A COLX packet with the PDN command is issued after this interval, causing the XDR DRAM to enter Powerdown state after an
interval of tPDN-ENTRY has elapsed (this is the parameter that should be used for calculating the power dissipation of the XDR
DRAM). The CFM/CFMN clock signals may be removed a time tPDN-CFM after the COLX packet with the PDN command. Also,
the termination voltage supply may be removed (set to the ground reference) from the Vterm pins a time tPDN-CFM after the
COLX pakcet with the PDN command. The voltage on the DQ/DQN pins will follow the voltae on the Vterm pins during Power-
donwn entry.
When the XDR DRAM is in Powerdown, an internal frequency source and state machine will automatically generate internal
refresh transactions. It will cycle through all 23 state combinations of the REFB register. When the largest value is reached and
the REFB value wraps around, the REFr register is incremented to the next value. The REFB and REFr values select which
bank and which row are refreshed during the next automatic refresh transaction.
The lower diagram shows the sequence needed for Powerdown exit. The sequence is started with a serial broadcast write
(SBW command) transaction using the serial bus of the XDR DRAM. This transaction writes the value “00000001” to the Power
Management (PM) register (SADR = “00000011”) of all XDR DRAMs connected to the serial bus. This sets the PX bit of the PM
register, causing the XDR DRAMs to return to Active power state.
The CFM/CFMN clock signals must be stable a time tCFM-PDN before the end of the SBW transaction. Also, the termination
voltage supply must be restored to its normal operating point (VTERM,DRSL) on the Vterm pins a time tCFM-PDN before the end of
the SWB transaction. The voltage on the DQ/DQN pins will follow the voltage on the Vterm pins during Powerdown exit.
The XDR DRAM will enter Active state after an interval of tPDN-EXIT has elapsed from the end of the SBW transaction (this is the
parameter that should be used for calculating the power dissipation of the XDR DRAM).
The first request packet may be issued after an interval of tPDN-CMD has elapsed from the end of the SBW transaction, and must
contain a “REFA” command in a ROWP packet. In this example, this packet is denoted with the command “REFA 1”. No other
request packets should be issued during this tPDN-CMD interval.
All “n” banks (in the example, n=23) must be refreshed using the current value of the REFr registers. The “nth” refresh transac-
tion will use a “REFI” command to inrement the REFr register (instead of a “REFR” command). This ensures that no matter what
value has been left in the REFB register, no row of any bank will be skipped when normal refresh is restarted in Active state.
There may be some banks at the current row value in the REFr registers that are refreshed twice during the Powerdown exit
process.
Note that during the Powerdown state an internal time source keeps the device refreshed. However, during the tPDN-CMD
interval, no internal refresh operations are performed. As a result, an additional burst of refresh transactions must be issued
after the burst of “n” transactions described above. This second burst consists of “m” refresh transactions:
m = ceiling[23*211*tPDN-CMD/tREF
]
Where “211” is the number of rows per bank, and “23” is the number of banks. Every ”nth” refresh transaction (where n=23) will
use a “REFI” command (to increment the REFr register) instead of a “REFA” command.
Version 1.0 Jan. 2005
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XDR DRAM
Figure 46 : Power State Management
CFM
CFMN
No signal
tPDN-CFM
tCYCLE
CMD
a
PDN
b
RQ11..0
Powerdown State...
DQ15..0
DQN15..0
tPDN-ENTRY
tCMD-PDN
Transaction a: Last precharge command
Transaction b: PDN
Powerdown Entry
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32 34
SCK
RST
tCYC,SCK
Power-up transaction
Start
‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’
SCMD
2’h0,SID[5:0]
‘0’ ‘0’
SADR[7:0]
SWD[7:0]
CMD
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
‘0’
‘0’
SDI
(input)
SDO
(output)
CFM
CFMN
No signal
tCYCLE
tCFM-PDN
tPDN-EXIT
RQ11..0
....Powerdown State
DQ15..0
DQN15..0
tPDN-CMD
CFM
CFMN
tCYCLE
REFP
n-1
REFP
n
REFA
1
REFA
2
REFI
n
REFP
n-2
RQ11..0
DQ15..0
DQN15..0
tPDN-CMD
The final REFA/REFI command increments the REFr register
Transaction 1: REFA
Transaction 2: REFA
Transaction n-1: REFA
Transaction n: REFI
Powerdown Exit
Version 1.0 Jan. 2005
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XDR DRAM
Initialization
Figure47 shows the topology of the serial interface signals of a XDR DRAM system. The three signals RST, CMD, and SCK are
transmitted by the controller and are received by each XDR DRAM device along the bus. The signals are terminated to the
VTERM supply through termination components at the end farthest from the controller. The SDI input of the XDR DRAM device
furthest from the controller is also terminated to VTERM. The SDO output of each XDR DRAM device is transmitted to the SDI
input of the next XDR DRAM device (in the direction of the controller). This SDO/SDI daisy chain topology continues to the
controller, where it ends at the SRD input of the controller. All the serial interface signals are low-true. All the signals use RSL
signaling circuits, except for the SDO output which uses CMOS signaling circuits.
Figure 47 : Serial Interface Systems Topology
VTERM
RST CMD SCK
RST CMD SCK
RST CMD SCK
RST CMD SCK
...
...
SRD
SDO
SDI
SDO
SDI
SDO
SDI
Controller
XDRDRAM
XDRDRAM
XDRDRAM
Figure48 shows the initialization timing of the serial interface for the XDR DRAM [k] device in the system shown above. Prior to
initialization, the RST is held at zero. The CMD input is not used here, and should also be held at zero. Note that the inputs are
all sampled by the negative edge of the SCK clock input. The SDI input for the XDR DRAM[0] device is zero, and is unknown for
the remaining devices.
On negative SCK edge S8 the RST input is sampled one. It is sampled one on the next four edges, and is sampled zero on edge
S12 a time tRST-10 after it was first sampled one. The state of the control registers in the XDR DRAM device are set to their reset
values after the first edge (S8) in which RST is sampled one.
Figure 48 : Initialization Timing for XDR DRAM [k] Device
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44 46
48
SCK
RST
tCYC,SCK
tRST-10
‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
tRST-SDI,00
= k * tCYC,SCK
CMD
SDI
(input)
‘x’ ‘x’ ‘x’ ‘x’ ‘x’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
tRST-SDO,11
tSDI-SDO,00
SDO
(output)
‘x’ ‘x’ ‘x’ ‘x’ ‘x’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
The SDI inputs will be sampled one within a time tRST-SDO,11 after RST is first sampled one in all the XDR DRAMs except for
XDR DRAM [0]. XDR DRAM [0]’s SDI input will always be sampled zero.
XDR DRAM [k] will see its RST input sampled zero at S12, and will then see its SDI input sampled zero at S16 (after SDI had
previously been sampled one). This interval (measured in tCYC,SCK units) will be equal to the index [k] of the XDR DRAM device
along the serial interface bus. In this example, k is equal to 4.
This is because each XDR DRAM device will drive its SDO output zero around the SCK edge a time tSDI-SDO 00
,
after its SDI
input is sample zero.
In other words, the XDR DRAM [0] device will see RST and SDI both sampled zero on the same edge S12 (tRST-SDI 00
,
will be 0
*tCYC,SCK units), and will drive its SDO to zero around the subsequent edge (S13).
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
The XDR DRAM [1] device will see SDI sampled zero on edge S13 (tRST-SDI 00
,
will be 1*tCYC,SCK units), and will drive its SDO to
zero around the subsequent edge (S14).
The XDR DRAM [2] device will see SDI sampled zero on edge S14 (tRST-SDI,00 will be 2* tCYC,SCK units), and will drive its SDO
to zero around the subsequent edge (S15).
This continues until the last XDR DRAM device drives the SRD input of the controller. Each XDR DRAM device contains a state
machine which measures the interval tRST-SDI,00 between the edges in which RST and SDI are both sampled zero, and uses this
value to set the SID [5:0] field of the SID (Serial Identification) register. This value allows directed read and write transactions to
be made to the individual XDR DRAM devices.
Table 10 summarizes the range of the timing parameters used for initialization by the serial interface bus.
Table 10 : Initialization Timing Parameters
Symbol
Parameter
Min Max
Unit
Figure (s)
Number of cycles between RST being sampled one and RST being
sampled zero
tRST,10
2
1
-
tCYC,SCK
-
Number of cycles between RST being sampled one and SDO being
driven to one
tRST-SDO,11
1
tCYC,SCK
-
-
Number of cycles between RST being sampled zero (after being sam-
pled one for tRST,10,MIN or more cycles) and SDI being sampled zero.
This will be equal to the index [k] of the XDR DRAM device along the
serial interface bus
tRST,SDI,00
0
63
tCYC,SCK
Number of cycles between SDI being sampled one (after RST has
tSDI-SDO,00 been sampled one for tRST,10,MIN or more cycles and is then sampled
zero) and SDO being driven to zero
1
1
-
tCYC,SCK
tCYC,SCK
-
-
tRST-SCK
Asynchronous reset interval.
20
XDR DRAM Initialization Overview
[1] Apply voltage to VDD, VTERM, and VREF pins. VTERM and VREF voltages must be less or equal to VDD voltage at all
times. Wait a time interval tCOREINIT. Power-on reset circuit in XDR DRAM places XDR DRAM into low-power state.
[2] Assert RST, SCK, SDI and CMD to logical zero, Then:
- Pulse SCK to logical one, then to logical zero four times.
- Assert RST to logical one. Reset circuit places XDR DRAM into low-power state(identical to power-on reset)
- Perform remaining initialization sequence in Figure 48.
[3] XDR DRAM has valid Serial ID and all registers have default values that are defined in Figure17 through Figure42.
[4] Perform broadcast or directed register writes to adjust registers which need a value different from their default value.
[5] Perform Powerdown Exit sequence shown in Figure46. This includes the activity from SCK cycle S0 through the final REFP
command.
[6] Perform termination/current calibration. The CALZ /CALE sequence shown in Figure 45 is issued 128 times. After this, each
sequence is issued once every tCALZ or tCALC interval.
[7] Condition the XDR DRAM banks by performing a REFA/REFI activate and REFP precharge operation to each bank eight
times. This can be interleaved to save time. The row address for the activate operation will step through eight successive values
of the REFr registers. The sequence between cycles T0 and T32 in the Interleaved Refresh Example in Figure 44 could be
performed eight times to satisfy this conditioning requirement.
XDR DRAM Pattern Load with WDSL Register
The XDR memory system requires a method of deterministically loading pattern data to XDR DRAMs before beginning Receive
Timing Calibration (RX TCAL). The method employed by the XDR DRAMs to achieve this is called Write Data Serial Load
(WDSL). A WDSL packet sends one-byte of serial data which is serially shifted into a holding register within the XDR DRAM.
Initialization software sends a sequence of WDSL packets, each of which shifts the new byte in and advances the shifter by 8
positions. In this way, XDR DRAMs of varying widths can be loaded with a single command type.
Each sequence of WDSL packets will load one full column of data to the internal holding register of the target XDR DRAM.
Depending upon the ratio of native device width to programmed width, there may be more than one sub-column per column.
After loading a full column, a series of WR commands will be issued to sequentially transfer each sub-column of the column to
the XDR DRAM core(s), based upon the SC [3:0] bits.
Version 1.0 Jan. 2005
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XDR DRAM
Table 11 : WDSL-to-Core Mapping (First Generation x16/x8/x4 XDR DRAM, BL = 16)
WDSL Core Word Load
Order
DQ Pins Used
x16
x8
x4
Core Word
SC[3:2] SC[3:2] SC[3:2] SC[3:2] SC[3:2] SC[3:2] SC[3:2]
x4
x8
x16
WD[n][15:0]
=xx
= 0x
= 1x
= 00
= 01
= 10
= 11
LOGICAL VIEW OF XDR DRAM
Word Written (1 = Written, 0 = Not Written)
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ0 WD[0][15:0]
DQ1 WD[1][15:0]
DQ2 WD[2][15:0]
DQ3 WD[3][15:0]
DQ4 WD[4][15:0]
DQ5 WD[5][15:0]
DQ6 WD[6][15:0]
DQ7 WD[7][15:0]
DQ8 WD[8][15:0]
DQ9 WD[9][15:0]
WDSL Word 8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
WDSL Word 7
WDSL Word 12
WDSL Word 3
WDSL Word 10
WDSL Word 5
WDSL Word 14
WDSL Word 1
WDSL Word 9
WDSL Word 6
WDSL Word 13
WDSL Word 2
WDSL Word 11
WDSL Word 4
WDSL Word 15
WDSL Word 0
DQ2 DQ10 WD[10][15:0]
DQ3 DQ11 WD[11][15:0]
DQ4 DQ12 WD[12][15:0]
DQ5 DQ13 WD[13][15:0]
DQ6 DQ14 WD[14][15:0]
DQ7 DQ15 WD[15][15:0]
PHYSICAL VIEW OF XDR DRAM
WDSL Word 15
Word Written (1 = Written, 0 = Not Written)
DQ14 WD[14][15:0]
DQ6 WD[6][15:0]
DQ10 WD[10][15:0]
DQ2 WD[2][15:0]
DQ12 WD[12][15:0]
DQ4 WD[4][15:0]
DQ8 WD[8][15:0]
DQ0 WD[0][15:0]
DQ1 WD[1][15:0]
DQ9 WD[9][15:0]
DQ5 WD[5][15:0]
DQ13 WD[13][15:0]
DQ3 WD[3][15:0]
DQ11 WD[11][15:0]
DQ7 WD[7][15:0]
DQ15 WD[15][15:0]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
DQ6
DQ2
DQ4
DQ0
DQ1
DQ5
DQ3
DQ7
WDSL Word 14
WDSL Word 13
WDSL Word 12
WDSL Word 11
WDSL Word 10
WDSL Word 9
WDSL Word 8
WDSL Word 7
WDSL Word 6
WDSL Word 5
WDSL Word 4
WDSL Word 3
WDSL Word 2
WDSL Word 1
WDSL Word 0
DQ2
DQ0
DQ1
DQ3
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XDR DRAM
Table 12 : Core Data Word-to-WDSL Formata
DQ Serialization Order
CFM/PCLK Cycle
Cycle 0
Cycle 1
t10 t11 t12 t13 t14 t15
Symbol (Bit) Time
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
Bit Transmitted on DQ
pins
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D12 D13 D14 D15
WDSL Byte/Bit Transfer Order
Core Word
Core Word WD[n][15:0]
WDSL Byte Order
WDSL Byte 0
WDSL Byte 1
SWD Field of Serial
Packet
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit Transmitted on CMD
pin
D15 D11 D7
D3 D14 D10 D6
D2 D13 D9
D5
D1 D12 D8
D4
D0
a. Applies for first generation x16/x8/x4 XDR DRAM with BL=16
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XDR DRAM
Special Feature Description
Dynamic Width Control
This XDR DRAM device includes a feature called dynamic width control. This permits the device to be configured so that read
and write data can be accessed through differing widths of DQ pins. Figure 49 shows a diagram of the logic in the path of the
read data (Q) and write data (D) that accomplishes this.
The read path is on the right of the figure. There are 16 sets of S signals (the internal data bus connecting to the sense amps of
the memory core), with 16 signals in each set. When the XDR DRAM device is configured for maximum width operation (using
the WIDTH [2:0] field in the CFG register), each set of 16 S signals goes to one of the 16 DQ pins (via the Q[15:0][15:0] read
bus) and are driven out in the 16 time slots for a read data packet.
When the XDR DRAM device is configured for a width that is less than the maximum, some of the DQ pins are used and the rest
are not used. The SC [3:0] field of the COL request packets which S[15:0] [15:0] signals are passed to the Q[15:0] [15:0] read
bus and driven as read data.
Figure 50 shows the mapping from the S bus to the Q bus as a function of the WIDTH [2:0] register field and the SC[3:0] field of
the COL request packet. There is a separate table for each valid value of WIDTH [2:0]. In each table, there is an entry in the left
column for each valid value of SC[3:0]. This field should be treated as an extension of the C[9:4] column address field. The right
hand column shows which sets of S[15:0] [15:0] signals are mapped to the Q read data bus for a particular value of SC[3:0].
For example, assume that the WIDTH [2:0] value is “010”, indicating a device width of x4. Looking at the appropriate table in
Figure50, it may be seen that in the SC [3:0] field, the SC [1:0] sub-column address bits are not used. The remaining SC [3:0]
address bit(s) selects one of the 64-bit blocks of S bus signals, causing them to be driven onto the Q [3:0] [15:0] read data bus,
which in turn is driven to the DQ3...0/DQN3...0 data pins. The Q[15:4] [15:0] signals and DQ15...4/DQN15....4 data pins are not
used for a device width of x4.
The write path is shown on the left side of Figure 49. As shown, there are 16 sets of S signals(the internal data bus connecting
to the sense amps of the memory core), with 16 signals in each set. When the XDR DRAM device is configured for maximum
width operation (using the WIDTH [2:0] field in the CFG register), each set of 16 S signals is driven from one fo the 16 DQ pins
(via the D[15:0] [15:0] write bus) from each of the 16 time slots for a write data packet.
Figure 50 also shows the mapping from the D bus to the S bus as a function of the WIDTH[2:0] register field and the SC[3:0]
field of the COL request packet. There is a separate table for each valid value of WIDTH[2:0]. In each table, there is an entry in
the left column for each valid value of SC[3:0]. This field should be treated as an extension of the C[9:4] column address field.
The right hand column shows which set of S[15:0] [15:0] signals are mapped from the D read data bus for a particular value of
SC[3:0].
For example, assume that the WIDTH[2:0] value is “001”, indicating a device width of x2. Looking at the appropriate table in
Figure50, it may be seen that in the SC[3:0] field, the SC[0] sub-column address bit is not used. The remaining SC [3:0] address
bit(s) selects one of the 32-bit blocks of S bus signals, causing them to be driven from the D [1:0] [15:0] write data bus, which in
turn is driven from the DQ1... 0/DQN1... 0 data pins. The D[15:2] [15:2] signals and DQ15... 2/DQN15...2 data pins are not used
for a device width of x2.
Figure 49 : Multiplexes for Dynamic Width Control
S[15:0][15:0]
16x16
16x16
8
M[7:0]
Byte Mask (WR)
D1[15:0][15:0]
4+3
16x16
4+3
WIDTH[2:0]
SC[3:0]
WIDTH[2:0]
SC[3:0]
Dynamic Width Demux (WR)
Dynamic Width Mux (RD)
16x16
16x16
D[15:0][15:0]
Q[15:0][15:0]
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
The block diagram in Figure 49 indicates that the Dynamic Width logic is positioned after the serial-to-parallel conversion
(demux block) in the data receiver block and before the parallel-to-serial conversion (mux block) in the data transmitter block
(see also the block diagram in Figure2). The block diagram is shown in this manner so the functionality of the logic can be made
as clear as possible. Some implementations may place this logic in the data receiver and transmitter blocks, performing the
mapping in Figure 50 on the serial data rather than the parallel data. However, this design choice will not affect the functionality
of the Dynamic Width logic; it is strictly an implementation decision.
Figure 50 : D-toS and S-to-D Mapping for Dynamic Width Control
WIDTH[2:0]=011 (x8 device width)
WIDTH[2:0]=000 (x1 device width)
WIDTH[2:0]=001 (x2 device width)
S[7:0][15:0]
S[0][15:0]
S[1:0][15:0]
0xxx
0000
000x
S[15:8][15:0]
S[1][15:0]
S[3:2][15:0]
1xxx
0001
001x
S[2][15:0]
S[5:4][15:0]
D[7:0][15:0]
SC[3:0]
0010
010x
Q[7:0][15:0]
S[3][15:0]
S[4][15:0]
S[5][15:0]
S[6][15:0]
S[7][15:0]
S[8][15:0]
S[9][15:0]
S[10][15:0]
S[11][15:0]
S[12][15:0]
S[13][15:0]
S[14][15:0]
S[15][15:0]
S[7:6][15:0]
S[9:8][15:0]
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
011x
100x
101x
110x
111x
S[11:10][15:0]
S[13:12][15:0]
S[15:14][15:0]
D[1:0][15:0]
Q[1:0][15:0]
SC[3:0]
WIDTH[2:0]=010 (x4 device width)
WIDTH[2:0]=100 (x16 device width)
S[3:0][15:0]
S[7:4][15:0]
S[15:0][15:0]
00xx
01xx
10xx
11xx
xxxx
D[15:0][15:0]
Q[15:0][15:0]
SC[3:0]
S[11:8][15:0]
S[15:12][15:0]
D[3:0][15:0]
Q[3:0][15:0]
D[0][15:0]
Q[0][15:0]
SC[3:0]
SC[3:0]
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Write Masking
Figure 51 shows the logic used by the XDR DRAM device when a write-masked command (WRM) is specified in a COLM
packet. This masking logic permits individual byte of a write data packet to be written or not written according to the value of an
eight bit write mask M [7:0].
In Figure 51, there are 16 sets of 16 bit signals forming the D1[15:0] [15:0] input bus for the Byte Mask block. These are treated
as 2 x 16 8-bit bytes:
D1 [15] [15.8]
D1 [15] [7:0]
...
D1 [1] [15:8]
D1 [1] [7:0]
D1 [0] [15:8]
D1 [0] [7:0]
The eight bits of each byte is compared to the value in the byte mask field (M[7:0]). If they are not equal (NE), then the corre-
sponding write enable signal (WE) is asserted and the byte is written into the sense amplifier. If they are equal, then corre-
sponding write enable signal (WE) is deasserted and the byte is not written into the sense amplifier.
In the example of Figure 51, a WRM command performs a masked write of a 64 byte data packet to all the memory devices
connected to the RQ bus (and receiving the command). It is the job of the memory controller to search the 64 bytes to find an
eight bit data value that is not used and place it into the M [7:0] field. This will always be possible because there are 256 possible
8-bit values and there are only 64 possible values used in the bytes in the data packet.
Figure 51 : Byte Mask Logic
S[15][15:8]
S[15][7:0]
S[0][15:8]
8
S[0][7:0]
8
WE-MSB
[15]
WE-LSB
WE-MSB
[0]
1
WE-LSB
[15]
1
[0]
1
8
8
1
8
8
NE
NE
NE
NE
Compare
Compare
Compare
Compare
8
8
8
8
8
8
8
8
8
8
D1[15][15:8]
D1[15][7:0]
D1[0][15:8]
D1[0][7:0]
M[7:0]
8
8
8
8
D1[15][15:8]
D1[15][7:0]
D1[0][15:8]
D1[0][7:0]
S[15:0][15:0]
16x16
16x16
8
M[7:0]
Byte Mask (WR)
D1[15:0][15:0]
16x16
4+3
WIDTH[2:0]
SC[3:0]
4+3
WIDTH[2:0]
SC[3:0]
Dynamic Width Demux (WR)
16x16
Dynamic Width Mux (RD)
16x16
D[15:0][15:0]
Q[15:0][15:0]
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Note that other systems might use a data transfer size that is different than the 64 bytes per tCC interval per RQ bus that is used
in the example in Figure 51.
Figure 52 shows the timing of two successive WRM commands in COLM packets. The timing is identical to that of two succes-
sive WR commands in COL packets. The one difference is that the COLM packet includes a M[7:0] field that indicates the
reserved bit pattern (for the eight bits of each byte) that indicates that the byte is not to be written. This requires that the align-
ment of bytes within the data packet be defined, and also that the bit numbering within each byte be defined (note that this was
not necessary for the unmasked WR command). In the figure, bytes are contained within a single DQ/DQN pin pair - this is
necessary so the dynamic width feature can be supported. Thus, each pin pair carries two bytes of each data packet. Byte[0] is
transferred earlier than byte[1], and bit[0] of each byte (corresponding to M [0]) is transferred first, followed by the remaining bits
in succession).
Figure 52 : Write-Masked (WRM) Transaction Example
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T
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T
T
T
T
T
T
T
T
T
T
T
T
T
22 23
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CFM
CFMN
tCYCLE
WRM
a1
WRM
a2
RD
a1
RQ11..0
tCC
tCWD
DQ15..0
DQN15..0
D(a1)
D(a2)
Q(a1)
tCAC
Bit- and Byte-number-
ing convention for write
and read data packets.
Byte [16+0]
Byte [0]
DQ0
DQN0
[0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
Byte [1]
Byte [16+1]
DQ1
DQN1
[0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
Byte [15]
Byte [16+15]
DQ15
DQN15
[0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Multiple Bank sets and the ERAW Feature
Figure 55 shows a block diagram of a XDR DRAM in which the banks are divided into two sets (called the even bank set and the
odd bank set) according to the least-significant bit of the bank address field. This XDR DRAM supports a feature called “Early
Read After Write” (hereafter called “ERAW”)
The logic that accepts commands on the RQ11...0 signals is capable of operating these two bank sets independently. In addi-
tion, each bank set connects to its own internal “S” data bus (called S0 and S1). The receive interface is able to drive write data
onto either of these internal data buses, and the transmit interface is able to sample read data from either of these internal data
buses. These capabilities will permit the delay between a write column operation and a read column operation to be reduced,
thereby improving performance.
Figure 53 shows the timing previously presented in Figure12, but with the activity on the internal S data bus included. The write-
to-read parameter t∆WR ensures that there is adequate turnaround time on the S bus between D (a2) and Q (c1).
When ERAW is supported with odd and even bank sets, the t∆WR MIN parameter must be obeyed when the write and read
,
column operations are to the same bank set, but a second parameter t∆WR-D permits earlier column operations to the opposite
bank set. Figure54 shows how this is possible because there are two internal data buses S0 and S1. In this example, the four
columns read operations are made to the same bank Bb, but they could use different banks as long as they all belonged to the
bank set that was different form the bank set containing Ba (for the column write operations).
Figure 53 : Write/Read Interaction - No ERAW Feature
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T
T
T
T
T
T
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T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
WR
a1
WR
a2
RD
c1
RD
c2
RQ11..0
t∆WR
tCAC
DQ15..0
DQN15..0
D(a1)
D(a2)
Q(c1)
Q(c2)
Q(c2)
tWR-BUB,XDRDRAM
tCC
tCWD
turnaround
tCC
S[15:0]
[15:0]
D(a1)
D(a2)
Q(c1)
a1 = {Ba,Ca1}
c1 = {Bc,Cc1}
a2 = {Ba,Ca2}
c2 = {Bc,Cc2}
Transaction a: WR
Transaction c: RD
Figure 54 : Write/Read Interaction - ERAW Feature
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T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
RD
b1
RD
b2
RD
b3
WR
a1
t∆WR-D
WR
a2
RD
b4
RD
c1
RQ11..0
tCAC
DQ15..0
DQN15..0
D(a1)
D(a2)
Q(b4)
Q(c1)
Q(c1)
Q(b1)
Q(b2)
Q(b3)
turnaround
tCC
tCWD
tCC
tWR-BUB,XDRDRAM
S0[15:0]
[15:0]
D(a1)
D(a2)
S1[15:0]
[15:0]
Q(b1)
Q(b2)
Q(b3)
Q(b4)
Bank Restrictions
Bb is in different bank set than Ba
Bc is in same bank set as Ba
Transaction a: WR
Transaction b: RD
Transaction c: RD
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
c1 = {Bc,Cc1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
b3 = {Bb,Cb3}
b4 = {Bb,Cb4}
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Figure 55 : XDR DRAM Block Diagram with Bank Sets
RQ11..0
12
1:2 Demux
Reg
COL
decode
PRE
decode
ACT
decode
6
3
11
3
3
Even
Odd
Bank Array
Bank Array
11
6
11
6
16x16*2 *2
16x16*2 *2
1
1
1
1
ACT
ACT
ACT logic
ACT
ACT
ROW
ROW
PRE
11
11
11
11
ROW
ROW
1
1
1
1
PRE
Bank 1
Bank 0
(23-2)
PRE logic
PRE
PRE
(23-1)
Bank
Bank
6
6
6
6
16x16*2
. . . 16x16*2
16x16*2
16x16*2
. . .
Sense Amp Array
Sense Amp Array
6
6
1
1
1
1
16x16*2
16x16*2
R/W
R/W
R/W
R/W
COL logic
Sense Amp 0
COL
COL
Sense Amp 1
6
6
6
6
COL
COL
Sense Amp
(2 -1)
(23-2)
3
Sense Amp
16x16
S1[15:0][15:0]
. . 1. 6x16
16x16
S0[15:0][15:0]
16x16
. . .
WR even
RD even
RD odd
16x16
WR odd
16x16
Byte Mask (WR)
Dynamic Width Demux (WR)
Dynamic Width Mux (RD)
16x16
16x16
D[15:0][15:0]
Q[15:0][15:0]
16
. . . .
. . .
16
16/t
1:16 Demux
16
16:1 Mux
16
16/t
CC
CC
16
DQ15..0
16
DQN15..0
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Simultaneous Activation
When the XDR DRAM supports multiple bank sets as in Figure 55, another feature may be supported, in addition to ERAW. This
feature is simultaneous activation, and the timing of several cases is shown in Figure 56.
The tRR parameter specifies the minimum spacing between packets with activation commands in XDR DRAMs with a single
bank set, or between packets to the same bank set in a XDR DRAM with multiple bank sets. The tRR-D parameter specifies the
minimum spacing between packets with activation commands to different bank sets in a XDR DRAM with multiple bank sets.
In Figure 56, Case 4 shows an example when both tRR and tRR-D must be at least 4*tCYCLE. In such a case, activation com-
mands to different bank sets satisfy the same constraint as activation commands to the same bank set.
In Figure 56, Case 2 shows an example when tRR must be at least 4*tCYCLE and tRR-D must be at least 2*tCYCLE. In such a case,
an activation command to one bank set may be inserted between two activation commands to a different bank set.
In Figure 56, Case 1 shows an example when tRR must be at least 4*tCYCLE and tRR-D must be at least 1*tCYCLE. As in the pre-
vious case, an activation command to one bank set may be inserted between two activation commands to a different bank set.
In this case, the middle activation command will not be symmetrically placed relative to the two outer activation commands.
In Figure 56, Case 0 shows an example when tRR must be at least 4*tCYCLE and tRR-D must be at least 0*tCYCLE. This means
that two activation commands may be issued on the same CFM clock edge. This is only possible by using the delay mechanism
in one of the two commands. See “Dynamic Request Scheduling” on page 18. In the example shown, the packet with the REFA
command is received one cycle before the command with the ACT command, and the REFA command includes a one cycle
delay. Both activation commands will be issued internally to different bank sets on the same CFM clock edge.
Figure 56 : Simultaneous Activation — tRR-D Cases
Case 4: t
= 4*t
Case 2: t
= 2*t
RR-D
CYCLE
RR-D CYCLE
REFA & ACT have same t
REFA fits between two ACT
RR
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T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
5
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
ACT
ACT
REFA
ACT
REFA
ACT
RQ11..0
tRR-D
tRR-D
tRR-D
tRR
DQ15..0
DQN15..0
note - REFA is directed to bank
set different from two ACT
Case 0: t
= 0*t
CYCLE
RR-D
Case 1: t
= 1*t
CYCLE
REFA simultaneous with ACT
RR-D
(REFA uses delay=1*t
)
REFA fits between two ACT
CYCLE
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T
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T
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
ACT
ACT
REFA
ACT
REFA
ACT
RQ11..0
tRR-D
tRR-D
DQ15..0
DQN15..0
note - REFA is directed to bank
set different from two ACT
note - REFA is directed to bank
set different from ACT at T
tRR
tRR
12
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K4Y5416(/08/04)4UF
XDR DRAM
Simultaneous Precharge
When the XDR DRAM supports multiple bank sets as in Figure55, another feature may be supported, in addition to ERAW. This
feature is simultaneous precharge, and the timing of several cases is shown in Figure57.
The tPP parameter specifies the minimum spacing between packets with precharge commands in XDR DRAMs with a single
bank set, or between packets to the same bank set in a XDR DRAM with multiple bank sets. The tPP-D parameter specifies the
minimum spacing between packets with precharge commands to different bank sets in a XDR DRAM with multiple bank sets.
In Figure57, Case4 shows an example when both tPP and tPP-D must be at least 4*tCYCLE. In such a case, precharge commands
to different bank sets satisfy the same constraint as precharge commands to the same bank set.
In Figure57, Case2 shows an example when tPP must be at least 4*tCYCLE and tPP-D must be at least 2*tCYCLE. In such a case,
a precharge command to one bank set may be inserted between two precharge commands to a different bank set.
In Figure57, Case1 shows an example when tPP must be at least 4*tCYCLE and tPP-D must be at least 1*tCYCLE. As in the
previous case, a precharge command to one bank set may be inserted between two precharge commands to a different bank
set. In this case, the middle precharge command will not be symmetrically placed relative to the two outer precharge commands.
In Figure57, Case0 shows an example when tPP must be at least 4*tCYCLE and tPP-D must be at least 0*tCYCLE. This means that
two precharge commands may be issued on the same CFM clock edge. This is only possible by using the delay mechanism in
one of the two commnads. See “Dynamic Request Scheduling” on page 18. It is also possibly by taking advantage of the fact
that two independent precharge commands may be encoded within a single ROWP packet. In the example shown, the ROWP
packet contains both a REFP command and a PRE command. Both precharge commands will be issued internally to different
bank sets on the same CFM clock edge.
Figure 57 : Simultaneous Precharge — tPP-D Cases
Case 4: t
= 4*t
Case 2: t
= 2*t
PP-D
CYCLE
PP-D CYCLE
REFP & PRE have same t
REFP fits between two PRE
RR
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T
T
T
T
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
5
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
PRE
PRE
REFP
PRE
REFP
PRE
RQ11..0
tPP-D
tPP-D
tPP-D
DQ15..0
DQN15..0
note - REFP is directed to bank
set different from two PRE
tPP
Case 0: t
= 0*t
CYCLE
PP-D
Case 1: t
= 1*t
CYCLE
REFP simultaneous with PRE
PP-D
REFP fits between two PRE
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T
T
T
T
T
T
T
T
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
CFM
CFMN
tCYCLE
PRE
PRE
REFP
REFP
PRE
PRE
RQ11..0
tPP-D
tPP-D
DQ15..0
DQN15..0
note - REFP is directed to bank
set different from two PRE
note - REFP is directed to bank
set different from PRE at T
tPP
tPP
12
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Operating Conditions
Electrical Conditions
Table13 summarizes all electrical conditions (temperature and voltage conditions) that may be applied to the memory compo-
nent. The first section of parameters is concerned with absolute voltage, storage and operating temperatures, and the power
supply, reference, and termination voltage.
The second section of parameters determines the input voltage levels for the RSL RQ signals. The high and low voltages must
satisfy a symmetry parameter with respect to the VREF, RSL
The third section of parameters determines the input voltage levels for the RSL SI(serial interface) signals. The high and low
voltages must satisfy a symmetry parameter with respect to the VREF, RSL
.
.
The fourth section of parameters determines the input voltage levels for the CFM clock signals. The high and low voltages are
specified by a common-mode value and a swing value.
The fifth section of parameters determines the input voltage levels for the write data signals on the DRSL DQ pins. The high and
low voltages are specified by a common-mode value and a swing value.
Table 13 : Electrical Conditions
Symbol
VIN,ABS
Parameter
Minimum
- 0.3
Maximum
1.5
Unit
V
Voltage applied to any pin (except VDD) with respect to GND
Voltage on VDD with respect to GND
VDD,ABS
TSTORE
TJ
- 0.5
2.3
V
Storage temperature
- 50
100
°C
°C
V
Junction temperature under bias during normal operation
Supply voltage applied to VDD pins during normal operation
100
VDD
1.8 - 0.09
1.8 + 0.09
VTERM,RSL
- 0.450 - 0.025
VTERM,RSL
- 0.450 + 0.025
RSL - Reference voltage applied to VREF pina
VREF,RSL
V
VTERM,DRSL DRSL - Termination voltage applied to VTERM pins
1.2 - 0.06
1.2 + 0.06
V
V
V
VIL,RQ
VREF,RSL - 0.45
VREF,RSL - 0.15
RSL RQ inputs -low voltage
RSL RQ inputs -high voltage
RSL RQ inputs - data asymmetry:
b
VREF,RSL + 0.15
TBD
VREF,RSL + 0.45
TBD
VIH,RQ
RA,RQ
VIL,SI
V
RA,RQ = (VIH,RQ-VREF,RSL)/(VREF,RSL-VIL,RQ)
VREF,RSL - 0.45
VREF,RSL + 0.20
VREF,RSL - 0.20
VREF,RSL + 0.45
RSL Serial Interface inputs -low voltage
RSL Serial Interface inputs -high voltage
V
V
b
VIH,SI
RSL Serial Interface inputs - data asymmetry:
A,SI = (VIH,RQ-VREF,RSL)/(VREF,RSL-VIL,RQ
RA,SI
TBD
TBD
V
V
R
)
CFM/CFMN input - common mode: VICM,CTM
(VIH,CFMb+VIL,CTM)/2
=
VICM,CFM
VTERM,DRSL-0.150 VTERM,DRSL-0.075
b
CFM/CFMN input - high-low swing: VISW,CFM = (VIH,CTM
VIL,CTM
-
VISW,CFM
0.15
0.30
V
)
DRSL DQ inputs - common mode: VICM,DQ
(VIH,DQb+VIL,DQ)/2
=
VICM,DQ
VISW,DQ
VTERM,DRSL-0.150 VTERM,DRSL-0.025
0.05 0.30
)
V
V
DRSL DQ inputs - high-low swing: VISW,DQ = (VIH,DQb - VIL,DQ
a. VTERM,RSL is typically 1.2V±0.06V. It connects to the RSL termination components, not to this DRAM component.
b. VIH is typically equal to VTERM,RSL or VTERM,DRSL (whichever is appropriate) under DC conditions in a system.
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Timing Conditions
Table14 summarizes all timing conditions that may be applied to the memory component. The first section of parameters is
concerned with parameters for the clock signals. The second section of parameters is concerned with parameters for the
request signals. The third section of parameters is concerned with parameters is concerned with parameters for the write data
signals. The fourth section of parameters is concerned with parameters for the serial interface signals. The fifth section is
concerned with all other parameters, including those for refresh, calibration, power state transitions, and initialization.
Table 14 : Timing Conditions
Symbol
Parameter and Other Conditions
CFM RSL clock - cycle time
Minimum
Maximum
Units
Figure(s)
-4000
-3200
-2400
2.00
2.50
3.33
3.83
3.83
3.83
ns
ns
ns
tCYCLE or tCYC,CTM
Figure 58
tR,CFM, tF,CFM
tH,CFM, tL,CFM
tR,RQ, tF,RQ
tCYCLE
tCYCLE
tCYCLE
CFM/CFMN input - rise and fall time - use minimum for test.
CFM/CFMN input - high and low times
0.08
40%
0.08
0.20
60%
0.26
Figure 58
Figure 58
Figure 59
RSL RQ input - rise/fall times (20% - 80%) - use minimum for test.
RSL RQ input to sample points (set/hold)
-
-
-
@ 2.50 ns > tCYCLE ≥ 2.00 ns
tbd
0.200
tbd
ns
ns
ns
tS,RQ, tH,RQ
tIR,DQ, tIF,DQ
tS,DQ, tH,DQ
Figure 59
Figure 60
@ 3.33 ns > tCYCLE ≥ 2.50 ns
@ 3.83 ns ≥ tCYCLE ≥ 3.33 ns
tCYCLE
DRSL DQ input - rise/fall times (20% - 80%) - use minimum for test.
0.020
0.074
DRSL DQ input to sample points (set/hold)
@ 2.50 ns > tCYCLE ≥ 2.00 ns
@ 3.33 ns > tCYCLE ≥ 2.50 ns
@ 3.83 ns ≥ tCYCLE ≥ 3.33 ns
-
-
-
ns
ns
ns
tbd
0.065
tbd
Figure 60
tDOFF,DQ
tCYCLE
DRSL DQ input delay offset (fixed) to sample points
Serial Interface SCK input - cycle time
-0.08
+0.08
-
Figure 60
Figure 62
Figure 62
Figure 62
Figure 62
Figure 62
tCYC,SCK
20
ns
ns
tR,SCK, tF,SCK
tH,SCK, tL,SCK
tIR,SI, tIF,SI
tS,SI,tH,SI
Serial Interface SCK input - rise and fall times
-
40%
-
5.0
60%
5.0
-
tCYC,SCK
Serial Interface SCK input - high and low times
Serial Interface CMD,RST,SDI input - rise and fall times
Serial Interface CMD,SDI input to SCK clock edge - set/hold time
ns
ns
5
Delay from last SCK clock edge for register write to first CFM edge with RQ
packet containing a command which uses the value in the register. Also,
delay from first CFM edge with RQ packet containing a command which
modifies register value to the first SCK clock edge for register read to this
register.
tDLY,SI-RQ
tCYC,SCK
10
-
-
-
Refresh interval. Every row of every bank must be accessed at least once in
this interval with a ROW-ACT, ROWP-REF or ROWP-REFI command.
tREF
16
ms
ns
Figure 44
-
Average refresh command interval. ROWP-REFA or ROWP-REFI com-
mands must be issued at this average rate. This depends upon tREF and the
tREFA-REFA,AVG
tREFA-REFA,AVG = 488
number of banks and the number of rows: tREFI = tREF/(NB*NR) =
t
REF/(23*211).
Refresh burst limit. The number of ROWP-REFA or ROWP-REFI com-
NREFA,BURST
mands which can be issued consecutively at the minimum command spac-
ing.
-
-
128
commands
tCYCLE
-
-
Refresh burst interval. The interval between a burst of NREFA,BURST,MAX
ROWP-REFA or ROWP-REFI commands and the next ROWP-REFA or
ROWP-REFI command.
tBURST-REFA
TBD
tCOREINIT
tCALC
Interval needed for core initialialization after power is applied.
Current calibration interval
-
-
1.5
ms
ms
-
100
Figure 45
Delay between packet with any command and CALC/CALZ packet
w/ PRE or REFP command
w/ any other command
tCMD-CALC, tCMD-CALZ
tCYCLE
4
16
-
-
Figure 45
tCALCE, tCALZE
tCALE-CMD
tCMD-PDN
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
Delay between CALC/CALZ packet and CALE packet
Delay between CALE packet and packet with any command
Last command before PDN entry
12
24
-
-
-
-
-
-
Figure 45
Figure 45
Figure 46
Figure 46
Figure 46
Figure 46
16
tPDN-CFM
RSL CFM/CFMN and VTERM stable after PDN entry
RSL CFM/CFMN and VTERM stable before PDN exit
16
tCFM-PDN
16
tPDN-CMD
First command after PDN exit (includes lock time for CFM/CFMN)
4096
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K4Y5416(/08/04)4UF
XDR DRAM
Operating Characteristics
Electrical Characteristics
Table15 summarizes all electrical parameters (temperature, current and voltage) that characterize this memory component. The
only exception is the supply current values(IDD) under different operating conditions covered in the Supply Current Profile
section.
The first section of parameters is concerned with the thermal characteristics of the memory component.
Ther second section of parameters is concerned with the current needed by the RQ pins and VREF pin.
The third section of parameters is concerned with the current needed by the DQ pins and voltage levels produced by the DQ
pins when driving read data. This section is also concerned with the current needed by the VTERM pin, and with the resistance
levels produced for the internal termination components that attach to the DQ pins.
The fourth section of parameters determines the output voltage levels and the current needed for the serial interface signals.
Table 15 : Electrical Characteristics
Symbol
ΘJC
Parameter
Minimum
Maximum
TBD
Units
°C/Watt
uA
Junction-to-case thermal resistance
-
II,RSL
RSL RQ or Serial Interface input current @ ( VIN= VIH,RQ,MAX
)
-10
-10
10
IREF,RSL
VOSW,DQ
VREF,RSL current @ VREF,RSL,MAX flowing into VREF pin
10
uA
DRSL DQ outputs - high-low swing: VOSW,DQ=(VIH,DQ
-
VIL,DQN) or (VIH,DQN VIL,DQ) (See Figure 27)
-
0.225
TBD
TBD
TBD
0.350
TBD
TBD
TBD
ODF = 00
ODF=01
ODF=10
ODF=11
V
RTERM,DQ
VOL,SI
DRSL DQ outputs - termination resistance
RSL serial interface SDO output - low voltage
RSL serial interface SDO output - high voltage
40.0
0.0
60.0
0.25
Ω
V
V
VOH,SI
VTERM,RSL - 0.25
VTERM,RSL
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K4Y5416(/08/04)4UF
XDR DRAM
Supply Current Profile
In this section, Table16 summarizes the supply current (IDD) that characterizes this memory component. This parameter is
shown under different operating conditions.
Table 16 : Supply Current Profile
Maximum Maximum Maximum
@tCYCLE
2.00 ns
=
@tCYCLE
2.50 ns
=
@tCYCLE
3.33 ns
=
Symbol
Power State and Steady State Transaction Rates
Units
Device in PDN, self-refresh enabled. a
IDD,PDN
IDD,STBY
IDD,REF
IDD,WR
TBD
TBD
TBD
9500
340
-
TBD
TBD
TBD
uA
mA
mA
Device in STBY. This is for a device in STBY with no packets
on the Channela
Device in STBY and refreshing rows at the tREF,MAX period.a
ACT command every tRR, PRE command every tPP, WR
TBD
TBD
1120
1200
TBD
TBD
mA
mA
a
command every tCC.
ACT command every tRR, PRE command every tPP, RD com-
IDD,RD
a,b
mand every tCC
No RD nor WR commands issued. c
ITERM,DRSL,NONE
ITERM,DRSL,RD
ITERM,DRSL,WR
TBD
TBD
TBD
35
TBD
TBD
TBD
mA
mA
mA
c
100
200
RD command every tCC.
c
WR command every tCC.
a. I current @ V
flowing into V pins
DD
DD
DD,MAX
b. This does not include the I
sink current. The device dissipates I
•V
in each DQ/DQN pair when driving data.
OL,DQ
OL,DQ TERM,DQ
c. I
current @ V
flowing into V
pins
TERM,DRSL
TERM,DQ,MAX
TERM
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Timing Characteristics
Table 17 summarizes all timing parameters that characterize this memory component. The only exceptions are the core timing
parameters that are speed-bin dependent. Refer to the Timing Parameters section for more information.
The first section of parameters pertains to the timing of the DQ pins when driving read data.
The second section of parameters is concerned with the timing for the serial interface signals when driving register read data.
The third section of parameters is concerned with the time intervals needed by the interface to transition between power states.
Table 17 : Timing Characteristics
Symbol
Parameter and Other Conditions
Minimum Maximum
Units
Figure(s)
DRSL DQ output delay (variation across 16 Q bits on each
DQ pin) from drive points - output delay
@ 2.50 ns > tCYCLE ≥ 2.00 ns
@ 3.33 ns > tCYCLE ≥ 2.50 ns
@ 3.83 ns ≥ tCYCLE ≥ 3.33 ns
tQ,DQ
tbd
-0.065
tbd
tbd
+0.065
tbd
ns
ns
ns
Figure 61
DRSL DQ output delay offset (a fixed value for all 16 Q bits on
each DQ pin) from drive points - output delay
tQOFF,DQ
tCYCLE
tCYCLE
0.00
+0.20
Figure 61
tOR,DQ, tOF,DQ
DRSL DQ output - rise and fall times (20%-80%).
0.02
0.04
15
15
10
16
-
Figure 61
Figure 63
Figure 63
Figure 63
Figure 46
Figure 46
tQ,SI
Serial SCK-to-SDO output delay @ CLOAD,MAX = 15 pF
Serial SDI-to-SDO propagation delay @ CLOAD,MAX = 15 pF
Serial SDO output rise/fall (20%-80%) @ CLOAD,MAX = 15 pF
2
-
ns
ns
tP,SI
tOR,SI, tOF,SI
tPDN-ENTRY
tPDN-EXIT
-
ns
tCYCLE
tCYCLE
Time for power state to change after PDN entry
Time for power state to change after PDN exit
-
0
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K4Y5416(/08/04)4UF
XDR DRAM
Timing Parameters
Table18 summarizes the timing parameters that characterize the core logic of this memory component.. These timing parame-
ters will vary as a function of the component’s speed bin. The four sections deal with the timing intervals between packets with,
respectively, row-row commands, row-column commands, column-column commands, and column-row commands.
Table 18 : Timing Parameters
Min
(A)
Min
(B)
Min
(C)
Symbol
Parameter and Other Conditions
Units
Figure(s)
tRC
16
16
19
23
20
20
24
28
24
24
24
28
a
Row-cycle time: interval between successive
ROWA-ACT or ROWP-REFA or ROWP-REFI acti-
vate commands to the same bank.
tRC-R, 2tCC = tRCD-R + tCC+ tRDP + tRP
Figure 4 -
Figure 7
tRC
tCYCLE
a
tRC-W, 2tCC, noERAW = tRCD-W + tCC+ tWRP +tRP
a
tRC-W, 2tCC, ERAW = tRCD-W + tCC+ tWRP + tRP
Row-asserted time: interval between a ROWA-ACT or ROWP-REFA or ROWP-REFI activate com-
mand and a ROWP-PRE or ROWP-REFP precharge command to the same bank.
Note that tRAS,MAX is 64 us for all timing bins.
Figure 4 -
Figure 7
tRAS
tCYCLE
tCYCLE
tCYCLE
10
6
13
7
17
7
Figure 4 -
Figure 7
Row-precharge time: interval between a ROWP-PRE or ROWP-REFP precharge command and a
ROWA-ACT or ROWP-REFA or ROWP-REFI activate command to the same bank.
tRP
Precharge-to-precharge time: interval between
successive ROWP-PRE or ROWP-REFP pre-
charge commands to different banks.
tPP
4
1
4
1
4
1
Figure 4 -
Figure 7
tPP
b
tPP-D
Row-to-row time: interval between ROWA-ACT or
ROWP- REFA or ROWP-REFI activate commands
to different banks.
tRR
4
4
4
4
4
4
Figure 4 -
Figure 7
tRR
tCYCLE
c
tRR-D
Figure 4 -
Figure 7
Row-to-column-read delay: interval between a ROWA-ACT activate command and a COL-RD read
command to the same bank.
tRCD-R
tRCD-W
tCYCLE
tCYCLE
5
1
7
3
7
3
Figure 4 -
Figure 7
Row-to-column-write delay: interval between a ROWA-ACT activate command and a COL-WR or
COL-WRM write command to the same bank.
tCAC
tCYCLE
tCYCLE
Column access delay: interval from COL-RD read command to Q read data
6
3
7
3
7
3
Figure 10
Figure 9
tCWD
Column write delay: interval from a COL-WR or COLM-WRM write command to D write data.
Figure 4 -
Figure 7
Column-to-column time: interval between successive COL-RD commands, or between successive
COL-WR or COLM-WRM commands.
tCC
tCYCLE
tCYCLE
tCYCLE
tCYCLE
2
3
3
8
2
3
3
9
2
3
3
9
Read-to-write bubble time: interval between the end of a Q read data packet and the start of D write
data packet (the end of a data packet is the time interval tCC after its start).
tRW-BUB,
XDRDRAM
Figure 13
Figure 13
Figure 12
Write-to-read bubble time: interval between the end of a D writed data and the start of Q read data
packet (the end of a data packet is the time interval tCC after its start).
tWR-BUB,
XDRDRAM
Read-to-write time: interval between a COL-RD read command and a COL-WR or COLM-WRM
write command.d
t∆RW
Write-to-read time: interval between a COL-WR or
COLM-WRM write command and a COL-RD read
command.
t∆WR
9
2
10
2
10
2
t∆WR
tCYCLE
Figure 12
e
t∆WR-D
Figure 4 -
Figure 7
Read-to-precharge time: interval between a COL-RD read command and a ROWP-PRE precharge
command to the same bank.
tRDP
tWRP
tDR
tCYCLE
tCYCLE
tCYCLE
tCYCLE
3
10
6
4
12
7
4
12
7
Figure 4 -
Figure 7
Write-to-precharge time: interval between a COL-WR or COLM-WRM write command and a
ROWP-PRE precharge command to the same bank.
Write data-to-read time: interval between the start of D write data and a COL-RD read command to
the same bank.
Figure 12
Figure 9
Write data-to-precharge time: interval between D write data and ROWP-PRE precharge command
to the same bank.
tDP
7
9
9
Interval between ROWP-LRRn command and a subsequent ROWP-LRRn command. f
Interval between ROWP-REFx command and a subsequent ROWP-LRRn command.
Interval between ROWP-LRRn command and a subsequent ROWP-REFx command.
tLRRn-LRRn
tREFx-LRRn
tLRRn-REFx
tCYCLE
tCYCLE
tCYCLE
16
16
16
20
20
20
24
24
24
Table5
Table5
Table5
a. The tRC,MIN parameter is applicable to all transaction types (read, write, refresh, etc.). Read and write transactions may have an additional limitation,
depending upon how many column accesses (each requiring tCC) are performed in each row access (tRC). The table lists the special cases (tRC-R, 2tCC, tRC-
W, 2tCC, noERAW, tRC-W, 2tCC, ERAW) in which two column accesses are performed in each row access. Note that tRC-W, 2tCC, ERAW uses a relaxed value of
tRCD-W that is equal to tRCD-R,MIN. All other parameters are minimum.
b. tPP-D is the tPP parameter for precharges to different bank sets. See “Simultaneous Precharge” on page 53.
c. tRR-D is the tRR parameter for activates to different bank sets. See “Simultaneous Activation” on page 52.
d. See “Propagation Delay” on page 27.
e. t∆WR-D is the t∆WR parameter for write-read accesses to different bank sets. See “Multiple Bank Sets and the ERAW Feature” on page 50. Also, note that
the value of t∆WR-D may not take on the values {3,5,7} within the range{t∆WR-D,MIN, ... t∆WR,MIN-1}. tDWR-D may assume any value ≥ t∆WR,MIN
.
f. ROWP-LRRn includes the commands {ROWP-LRR0,ROWP-LRR1,LOWP-LRR2}, ROWP-REFx includes the commands {ROWP-REFA,ROWP-REFI,
LOWP-REFP},
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Receive/Transmit Timing
Clocking
Figure58 shows a timing diagram for the CFM/CFMN clock pins of the memory component. This diagram represents a magni-
fied view of these pins. This diagram shows only one clock cycle.
CFM and CFMN are differential signals: one signal is the complement of the other. They are also high-true signals - a low
voltage represents a logical zero and a high voltage represents a logical one. There are two crossing points in each clock cycle.
The primary crossing point includes the high-voltage-to-low-voltage transition of CFM (indicated with the arrowhead in the
diagram). The secondary crossing point includes the low-voltage-to-high-voltage transition of CFM. All timing events on the RSL
signals are referenced to the first set of edges.
Timing events are measured to and from the crossing point of the CFM and CFMN signals. In the timing diagram, this is how the
clock-cycle time (tCYCLE or tCYC, CFM), clock-low time (tL, CFM) and clock-high time (tH, CFM) are measured.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (tR, CFM
)
and fall time (tF, CFM) of the signals are measured from the 20% and 80% points of the full-swing levels.
20% = VIL, CFM + 0.2*(VIH, CFM - VIL, CFM)
80% = VIL, CFM + 0.8*(VIH, CFM - VIL, CFM)
Figure 58 : Clocking Waveforms
tCYCLE or tCYC,CFM
logic 1
tL,CFM
tH,CFM
VIH,CFM
80%
CFM
CFMN
20%
VIL,CFM
logic 0
tR,CFM
tF,CFM
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K4Y5416(/08/04)4UF
XDR DRAM
RSL RQ Receive Timing
Figure59 shows a timing diagram for the RQ11...0 request pins of the memory component. This diagram represents a magnified
view of the pins and only a few clock cycle (CFM and CFMN are the clock signals). Timing events are measured to and from the
primary CFM/CFMN crossing point in which CFM makes its high-voltage-to-low-voltage transition. The RQ11...0 signals are low-
true: a high voltage represents a logical zero and a low voltage represents a logical one. Timing events on the RQ11... 0 pins are
measured to and from the point that the signal reaches the level of the reference voltage VREF, RSL.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (tR, RQ
)
and fall time (tF, RQ) of the signals are measured from the 20% and 80% points of the full-swing levels.
20% = VIL, RQ + 0.2*(VIH, RQ - VIL, RQ
80% = VIL, RQ + 0.8*(VIH, RQ - VIL, RQ
)
)
There are two data receiving windows defined for each RQ11...0 signal. The first of these (labeled “0”) and a set time, tS,RQ, and
a hold time, tH,RQ, measured around the primary CFM/CFMN crossing point. The second (labeled “1”) has a set time (tS, RQ
and a hold time (tH, RQ) measured around a point 0.5*tCYCLE after the primary CFM/CFMN crossing point.
)
Figure 59 : RSL RQ Receive Waveform
tCYCLE
CFM
CFMN
[1/2]•tCYCLE
tH,RQ
logic 0
tS,RQ
tS,RQ
tH,RQ
VIH,RQ
80%
RQ0
VREF,RSL
20%
0
1
VIL,RQ
logic1
tR,RQ
tF,RQ
[1/2]•tCYCLE
tH,RQ
logic 0
VIH,RQ
80%
tS,RQ
tS,RQ
tH,RQ
RQ11
VREF,RSL
0
1
20%
VIL,RQ
logic 1
tR,RQ
tF,RQ
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K4Y5416(/08/04)4UF
XDR DRAM
DRSL DQ Receive Timing
Figure60 shows a timing diagram for receiving write data on the DQ/DQN data pins of the memory component. This diagram
represents a magnified view of the pins and only a few clock cycles are shown (CFM and CFMN are the clock signals). Timing
events are measured to and from the primary CFM/CFMN crossing point in which CFM makes its high-voltage-to-low -voltage
transition. The DQ15...0/DQN15...0 signals are high-true: a low voltage represents a logical zero and a high voltage represents
a logical one. They are also differential - timing events on the DQ15...0/DQN15... 0 pins are measured to and from the point that
each differential pair crosses.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (tIR
,
DQ) and fall time (tIF, DQ) of the signals are measured from the 20% and 80% points of the full-swing levels.
20% = VIL, DQ + 0.2*(VIH
,
,
DQ - VIL, DQ
DQ - VIL, DQ
)
)
80% = VIL, DQ + 0.8*(VIH
There are 16 data receiving windows defined for each DQ15...0/DQN15... 0 pin pair. The receiving windows for a particular
DQi/DQNi pin pair is referenced to an offset parameter tDOFF DQi (the index “i” may take on the values {0, 1, .. , 15} and refers to
each of the DQ15... 0/DQN15... 0 pin pairs).
,
The tDOFF DQi parameter determines the time between the primary CFM/CFMN crossing point and the offset point for the
DQi/DQNi pin pair. The 16 receiving windows are placed at times tDOFF DQi + (j/8)*tCYCLE (the index “j” may take on the values
{0, 1, .. , 15} and refers to each of the receiving windows for the DQi/DQNi pin pair).
The offset values tDOFF DQi for each of the 16 DQi/DQNi pin pairs can be different. However, each is constrained to lie inside the
range {tDOFF MIN, tDOFF MAX}. Furthermore, each offset value tDOFF DQi is static and will not change during system operation. Its
value can be determined at initialization.
The 16 receiving windows (j = 0 ... 15) for the first pair DQ0/DQN0 are labeled “0” through “15”. Each window has a set time (tS,
DQ) and a hold time (tH, DQ) measured around a point tDOFF DQ0 + (j/8) *tCYCLE after the primary CFM/CFMN crossing point.
The 16 receiving windows (j = 0 ... 15) for the each of the other pairs DQi/DQNi are also labeled “0” through “15”. Each window
,
,
,
,
,
,
,
has a set time (tS, DQ) and a hold time (tH, DQ) measured around a point tDOFF DQi
,
+ (j/8)*tCYCLE after the primary CFM/CFMN
crossing point.
Version 1.0 Jan. 2005
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Figure 60 : DRSL DQ Receive Waveforms
tCYCLE
CFM
...
CFMN
i = {0,1,2,3,4,5,...15}
j = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
tDOFF,MAX
tDOFF,MIN
[(j)/8]•tCYCLE
tDOFF,DQ0
logic 1
VIH,DQ
tS,DQ
tH,DQ
DQ0
80%
...
...
0
1
2
3
4
5
6
j
14
15
20%
DQN0
VIL,DQ
logic 0
tIF,DQ
tIR,DQ
[(j)/8]•tCYCLE
tDOFF,DQi
logic 1
VIH,DQ
80%
tS,DQ
tH,DQ
DQi
...
...
0
1
2
3
4
5
6
j
14
15
20%
DQNi
VIL,DQ
logic 0
tIR,DQ
tIF,DQ
[(j)/8]•tCYCLE
tDOFF,DQ15
logic 1
VIH,DQ
80%
tS,DQ
tH,DQ
DQ15
...
...
0
1
2
3
4
5
6
j
14
15
20%
DQN15
VIL,DQ
logic 0
tIR,DQ
tIF,DQ
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K4Y5416(/08/04)4UF
XDR DRAM
DRSL DQ Transmit Timing
Figure61 shows a timing diagram for transmitting read data on the DQ15...0/DQN15...0 data pins of the memory component.
This diagram represents a magnified view of these pins and only a few clock cycles are shown (CFM and CFMN are the clock
signals). Timing events are measured to and from the primary CFM/CFMN crossing point in which CFM makes its high-voltage-
to-low-voltage transition. The DQ15...0/DQN15...0 signals are high-true: a low voltage represents a logical zero and a high
voltage represents a logical one. They are also differential - timing events on the DQ15...0/DQN15...0 pins are measured to and
from the point that each differential pair crosses.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (tOR, DQ
and fall time (tOF, DQ) of the signals are measured from the 20% and 80% points of the full-swing levels.
)
20% = VOL
,
,
DQ + 0.2*(VOH
,
,
DQ - VOL
,
,
)
)
DQ
DQ
80% = VOL
DQ + 0.8*(VOH
DQ - VOL
There are 16 data transmit windows defined for each DQ15...0/DQN15...0 pin pair. The transmitting windows for a particular
DQi/DQNi pin pair is referenced to an offset parameter tQOFF DQi (the index “i” may take on the values {0, 1, .., 15} and refers to
each of the DQ15... 0/DQN15...0 pin pairs).
,
The tQOFF DQi + tQ,DQ,MAX expression determines the time between the primary CFM/CFMN crossing point and the offset point
for the DQi/DQNi pin pair.
The offset values tQOFF DQi for each of the 16 DQi/DQNi pin pairs can be different. However, each is constrained to lie inside the
range {tQOFF MIN, tQOFF MAX}. Furthermore, each offset value tQOFF DQi is static; its value will not change during system opera-
tion. Its value can be determined at initialization time.
The 16 transmit windwos (j = 0 ... 15} for the first pair DQ0/DQN0 are labeled “0” through “15”. Each window begins at the time
(tQOFF DQ0 + tQ,DQ,MAX +((j+0.5)/8)*tCYCLE) and ends at the time (tQOFF DQ0 + tQ,DQ,MIN +((j+1.5)/8)*tCYCLE) measured after the
primary CFM/CFMN crossing point.
,
,
,
,
,
,
,
Note that when no read data is to be transmitted on the DQ/DQN pins(and no other component is transmitting on the external
DQ/DQN wires), then the voltage level on the DQ/DQN pins will follow the voltage reference value VTERM,DRSL on the
VTERM pin. The logical value of each DQ/DQN pin pair in this no-drive state will be “1/1”; when read data is driven, each
DQ/DQN pin pair will have either the logical value of “1/0” or “0/1”.
Version 1.0 Jan. 2005
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Figure 61 : RSL DQ Transmit Waveforms
tCYCLE
CFM
...
CFMN
i = {0,1,2,3,4,5,...15}
j = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
tQOFF,MAX
tQOFF,MIN
[(j+0.5)/8]•tCYCLE
[(j-0.5)/8]•tCYCLE
logic “1”
VOH,DQ
80%
tQ,DQ,MIN
tQ,DQ,MAX
DQ0
tQOFF,DQ0
tQOFF,DQi
tQOFF,DQ7
...
...
0
1
2
3
4
6
7
8
j
14
15
20%
DQN0
VOL,DQ
logic “0”
tOR,DQ
tOF,DQ
[(j+0.5)/8]•tCYCLE
[(j-0.5)/8]•tCYCLE
logic “1”
VOH,DQ
80%
tQ,DQ,MIN
tQ,DQ,MAX
DQi
...
...
0
1
2
3
4
5
6
7
j
14
15
20%
DQni
VOL,DQ
logic “0”
tOR,DQ
tOF,DQ
[(j+0.5)/8]•tCYCLE
[(j-0.5)/8]•tCYCLE
logic “1”
VOH,DQ
80%
tQ,DQ,MIN
tQ,DQ,MAX
DQ7
...
...
0
1
2
3
4
5
6
7
j
14
15
20%
DQN7
VOL,DQ
logic “0”
tOR,DQ
tOF,DQ
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Serial Interface Receive Timing
Figure62 shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified
view of the pins only a few clock cycles.
The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical
one. Timing events are measured to and from the VREF,RSL level. Because timing intervals are measured in this fashion, it is
necessary to constrain the slew rate of the signals. The rise time (tR,SCK and tRI,SI) and fall time (tF,SCK and tIF,SI) of the signals
are measured from the 20% and 80% points of the full-swing levels.
20% = VIL,SI + 0.2 *(VIH SI
50% = VIL,SI + 0.5 *(VIH SI
80% = VIL,SI + 0.8 *(VIH SI
,
- VIL,SI)
- VIL,SI)
- VIL,SI)
,
,
There is one receiving window defined for each serial interface signal (RST, CMD and SDI pins). This window has a set time (tS,
RQ) and a hold time (tH, RQ) measured around the falling edge of the SCK clock signal.
Figure 62 : Serial Interface Receive Waveforms
tCYC,SCK
logic 0
tH,SCK
tL,SCK
VIH,SI
80%
SCK
VREF,RSL
20%
VIL,SI
logic 1
tF,SCK
tR,SCK
tS,SI
tH,SI
logic 0
VIH,SI
80%
RST
CMD
SDI
VREF,RSL
20%
VIL,SI
logic 1
tIR,SI
tIF,SI
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Serial Interface Transmit Timing
Figure63 shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified
view of the pins and only a few clock cycles are shown.
The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical
one. Timing events are measured to and from the VREF,RSL level. Because timing intervals are measured in this fashion, it is
necessary to constrain the slew rate of the signals. The rise time (tOR,SI) and fall time (tOF,SI) of the signals are measured from
the 20% and 80% points of the full-swing levels.
20% = VOL,SI + 0.2*(VOH,SI - VOL,SI
50% = VOL,SI + 0.5*(VOH,SI - VOL,SI
80% = VOL,SI + 0.8*(VOH,SI - VOL,SI
)
)
)
There is one transmit window defined for the serial interface data signal (SDO pins). This window has a maximum delay time (tQ,
SI,MAX) from the falling edge of the SCK clock signal and a minimum delay time (tQ,SI,MIN) from the next falling edge of the SCK
clock signal.
When the memory component is not selected during a serial device read transaction, it will simply pass the information on the
SDI input to the SDO output. This combinational propagation delay parameter is tP,SI. The tCYC,SCK will need to be increased
during a serial read transaction (relative to the tCYC,SCK value for a serial write transaction) because of the accumulated propa-
gation delay through all of the XDR DRAM devices on the serial interface.
During Initialization, when the serial identification is determined, the SDI-to-SDO path is registered, so the tCYC,SCK value can be
set to the same value as for serial write transactions. See “Initialization” on page42.
Figure 63 : Serial Interface Transmit Waveforms
tCYC,SCK
logic 0
tH,SCK
tL,SCK
VIH,SI
80%
SCK
VREF,RSL
20%
VIL,SI
logic 1
tF,SCK
tR,SCK
tQ,SI,MAX
tQ,SI,MIN
logic 0
VOH,SI
80%
tP,SI
VREF,RSL
SDO
20%
VOL,SI
logic 1
tOR,SI
tOF,SI
Combinational propagation from SDI to
SDO when the device is not selected
during a serial device read transaction.
logic 0
VIH,SI
80%
SDI
VREF,RSL
20%
VIL,SI
logic 1
Version 1.0 Jan. 2005
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XDR DRAM
Package Description
Package Parasitic Summary
Table19 summarizes inductance, capacitance, and resistance values associated with each pin group for the memory compo-
nent. Most of the parameters have maximum values only, however some have both maximum and minimum values.
The first group of parameters are for the CFM/CFMN clock pair pins. They include inductance, capacitance, and resistance
values.
The second group of parameters are for the RQ request pins. They include inductance, mutual inductance, capacitance, and
resistance values. There are also limits on the spread in inductance and capacitance values allowed in any one memory compo-
nent.
The third group of parameters are specific to the DQ data pins and include inductance, mutual inductance, capacitance, and
resistance values. There are limits on the spread in inductance and capacitance values allowed in any one memory component.
The fourth group of parameters are for the serial interface pins. They include inductance and capacitance values.
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Table 19 : Package RSL Parasitic Summary
Parameter and Other Conditions Minimum
Symbol
Maximum
Units
LVTERM
VTERM pin - effective input inductance per four bits
-
2.2
nH
-
-
-
tbd
5.0
tbd
-2400
-3200
-4000
CFM/CFMN pins - effective input capacianceb
LI ,CFM
nH
-
1.8
-
tbd
2.4
tbd
-2400
-3200
-4000
CFM/CFMN pins - effective input capacianceb
CFM/CFMN pins - effective input resistance
CI ,CFM
RI ,CFM
LI ,RQ
pF
Ω
4
15
-
-
-
tbd
5.0
tbd
-2400
-3200
-4000
RSL RQ pins - effective input inductanceb
RSL RQ pins - effective input capacitanceb
nH
tbd
1.8
tbd
tbd
2.4
tbd
-2400
-3200
-4000
CI ,RQ
pF
RI ,RQ
L12,RQ
∆LI,RQ
RSL RQ pins - effective input resistance
4
-
15
0.6
1.8
Ω
Mutual inductance between adjacent RSL RQ signals
nH
nH
Difference in LI,RQ between any RSL RQ pins of a single device
-
Difference in CI between CFM/CFMN average and RSL RQ pins of
single device
∆CI,RQ
-0.06
+0.06
pF
tbd
70
tbd
tbd
130
tbd
-2400
DRSLDQpins-packagedifferentialimpednce
ZPKG,DQ
-3200
note - package trace length should be less than 10mm long.
-4000
Ω
-
-
-
tbd
2.0
tbd
-2400
DRSL DQ pins - effective input capacitancea
-3200
CI ,DQ
pF
pF
-4000
-2400
-
-
-
tbd
0.06
tbd
Difference in CI between DQi and DQNi of each DRSL paira
-3200
∆CI,DQ
-4000
RI ,DQ
LI ,SI
DRSL DQ pins - effective input resistance
4
-
25
Ω
Serial Interface effective input inductance
8.0
nH
Serial Interface effective input capacitance
RST, SCK, CMD
SDI,SDO
CI ,SI
1.7
-
3.0
7.0
pF
pF
a. This is the effective die input capacitance, and does not include package capacitance.
b. CFM/RQ/SI should include package capacitance/Impedance, only DQ deos not include pacage capacitance. This value is a
combination of the device I/O circuitry and package capacitance&inductance
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Figure 64 : Equivalent Circuits for Package Parasitic
Pad
RQ Pin
RQ Pin
L12,RQ
L12,RQ
LI,RQ
CI,RQ
RQ Pin
RI,RQ
GND Pin
Pad
Pad
ZPKG,DQ/2
ZPKG,DQ/2
DQ Pin
DQN Pin
CI,DQ
CI,DQ
RI,DQ
RI,DQ
GND Pin
Pad
Pad
ZPKG,CFM/2
ZPKG,CFM/2
CFM Pin
CFMN Pin
CI,CFM
CI,CFM
RI,CFM
RI,CFM
GND Pin
Pad
LI,SI
SCK,CMD,RST Pin
SDI,SDO Pin
CI,SI
GND Pin
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Package Mechanical Drawing
Figure65 illustrates the XDR DRAM device package and Table20 summarizes the mechanical parameters for that package.
Table 20 : XDR DRAM Package Mechanical Parameters
Symbol Parameter
Min
1.27
0.80
13.9
14.4
Max
1.27
0.80
14.1
14.6
Unit Symbol Parameter
Min
0.93
0.30
0.40
Max
1.13
0.40
0.50
Unit
mm
mm
mm
e1
e2
A
Ball pitch (x-axis)
mm
mm
mm
mm
E
E1
d
Package total thickness
Ball height
Ball pitch (y-axis)
Package body length
Package body width
Ball diameter
D
Figure 65 : XDR DRAM Package Mechanical Drawing (Bottom View)
E1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
A16
L
K
J
H
d
G
F
Top
E
D
C
B
e1
A
D
Bottom
e2
A
Bottom
E
Top
Version 1.0 Jan. 2005
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XDR DRAM
Table of Contents
Overview
1
1
Features
2
3
Key Timing Parameters/Part Numbers
General Description
4
5
Pinouts and Definitions
Pin Description
6
Block Diagram
8
Request Packets
8
Request Packet Formats
Request Field Encoding
Request Field Interaction
Request Interaction Cases
Dynamic Request Scheduling
Memory Operations
10
12
13
18
20
20
22
24
26
27
29
29
29
29
31
37
37
37
39
40
42
43
43
46
46
48
50
52
53
54
54
55
56
56
57
58
59
60
60
61
62
64
66
67
68
68
71
Write Transactions
Read Transactions
Interleaved Transactions
Read/Write Interaction
Propagation Delay
Register Operations
Serial Transactions
Serial Write Transaction
Serial Read Transaction
Register Summary
Maintenance Operations
Refresh Transactions
Interleaved Refresh Transactions
Calibration Transactions
Power State Management
Initialization
XDR DRAM Initialization Overview
XDR DRAM Pattern Load with WDSL Reg
Special Feature Description
Dynamic Width Control
Write Masking
Multiple Bank Sets and the ERAW Feature
Simultaneous Activation
Simultaneous Precharge
Operating Conditions
Electrical Conditions
Timing Conditions
Operating Characteristics
Electrical Characteristics
Supply Current Profile
Timing Characteristics
Timing Parameters
Receive/Transmit Timing
Clocking
RSL RQ Receive Timing
DRSL DQ Receive Timing
DRSL DQ Transmit Timing
Serial Interface Receive Timing
Serial Interface Transmit Timing
Package Description
Package Parasitic Summary
Package Mechanical Drawing
Version 1.0 Jan. 2005
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K4Y5416(/08/04)4UF
XDR DRAM
Copyright © Jan. 2005, Samsung Electronics.
All rights reserved.
Rambus and Rambus logo are trademarks or registered trademarks of Rambus Inc.
XDR is trademark of Rambus Inc.
This document contains advanced information that is subject to change by Samsung Electronics without notice
Document Version 0.1ver.
Samsung Electronics Co. Ltd.
San #16 Banwol-ri, Taean-Eup Hwasung-City, Gyeonggi-Do, KOREA
Telephone: 82-31-208-6369
Fax: 82-31-208-6799
http://www.intl.samsungsemi.com
Version 1.0 Jan. 2005
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