K5L5628JTM-DH180_技术文档

Preliminary

MCP MEMORY

K5L5628JT(B)M

Document Title

Multi-Chip Package MEMORY

256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

Revision History

Revision No. History

Draft Date

Remark

0.0

Initial Draft

August 12, 2004

Preliminary

(256M NOR Flash A-die_rev0.3)

(128M UtRAM M-die_rev0.1)

1.0

Finalize

November 10, 2004 Final

<UtRAM> ....... rev 1.0

- Deleted Synchronous Burst Read and Asynchronous Write Mode

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site.

http://samsungelectronics.com/semiconductors/products/products_index.html

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

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Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Multi-Chip Package MEMORY

256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

FEATURES

• Handshaking Feature

• Operating Temperature : -30°C ~ 85°C

• Package : 115Ball FBGA Type - 8.0mm x 12.0mm

0.8mm ball pitch

- Provides host system with minimum latency by monitoring

RDY

• Erase Suspend/Resume

1.4mm (Max.) Thickness

• Program Suspend/Resume

• Unlock Bypass Program/Erase

• Hardware Reset (RESET)

• Data Polling and Toggle Bits

- Provides a software method of detecting the status of program

or erase completion

• Single Voltage, 1.7V to 1.95V for Read and Write operations

• Organization

- 16,772,216 x 16 bit ( Word Mode Only)

• Read While Program/Erase Operation

• Multiple Bank Architecture

• Endurance

- 16 Banks (16Mb Partition)

100K Program/Erase Cycles Minimum

• OTP Block : Extra 256Byte block

• Read Access Time (@ CL=30pF)

- Asynchronous Random Access Time :

90ns (54MHz) / 80ns (66MHz)

- Synchronous Random Access Time :

88.5ns (54MHz) / 70ns (66MHz)

- Burst Access Time :

14.5ns (54MHz) / 11ns (66MHz)

• Burst Length :

- Continuous Linear Burst

- Linear Burst : 8-word & 16-word with No-wrap & Wrap

• Block Architecture

• Data Retention : 10 years

• Support Common Flash Memory Interface

• Low Vcc Write Inhibit

<UtRAM>

• Process Technology: CMOS

• Organization: 8M x16 bit

• Power Supply Voltage: VCC 2.5~2.7V, VCCQ 1.7~2.0V

• Three State Outputs

• Supports MRS (Mode Register Set)

• MRS control - MRS Pin Control

• Supports Power Saving modes - Partial Array Refresh mode

Internal TCSR

- Eight 4Kword blocks and five hundreds eleven 32Kword

blocks

• Supports Driver Strength Optimization for system environment

power saving.

- Bank 0 contains eight 4 Kword blocks and thirty-one 32Kword

blocks

• Supports Asynchronous 4-Page Read and Asynchronous Write

Operation

• Supports Synchronous Burst Read and Synchronous Burst

Write Operation

• Synchronous Burst(Read/Write) Operation

- Supports 4 word / 8 word / 16 word and Full Page(256 word)

burst

- Supports Linear Burst type & Interleave Burst type

- Latency support : Latency 3 @ 52.9MHz(tCD 12ns)

- Supports Burst Read Suspend in No Clock toggling

- Supports Burst Write Data Masking by /UB & /LB pin control

- Supports WAIT pin function for indicating data availability.

• Max. Burst Clock Frequency : 52.9MHz

- Bank 1 ~ Bank 15 contain four hundred eighty 32Kword blocks

• Reduce program time using the VPP

• Support Single & Quad word accelerate program

• Power Consumption (Typical value, CL=30pF)

- Burst Access Current : 30mA

- Program/Erase Current : 15mA

- Read While Program/Erase Current : 40mA

- Standby Mode/Auto Sleep Mode : 25uA

• Block Protection/Unprotection

- Using the software command sequence

- Last two boot blocks are protected by WP=VIL

- All blocks are protected by VPP=VIL

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

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Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

GENERAL DESCRIPTION

The K5L5628JT(B)M is a Multi Chip Package Memory which combines 256Mbit Synchronous Burst Multi Bank NOR Flash Memory

and 128Mbit Synchronous Burst UtRAM.

256Mbit Synchronous Burst Multi Bank NOR Flash Memory is organized as 16M x16 bits and 128Mbit Synchronous Burst UtRAM is

organized as 8M x16 bits.

In 256Mbit Synchronous Burst Multi Bank NOR Flash Memory, the memory architecture of the device is designed to divide its memory

arrays into 519 blocks with independent hardware protection. This block architecture provides highly flexible erase and program capa-

bility. The NOR Flash consists of sixteen banks. This device is capable of reading data from one bank while programming or erasing

in the other bank.

Regarding read access time, the device provides an 14.5ns burst access time and an 88.5ns initial access time at 54MHz. At 66MHz,

the device provides an 11ns burst access time and 70ns initial access time. The device performs a program operation in units of 16

bits (Word) and an erase operation in units of a block. Single or multiple blocks can be erased. The block erase operation is com-

pleted within typically 0.7 sec. The device requires 15mA as program/erase current.

In 128Mbit Synchronous Burst UtRAM, the device is fabricated by SAMSUNG′s advanced CMOS technology using one transistor

memory cell. The device supports the traditional SRAM like asynchronous bus operation(asynchronous page read and asynchronous

write), and the fully synchronous bus operation(synchronous burst read and synchronous burst write). These two bus operation

modes are defined through the mode register setting. The device also supports the special features for the standby power saving.

Those are the Partial Array Refresh(PAR) mode and internal Temperature Compensated Self Refresh(TCSR) mode.

The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings.

Through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation.

The K5L5628JT(B)M is suitable for use in data memory of mobile communication system to reduce not only mount area but also

power consumption. This device is available in 115-ball FBGA Type.

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Preliminary

MCP MEMORY

K5L5628JT(B)M

PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

10

DNU

ADVf

WP

A3

DNU

A

B

C

D

E

F

NC

A7

CLKf

LB

NC

Vpp

Vccu

WE

ADVu

A8

CLKu

A11

NC

DNU

A6

UB

RESET

MRS

A20

NC

A19

A9

A12

A15

A21

A22

A16

NC

RDYf/

WAITu

A2

A5

A18

A17

DQ1

DQ9

DQ10

DQ2

Vss

A13

A1

A4

NC

Vccu

DQ3

Vccf

DQ11

Vccf

A10

DQ6

DQ13

DQ12

DQ5

NC

A14

G

H

J

A0

Vss

OE

DQ0

DQ8

NC

A23

CEf

CSu

NC

DQ4

Vccqu

NC

DQ15

DQ7

DQ14

NC

Vss

NC

K

L

NC

M

N

P

DNU

115-FBGA: Top View (Ball Down)

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Preliminary

MCP MEMORY

K5L5628JT(B)M

PIN DESCRIPTION

Ball Name

Description

Ball Name

RDYf/WAITu

ADVf

ADVu

MRS

Description

Ready Output (Flash Memory)/Wait(UtRAM)

Address Input Valid (Flash Memory)

Address Input Valid (UtRAM)

Mode Register Set (UtRAM)

Lower Byte Enable (UtRAM)

Upper Byte Enable (UtRAM)

Power Supply (Flash Memory)

Power Supply (UtRAM)

A0 to A22

A23

Address Input Balls (Common)

Address Input Balls (Flash Memory)

Data Input/Output Balls (Common)

Chip Enable (Flash Memory)

Chip Select (UtRAM)

DQ0 to DQ15

CEf

CSu

LB

OE

Output Enable (Common)

UB

RESET

VPP

Hardware Reset (Flash Memory)

Accelerates Programming (Flash Memory)

Write Enable (Common)

Vccf

Vccu

WE

Vccqu

Vss

Data Out Power (UtRAM)

Ground (Common)

WP

Write Protection (Flash Memory)

Clock (Flash Memory)

CLKf

NC

No Connection

CLKu

Clock (UtRAM)

DNU

Do Not Use

ORDERING INFORMATION

K 5 L 56 28 J T(B) M - D H 18

Samsung MCP Memory

2Chip MCP

UtRAM Access Time

18.9ns

Device Type

Demuxed NOR Flash + Demuxed UtRAM

Flash Access Time

14.5ns(CF 54MHz)

NOR Flash Density

56 : 256Mbit, x16

Package

D : FBGA(Lead Free)

Version

1st Generation

UtRAM Density, (Organization)

28 : 128Mbit, x16, Burst

Block Architecture

T = Top Boot Block

B = Bottom Boot Block

Operating Voltage

J : 1.8V/1.8V(NOR), 2.6V/1.8V(UtRAM)

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Preliminary

MCP MEMORY

K5L5628JT(B)M

Figure 1. FUNCTIONAL BLOCK DIAGRAM

Vccf

Vss

Address(A0 to A22)

Address(A23)

OE

WE

CEf

DQ0 to DQ15

256M bit

Flash Memory

RESET

Vpp

WP

CLKf

RDYf

ADVf

Vccu Vccqu

Vss

DQ0 to DQ15

CSu

UB

DQ0 to DQ15

128M bit

UtRAM

LB

CLKu

ADVu

MRS

WAITu

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November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

256M Bit (16M x16)

Synchronous Burst , Multi Bank NOR Flash A-die

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Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 1. PRODUCT LINE-UP

Synchronous/Burst

7B

(54MHz) (66MHz)

Asynchronous

7C

7B

7C

Speed Option

(54MHz) (66MHz)

Max. Initial Access Time (tIAA, ns)

Max. Burst Access Time (tBA, ns)

Max. OE Access Time (tOE, ns)

88.5

14.5

20

70

11

20

Max Access Time (tAA, ns)

90

20

80

20

VCC=1.7V-1.95V

Max CE Access Time (tCE, ns)

Max OE Access Time (tOE, ns)

Table 2. DEVICE BANK DIVISIONS

Bank 0

Bank 1 ~ Bank 15

Mbit

Block Sizes

Mbit

Block Sizes

Eight 4Kwords,

Thirty-one 32Kwords

Four hundred

eighty 32Kwords

16 Mbit

240 Mbit

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Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Top Boot Block Address Table

Bank

Block

BA518

BA517

Block Size

4 Kwords

(x16) Address Range

FFF000h-FFFFFFh

FFE000h-FFEFFFh

4 Kwords

BA516

BA515

BA514

FFD000h-FFDFFFh

FFC000h-FFCFFFh

FFB000h-FFBFFFh

BA513

BA512

BA511

BA510

BA509

BA508

BA507

BA506

BA505

BA504

BA503

BA502

BA501

BA500

BA499

BA498

BA497

BA496

BA495

BA494

BA493

BA492

BA491

BA490

BA489

BA488

BA487

BA486

BA485

BA484

BA483

BA482

BA481

BA480

BA479

BA478

BA477

BA476

BA475

FFA000h-FFAFFFh

FF9000h-FF9FFFh

FF8000h-FF8FFFh

FF0000h-FF7FFFh

FE8000h-FEFFFFh

FE0000h-FE7FFFh

FD8000h-FDFFFFh

FD0000h-FD7FFFh

FC8000h-FCFFFFh

FC0000h-FC7FFFh

FB8000h-FBFFFFh

FB0000h-FB7FFFh

FA8000h-FAFFFFh

FA0000h-FA7FFFh

F98000h-F9FFFFh

F90000h-F97FFFh

F88000h-F8FFFFh

F80000h-F87FFFh

F78000h-F7FFFFh

F70000h-F77FFFh

F68000h-F6FFFFh

F60000h-F67FFFh

F58000h-F5FFFFh

F50000h-F57FFFh

F48000h-F4FFFFh

F40000h-F47FFFh

F38000h-F3FFFFh

F30000h-F37FFFh

F28000h-F2FFFFh

F20000h-F27FFFh

F18000h-F1FFFFh

F10000h-F17FFFh

F08000h-F0FFFFh

F00000h-F07FFFh

EF8000h-EFFFFFh

EF0000h-EF7FFFh

EE8000h-EEFFFFh

EE0000h-EE7FFFh

ED8000h-EDFFFFh

4 Kwords

32 Kwords

32 kwords

32 Kwords

Bank 0

Bank 1

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Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Top Boot Block Address Table

Bank

Block

BA474

BA473

BA472

BA471

BA470

BA469

BA468

BA467

BA466

BA465

BA464

BA463

BA462

BA461

BA460

BA459

BA458

BA457

BA456

BA455

BA454

BA453

BA452

BA451

BA450

BA449

BA448

BA447

BA446

BA445

BA444

BA443

BA442

BA441

BA440

BA439

BA438

BA437

BA436

BA435

BA434

BA433

BA432

BA431

Block Size

32 Kwords

(x16) Address Range

ED0000h-ED7FFFh

EC8000h-ECFFFFh

EC0000h-EC7FFFh

EB8000h-EBFFFFh

EB0000h-EB7FFFh

EA8000h-EAFFFFh

EA0000h-EA7FFFh

E98000h-E9FFFFh

E90000h-E97FFFh

E88000h-E8FFFFh

E80000h-E87FFFh

E78000h-E7FFFFh

E70000h-E77FFFh

E68000h-E6FFFFh

E60000h-E67FFFh

E58000h-E5FFFFh

E50000h-E57FFFh

E48000h-E4FFFFh

E40000h-E47FFFh

E38000h-E3FFFFh

E30000h-E37FFFh

E28000h-E2FFFFh

E20000h-E27FFFh

E18000h-E1FFFFh

E10000h-E17FFFh

E08000h-E0FFFFh

E00000h-E07FFFh

DF8000h-DFFFFFh

DF0000h-DF7FFFh

DE8000h-DEFFFFh

DE0000h-DE7FFFh

DD8000h-DDFFFFh

DD0000h-DD7FFFh

DC8000h-DCFFFFh

DC0000h-DC7FFFh

DB8000h-DBFFFFh

DB0000h-DB7FFFh

DA8000h-DAFFFFh

DA0000h-DA7FFFh

D98000h-D9FFFFh

D90000h-D97FFFh

D88000h-D8FFFFh

D80000h-D87FFFh

D78000h-D7FFFFh

Bank 1

Bank 2

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MCP MEMORY

K5L5628JT(B)M

Table 3-1. Top Boot Block Address Table

Bank

Block

BA430

BA429

BA428

BA427

BA426

BA425

BA424

BA423

BA422

BA421

BA420

BA419

BA418

BA417

BA416

BA415

BA414

BA413

BA412

BA411

BA410

BA409

BA408

BA407

BA406

BA405

BA404

BA403

BA402

BA401

BA400

BA399

BA398

BA397

BA396

BA395

BA394

BA393

BA392

BA391

BA390

BA389

BA388

BA387

BA386

Block Size

32 Kwords

(x16) Address Range

D70000h-D77FFFh

D68000h-D6FFFFh

D60000h-D67FFFh

D58000h-D5FFFFh

D50000h-D57FFFh

D48000h-D4FFFFh

D40000h-D47FFFh

D38000h-D3FFFFh

D30000h-D37FFFh

D28000h-D2FFFFh

D20000h-D27FFFh

D18000h-D1FFFFh

D10000h-D17FFFh

D08000h-D0FFFFh

D00000h-D07FFFh

CF8000h-CFFFFFh

CF0000h-CF7FFFh

CE8000h-CEFFFFh

CE0000h-CE7FFFh

CD8000h-CDFFFFh

CD0000h-CD7FFFh

CC8000h-CCFFFFh

CC0000h-CC7FFFh

CB8000h-CBFFFFh

CB0000h-CB7FFFh

CA8000h-CAFFFFh

CA0000h-CA7FFFh

C98000h-C9FFFFh

C90000h-C97FFFh

C88000h-C8FFFFh

C80000h-C87FFFh

C78000h-C7FFFFh

C70000h-C77FFFh

C68000h-C6FFFFh

C60000h-C67FFFh

C58000h-C5FFFFh

C50000h-C57FFFh

C48000h-C4FFFFh

C40000h-C47FFFh

C38000h-C3FFFFh

C30000h-C37FFFh

C28000h-C2FFFFh

C20000h-C27FFFh

C18000h-C1FFFFh

C10000h-C17FFFh

Bank 2

Bank 3

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MCP MEMORY

K5L5628JT(B)M

Table 3-1. Top Boot Block Address Table

Bank

Block

BA385

BA384

BA383

BA382

BA381

BA380

BA379

BA378

BA377

BA376

BA375

BA374

BA373

BA372

BA371

BA370

BA369

BA368

BA367

BA366

BA365

BA364

BA363

BA362

BA361

BA360

BA359

BA358

BA357

BA356

BA355

BA354

BA353

BA352

BA351

BA350

BA349

BA348

BA347

BA346

BA345

BA344

BA343

BA342

BA341

Block Size

32 Kwords

(x16) Address Range

C08000h-C0FFFFh

C00000h-C07FFFh

BF8000h-BFFFFFh

BF0000h-BF7FFFh

BE8000h-BEFFFFh

BE0000h-BE7FFFh

BD8000h-BDFFFFh

BD0000h-BD7FFFh

BC8000h-BCFFFFh

BC0000h-BC7FFFh

BB8000h-BBFFFFh

BB0000h-BB7FFFh

BA8000h-BAFFFFh

BA0000h-BA7FFFh

B98000h-B9FFFFh

B90000h-B97FFFh

B88000h-B8FFFFh

B80000h-B87FFFh

B78000h-B7FFFFh

B70000h-B77FFFh

B68000h-B6FFFFh

B60000h-B67FFFh

B58000h-B5FFFFh

B50000h-B57FFFh

B48000h-B4FFFFh

B40000h-B47FFFh

B38000h-B3FFFFh

B30000h-B37FFFh

B28000h-B2FFFFh

B20000h-B27FFFh

B18000h-B1FFFFh

B10000h-B17FFFh

B08000h-B0FFFFh

B00000h-B07FFFh

AF8000h-AFFFFFh

AF0000h-AF7FFFh

AE8000h-AEFFFFh

AE0000h-AE7FFFh

AD8000h-ADFFFFh

AD0000h-AD7FFFh

AC8000h-ACFFFFh

AC0000h-AC7FFFh

AB8000h-ABFFFFh

AB0000h-AB7FFFh

AA8000h-AAFFFFh

Bank 3

Bank 4

Bank 5

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MCP MEMORY

K5L5628JT(B)M

Table 3-1. Top Boot Block Address Table

Bank

Block

BA340

BA339

BA338

BA337

BA336

BA335

BA334

BA333

BA332

BA331

BA330

BA329

BA328

BA327

BA326

BA325

BA324

BA323

BA322

BA321

BA320

BA319

BA318

BA317

BA316

BA315

BA314

BA313

BA312

BA311

BA310

BA309

BA308

BA307

BA306

BA305

BA304

BA303

BA302

BA301

BA300

BA299

BA298

BA297

BA296

Block Size

32 Kwords

(x16) Address Range

AA0000h-AA7FFFh

A98000h-A9FFFFh

A90000h-A97FFFh

A88000h-A8FFFFh

A80000h-A87FFFh

A78000h-A7FFFFh

A70000h-A77FFFh

A68000h-A6FFFFh

A60000h-A67FFFh

A58000h-A5FFFFh

A50000h-A57FFFh

A48000h-A4FFFFh

A40000h-A47FFFh

A38000h-A3FFFFh

A30000h-A37FFFh

A28000h-A2FFFFh

A20000h-A27FFFh

A18000h-A1FFFFh

A10000h-A17FFFh

A08000h-A0FFFFh

A00000h-A07FFFh

9F8000h-9FFFFFh

9F0000h-9F7FFFh

9E8000h-9EFFFFh

9E0000h-9E7FFFh

9D8000h-9DFFFFh

9D0000h-9D7FFFh

9C8000h-9CFFFFh

9C0000h-9C7FFFh

9B8000h-9BFFFFh

9B0000h-9B7FFFh

9A8000h-9AFFFFh

9A0000h-9A7FFFh

998000h-99FFFFh

990000h-997FFFh

988000h-98FFFFh

980000h-987FFFh

978000h-97FFFFh

970000h-977FFFh

968000h-96FFFFh

960000h-967FFFh

958000h-95FFFFh

950000h-957FFFh

948000h-94FFFFh

940000h-947FFFh

Bank 5

Bank 6

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MCP MEMORY

K5L5628JT(B)M

Table 3-1. Top Boot Block Address Table

Bank

Block

BA295

BA294

BA293

BA292

BA291

BA290

BA289

BA288

BA287

BA286

BA285

BA284

BA283

BA282

BA281

BA280

BA279

BA278

BA277

BA276

BA275

BA274

BA273

BA272

BA271

BA270

BA269

BA268

BA267

BA266

BA265

BA264

BA263

BA262

BA261

BA260

BA259

BA258

BA257

BA256

Block Size

32 Kwords

(x16) Address Range

938000h-93FFFFh

930000h-937FFFh

928000h-92FFFFh

920000h-927FFFh

918000h-91FFFFh

910000h-917FFFh

908000h-90FFFFh

900000h-907FFFh

8F8000h-8FFFFFh

8F0000h-8F7FFFh

8E8000h-8EFFFFh

8E0000h-8E7FFFh

8D8000h-8DFFFFh

8D0000h-8D7FFFh

8C8000h-8CFFFFh

8C0000h-8C7FFFh

8B8000h-8BFFFFh

8B0000h-8B7FFFh

8A8000h-8AFFFFh

8A0000h-8A7FFFh

898000h-89FFFFh

890000h-897FFFh

888000h-88FFFFh

880000h-887FFFh

878000h-87FFFFh

870000h-877FFFh

868000h-86FFFFh

860000h-867FFFh

858000h-85FFFFh

850000h-857FFFh

848000h-84FFFFh

840000h-847FFFh

838000h-83FFFFh

830000h-837FFFh

828000h-82FFFFh

820000h-827FFFh

818000h-81FFFFh

810000h-817FFFh

808000h-80FFFFh

800000h-807FFFh

Bank 6

32 Kwords

Bank 7

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MCP MEMORY

K5L5628JT(B)M

Table 3-1. Top Boot Boot Block Address Table

Bank

Block

BA255

BA254

BA253

BA252

BA251

BA250

BA249

BA248

BA247

BA246

BA245

BA244

BA243

BA242

BA241

BA240

BA239

BA238

BA237

BA236

BA235

BA234

BA233

BA232

BA231

BA230

BA229

BA228

BA227

BA226

BA225

BA224

BA223

BA222

BA221

BA220

BA219

BA218

BA217

BA216

BA215

BA214

BA213

BA212

Block Size

(x16) Address Range

7F8000h-7FFFFFh

7F0000h-7F7FFFh

7E8000h-7EFFFFh

7E0000h-7E7FFFh

7D8000h-7DFFFFh

7D0000h-7D7FFFh

7C8000h-7CFFFFh

7C0000h-7C7FFFh

7B8000h-7BFFFFh

7B0000h-7B7FFFh

7A8000h-7AFFFFh

7A0000h-7A7FFFh

798000h-79FFFFh

790000h-797FFFh

788000h-78FFFFh

780000h-787FFFh

778000h-77FFFFh

770000h-777FFFh

768000h-76FFFFh

760000h-767FFFh

758000h-75FFFFh

750000h-757FFFh

748000h-74FFFFh

740000h-747FFFh

738000h-73FFFFh

730000h-737FFFh

728000h-72FFFFh

720000h-727FFFh

718000h-71FFFFh

710000h-717FFFh

708000h-70FFFFh

700000h-707FFFh

6F8000h-6FFFFFh

6F0000h-6F7FFFh

6E8000h-6EFFFFh

6E0000h-6E7FFFh

6D8000h-6DFFFFh

6D0000h-6D7FFFh

6C8000h-6CFFFFh

6C0000h-6C7FFFh

6B8000h-6BFFFFh

6B0000h-6B7FFFh

6A8000h-6AFFFFh

6A0000h-6A7FFFh

32 Kwords

32 kwords

32 Kwords

Bank 8

Bank 9

15

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Top Boot Block Address Table

Bank

Block

BA211

BA210

BA209

BA208

BA207

BA206

BA205

BA204

BA203

BA202

BA201

BA200

BA199

BA198

BA197

BA196

BA195

BA194

BA193

BA192

BA191

BA190

BA189

BA188

BA187

BA186

BA185

BA184

BA183

BA182

BA181

BA180

BA179

BA178

BA177

BA176

BA175

BA174

BA173

BA172

BA171

BA170

BA169

BA168

Block Size

32 Kwords

(x16) Address Range

698000h-69FFFFh

690000h-697FFFh

688000h-68FFFFh

680000h-687FFFh

678000h-67FFFFh

670000h-677FFFh

668000h-66FFFFh

660000h-667FFFh

658000h-65FFFFh

650000h-657FFFh

648000h-64FFFFh

640000h-647FFFh

638000h-63FFFFh

630000h-637FFFh

628000h-62FFFFh

620000h-627FFFh

618000h-61FFFFh

610000h-617FFFh

608000h-60FFFFh

600000h-607FFFh

5F8000h-5FFFFFh

5F0000h-5F7FFFh

5E8000h-5EFFFFh

5E0000h-5E7FFFh

5D8000h-5DFFFFh

5D0000h-5D7FFFh

5C8000h-5CFFFFh

5C0000h-5C7FFFh

5B8000h-5BFFFFh

5B0000h-5B7FFFh

5A8000h-5AFFFFh

5A0000h-5A7FFFh

598000h-59FFFFh

590000h-597FFFh

588000h-58FFFFh

580000h-587FFFh

578000h-57FFFFh

570000h-577FFFh

568000h-56FFFFh

560000h-567FFFh

558000h-55FFFFh

550000h-557FFFh

548000h-54FFFFh

540000h-547FFFh

Bank 9

Bank 10

16

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Top Boot Block Address Table

Bank

Block

BA167

BA166

BA165

BA164

BA163

BA162

BA161

BA160

BA159

BA158

BA157

BA156

BA155

BA154

BA153

BA152

BA151

BA150

BA149

BA148

BA147

BA146

BA145

BA144

BA143

BA142

BA141

BA140

BA139

BA138

BA137

BA136

BA135

BA134

BA133

BA132

BA131

BA130

BA129

BA128

BA127

BA126

BA125

BA124

BA123

Block Size

32 Kwords

(x16) Address Range

538000h-53FFFFh

530000h-537FFFh

528000h-52FFFFh

520000h-527FFFh

518000h-51FFFFh

510000h-517FFFh

508000h-50FFFFh

500000h-507FFFh

4F8000h-4FFFFFh

4F0000h-4F7FFFh

4E8000h-4EFFFFh

4E0000h-4E7FFFh

4D8000h-4DFFFFh

4D0000h-4D7FFFh

4C8000h-4CFFFFh

4C0000h-4C7FFFh

4B8000h-4BFFFFh

4B0000h-4B7FFFh

4A8000h-4AFFFFh

4A0000h-4A7FFFh

498000h-49FFFFh

490000h-497FFFh

488000h-48FFFFh

480000h-487FFFh

478000h-47FFFFh

470000h-477FFFh

468000h-46FFFFh

460000h-467FFFh

458000h-45FFFFh

450000h-457FFFh

448000h-44FFFFh

440000h-447FFFh

438000h-43FFFFh

430000h-437FFFh

428000h-42FFFFh

420000h-427FFFh

418000h-41FFFFh

410000h-417FFFh

408000h-40FFFFh

400000h-407FFFh

3F8000h-3FFFFFh

3F0000h-3F7FFFh

3E8000h-3EFFFFh

3E0000h-3E7FFFh

3D8000h-3DFFFFh

Bank 10

Bank 11

Bank 12

17

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Top Boot Block Address Table

Bank

Block

BA122

BA121

BA120

BA119

BA118

BA117

BA116

BA115

BA114

BA113

BA112

BA111

BA110

BA109

BA108

BA107

BA106

BA105

BA104

BA103

BA102

BA101

BA100

BA99

Block Size

32 Kwords

(x16) Address Range

3D0000h-3D7FFFh

3C8000h-3CFFFFh

3C0000h-3C7FFFh

3B8000h-3BFFFFh

3B0000h-3B7FFFh

3A8000h-3AFFFFh

3A0000h-3A7FFFh

398000h-39FFFFh

390000h-397FFFh

388000h-38FFFFh

380000h-387FFFh

378000h-37FFFFh

370000h-377FFFh

368000h-36FFFFh

360000h-367FFFh

358000h-35FFFFh

350000h-357FFFh

348000h-34FFFFh

340000h-347FFFh

338000h-33FFFFh

330000h-337FFFh

328000h-32FFFFh

320000h-327FFFh

318000h-31FFFFh

310000h-317FFFh

308000h-30FFFFh

300000h-307FFFh

2F8000h-2FFFFFh

2F0000h-2F7FFFh

2E8000h-2EFFFFh

2E0000h-2E7FFFh

2D8000h-2DFFFFh

2D0000h-2D7FFFh

2C8000h-2CFFFFh

2C0000h-2C7FFFh

2B8000h-2BFFFFh

2B0000h-2B7FFFh

2A8000h-2AFFFFh

2A0000h-2A7FFFh

298000h-29FFFFh

290000h-297FFFh

288000h-28FFFFh

280000h-287FFFh

278000h-27FFFFh

270000h-277FFFh

Bank 12

BA98

BA97

BA96

BA95

BA94

BA93

BA92

BA91

BA90

BA89

BA88

BA87

Bank 13

BA86

BA85

BA84

BA83

BA82

BA81

BA80

BA79

BA78

18

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Top Boot Block Address Table

Bank

Block

BA77

BA76

BA75

BA74

BA73

BA72

BA71

BA70

BA69

BA68

BA67

BA66

BA65

BA64

BA63

BA62

BA61

BA60

BA59

BA58

BA57

BA56

BA55

BA54

BA53

BA52

BA51

BA50

BA49

BA48

BA47

BA46

BA45

BA44

BA43

BA42

BA41

BA40

BA39

BA38

BA37

BA36

BA35

BA34

BA33

BA32

Block Size

32 Kwords

(x16) Address Range

268000h-26FFFFh

260000h-267FFFh

258000h-25FFFFh

250000h-257FFFh

248000h-24FFFFh

240000h-247FFFh

238000h-23FFFFh

230000h-237FFFh

228000h-22FFFFh

220000h-227FFFh

218000h-21FFFFh

210000h-217FFFh

208000h-20FFFFh

200000h-207FFFh

1F8000h-1FFFFFh

1F0000h-1F7FFFh

1E8000h-1EFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

178000h-17FFFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

148000h-14FFFFh

140000h-147FFFh

138000h-13FFFFh

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

Bank 13

Bank 14

19

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Top Boot Block Address Table

Bank

Block

BA31

BA30

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

BA20

BA19

BA18

BA17

BA16

BA15

BA14

BA13

BA12

BA11

BA10

BA9

Block Size

(x16) Address Range

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

000000h-007FFFh

32 Kwords

Bank 15

BA8

BA7

BA6

BA5

BA4

BA3

BA2

BA1

BA0

Table 3-1-1. Top Boot Block OTP Addresses Table

Block Address

A23 ~ A8

Block Size

128words

(x16) Address Range

OTP

FFFF80h-FFFFFFh

FFFFh

After entering OTP block, any issued addresses should be in the range of OTP block address

20

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Bottom Boot Block Address Table

Bank

Block

BA518

BA517

BA516

BA515

BA514

BA513

BA512

BA511

BA510

BA509

BA508

BA507

BA506

BA505

BA504

BA503

BA502

BA501

BA500

BA499

BA498

BA497

BA496

BA495

BA494

BA493

BA492

BA491

BA490

BA489

BA488

BA487

BA486

BA485

BA484

BA483

BA482

Block Size

(x16) Address Range

FF8000h-FFFFFFh

FF0000h-FF7FFFh

FE8000h-FEFFFFh

FE0000h-FE7FFFh

FD8000h-FDFFFFh

FD0000h-FD7FFFh

FC8000h-FCFFFFh

FC0000h-FC7FFFh

FB8000h-FBFFFFh

FB0000h-FB7FFFh

FA8000h-FAFFFFh

FA0000h-FA7FFFh

F98000h-F9FFFFh

F90000h-F97FFFh

F88000h-F8FFFFh

F80000h-F87FFFh

F78000h-F7FFFFh

F70000h-F77FFFh

F68000h-F6FFFFh

F60000h-F67FFFh

F58000h-F5FFFFh

F50000h-F57FFFh

F48000h-F4FFFFh

F40000h-F47FFFh

F38000h-F3FFFFh

F30000h-F37FFFh

F28000h-F2FFFFh

F20000h-F27FFFh

F18000h-F1FFFFh

F10000h-F17FFFh

F08000h-F0FFFFh

F00000h-F07FFFh

EF8000h-EFFFFFh

EF0000h-EF7FFFh

EE8000h-EEFFFFh

EE0000h-EE7FFFh

ED8000h-EDFFFFh

32 Kwords

32 kwords

32 Kwords

Bank 15

Bank 14

21

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Bottom Boot Block Address Table

Bank

Block

BA481

BA480

BA479

BA478

BA477

BA476

BA475

BA474

BA473

BA472

BA471

BA470

BA469

BA468

BA467

BA466

BA465

BA464

BA463

BA462

BA461

BA460

BA459

BA458

BA457

BA456

BA455

BA454

BA453

BA452

BA451

BA450

BA449

BA448

BA447

BA446

BA445

BA444

BA443

BA442

BA441

BA440

BA439

BA438

Block Size

32 Kwords

(x16) Address Range

ED0000h-ED7FFFh

EC8000h-ECFFFFh

EC0000h-EC7FFFh

EB8000h-EBFFFFh

EB0000h-EB7FFFh

EA8000h-EAFFFFh

EA0000h-EA7FFFh

E98000h-E9FFFFh

E90000h-E97FFFh

E88000h-E8FFFFh

E80000h-E87FFFh

E78000h-E7FFFFh

E70000h-E77FFFh

E68000h-E6FFFFh

E60000h-E67FFFh

E58000h-E5FFFFh

E50000h-E57FFFh

E48000h-E4FFFFh

E40000h-E47FFFh

E38000h-E3FFFFh

E30000h-E37FFFh

E28000h-E2FFFFh

E20000h-E27FFFh

E18000h-E1FFFFh

E10000h-E17FFFh

E08000h-E0FFFFh

E00000h-E07FFFh

DF8000h-DFFFFFh

DF0000h-DF7FFFh

DE8000h-DEFFFFh

DE0000h-DE7FFFh

DD8000h-DDFFFFh

DD0000h-DD7FFFh

DC8000h-DCFFFFh

DC0000h-DC7FFFh

DB8000h-DBFFFFh

DB0000h-DB7FFFh

DA8000h-DAFFFFh

DA0000h-DA7FFFh

D98000h-D9FFFFh

D90000h-D97FFFh

D88000h-D8FFFFh

D80000h-D87FFFh

D78000h-D7FFFFh

Bank 14

Bank 13

22

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Bottom Boot Block Address Table

Bank

Block

BA437

BA436

BA435

BA434

BA433

BA432

BA431

BA430

BA429

BA428

BA427

BA426

BA425

BA424

BA423

BA422

BA421

BA420

BA419

BA418

BA417

BA416

BA415

BA414

BA413

BA412

BA411

BA410

BA409

BA408

BA407

BA406

BA405

BA404

BA403

BA402

BA401

BA400

BA399

BA398

BA397

BA396

BA395

BA394

BA393

Block Size

32 Kwords

(x16) Address Range

D70000h-D77FFFh

D68000h-D6FFFFh

D60000h-D67FFFh

D58000h-D5FFFFh

D50000h-D57FFFh

D48000h-D4FFFFh

D40000h-D47FFFh

D38000h-D3FFFFh

D30000h-D37FFFh

D28000h-D2FFFFh

D20000h-D27FFFh

D18000h-D1FFFFh

D10000h-D17FFFh

D08000h-D0FFFFh

D00000h-D07FFFh

CF8000h-CFFFFFh

CF0000h-CF7FFFh

CE8000h-CEFFFFh

CE0000h-CE7FFFh

CD8000h-CDFFFFh

CD0000h-CD7FFFh

CC8000h-CCFFFFh

CC0000h-CC7FFFh

CB8000h-CBFFFFh

CB0000h-CB7FFFh

CA8000h-CAFFFFh

CA0000h-CA7FFFh

C98000h-C9FFFFh

C90000h-C97FFFh

C88000h-C8FFFFh

C80000h-C87FFFh

C78000h-C7FFFFh

C70000h-C77FFFh

C68000h-C6FFFFh

C60000h-C67FFFh

C58000h-C5FFFFh

C50000h-C57FFFh

C48000h-C4FFFFh

C40000h-C47FFFh

C38000h-C3FFFFh

C30000h-C37FFFh

C28000h-C2FFFFh

C20000h-C27FFFh

C18000h-C1FFFFh

C10000h-C17FFFh

Bank 13

Bank 12

23

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Bottom Boot Block Address Table

Bank

Block

BA392

BA391

BA390

BA389

BA388

BA387

BA386

BA385

BA384

BA383

BA382

BA381

BA380

BA379

BA378

BA377

BA376

BA375

BA374

BA373

BA372

BA371

BA370

BA369

BA368

BA367

BA366

BA365

BA364

BA363

BA362

BA361

BA360

BA359

BA358

BA357

BA356

BA355

BA354

BA353

BA352

BA351

BA350

BA349

BA348

Block Size

32 Kwords

(x16) Address Range

C08000h-C0FFFFh

C00000h-C07FFFh

BF8000h-BFFFFFh

BF0000h-BF7FFFh

BE8000h-BEFFFFh

BE0000h-BE7FFFh

BD8000h-BDFFFFh

BD0000h-BD7FFFh

BC8000h-BCFFFFh

BC0000h-BC7FFFh

BB8000h-BBFFFFh

BB0000h-BB7FFFh

BA8000h-BAFFFFh

BA0000h-BA7FFFh

B98000h-B9FFFFh

B90000h-B97FFFh

B88000h-B8FFFFh

B80000h-B87FFFh

B78000h-B7FFFFh

B70000h-B77FFFh

B68000h-B6FFFFh

B60000h-B67FFFh

B58000h-B5FFFFh

B50000h-B57FFFh

B48000h-B4FFFFh

B40000h-B47FFFh

B38000h-B3FFFFh

B30000h-B37FFFh

B28000h-B2FFFFh

B20000h-B27FFFh

B18000h-B1FFFFh

B10000h-B17FFFh

B08000h-B0FFFFh

B00000h-B07FFFh

AF8000h-AFFFFFh

AF0000h-AF7FFFh

AE8000h-AEFFFFh

AE0000h-AE7FFFh

AD8000h-ADFFFFh

AD0000h-AD7FFFh

AC8000h-ACFFFFh

AC0000h-AC7FFFh

AB8000h-ABFFFFh

AB0000h-AB7FFFh

AA8000h-AAFFFFh

Bank 12

Bank 11

Bank 10

24

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Bottom Boot Block Address Table

Bank

Block

BA347

BA346

BA345

BA344

BA343

BA342

BA341

BA340

BA339

BA338

BA337

BA336

BA335

BA334

BA333

BA332

BA331

BA330

BA329

BA328

BA327

BA326

BA325

BA324

BA323

BA322

BA321

BA320

BA319

BA318

BA317

BA316

BA315

BA314

BA313

BA312

BA311

BA310

BA309

BA308

BA307

BA306

BA305

BA304

BA303

Block Size

32 Kwords

(x16) Address Range

AA0000h-AA7FFFh

A98000h-A9FFFFh

A90000h-A97FFFh

A88000h-A8FFFFh

A80000h-A87FFFh

A78000h-A7FFFFh

A70000h-A77FFFh

A68000h-A6FFFFh

A60000h-A67FFFh

A58000h-A5FFFFh

A50000h-A57FFFh

A48000h-A4FFFFh

A40000h-A47FFFh

A38000h-A3FFFFh

A30000h-A37FFFh

A28000h-A2FFFFh

A20000h-A27FFFh

A18000h-A1FFFFh

A10000h-A17FFFh

A08000h-A0FFFFh

A00000h-A07FFFh

9F8000h-9FFFFFh

9F0000h-9F7FFFh

9E8000h-9EFFFFh

9E0000h-9E7FFFh

9D8000h-9DFFFFh

9D0000h-9D7FFFh

9C8000h-9CFFFFh

9C0000h-9C7FFFh

9B8000h-9BFFFFh

9B0000h-9B7FFFh

9A8000h-9AFFFFh

9A0000h-9A7FFFh

998000h-99FFFFh

990000h-997FFFh

988000h-98FFFFh

980000h-987FFFh

978000h-97FFFFh

970000h-977FFFh

968000h-96FFFFh

960000h-967FFFh

958000h-95FFFFh

950000h-957FFFh

948000h-94FFFFh

940000h-947FFFh

Bank 10

Bank 9

25

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Bottom Boot Block Address Table

Bank

Block

BA302

BA301

BA300

BA299

BA298

BA297

BA296

BA295

BA294

BA293

BA292

BA291

BA290

BA289

BA288

BA287

BA286

BA285

BA284

BA283

BA282

BA281

BA280

BA279

BA278

BA277

BA276

BA275

BA274

BA273

BA272

BA271

BA270

BA269

BA268

BA267

BA266

BA265

BA264

BA263

Block Size

32 Kwords

(x16) Address Range

938000h-93FFFFh

930000h-937FFFh

928000h-92FFFFh

920000h-927FFFh

918000h-91FFFFh

910000h-917FFFh

908000h-90FFFFh

900000h-907FFFh

8F8000h-8FFFFFh

8F0000h-8F7FFFh

8E8000h-8EFFFFh

8E0000h-8E7FFFh

8D8000h-8DFFFFh

8D0000h-8D7FFFh

8C8000h-8CFFFFh

8C0000h-8C7FFFh

8B8000h-8BFFFFh

8B0000h-8B7FFFh

8A8000h-8AFFFFh

8A0000h-8A7FFFh

898000h-89FFFFh

890000h-897FFFh

888000h-88FFFFh

880000h-887FFFh

878000h-87FFFFh

870000h-877FFFh

868000h-86FFFFh

860000h-867FFFh

858000h-85FFFFh

850000h-857FFFh

848000h-84FFFFh

840000h-847FFFh

838000h-83FFFFh

830000h-837FFFh

828000h-82FFFFh

820000h-827FFFh

818000h-81FFFFh

810000h-817FFFh

808000h-80FFFFh

800000h-807FFFh

Bank 9

32 Kwords

Bank 8

26

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 3-1. Bottom Boot Boot Block Address Table

Bank

Block

BA262

BA261

BA260

BA259

BA258

BA257

BA256

BA255

BA254

BA253

BA252

BA251

BA250

BA249

BA248

BA247

BA246

BA245

BA244

BA243

BA242

BA241

BA240

BA239

BA238

BA237

BA236

BA235

BA234

BA233

BA232

BA231

BA230

BA229

BA228

BA227

BA226

BA225

BA224

BA223

BA222

BA221

BA220

BA219

Block Size

(x16) Address Range

7F8000h-7FFFFFh

7F0000h-7F7FFFh

7E8000h-7EFFFFh

7E0000h-7E7FFFh

7D8000h-7DFFFFh

7D0000h-7D7FFFh

7C8000h-7CFFFFh

7C0000h-7C7FFFh

7B8000h-7BFFFFh

7B0000h-7B7FFFh

7A8000h-7AFFFFh

7A0000h-7A7FFFh

798000h-79FFFFh

790000h-797FFFh

788000h-78FFFFh

780000h-787FFFh

778000h-77FFFFh

770000h-777FFFh

768000h-76FFFFh

760000h-767FFFh

758000h-75FFFFh

750000h-757FFFh

748000h-74FFFFh

740000h-747FFFh

738000h-73FFFFh

730000h-737FFFh

728000h-72FFFFh

720000h-727FFFh

718000h-71FFFFh

710000h-717FFFh

708000h-70FFFFh

700000h-707FFFh

6F8000h-6FFFFFh

6F0000h-6F7FFFh

6E8000h-6EFFFFh

6E0000h-6E7FFFh

6D8000h-6DFFFFh

6D0000h-6D7FFFh

6C8000h-6CFFFFh

6C0000h-6C7FFFh

6B8000h-6BFFFFh

6B0000h-6B7FFFh

6A8000h-6AFFFFh

6A0000h-6A7FFFh

32 Kwords

32 kwords

32 Kwords

Bank 7

Bank 6

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Table 3-1. Bottom Boot Block Address Table

Bank

Block

BA218

BA217

BA216

BA215

BA214

BA213

BA212

BA211

BA210

BA209

BA208

BA207

BA206

BA205

BA204

BA203

BA202

BA201

BA200

BA199

BA198

BA197

BA196

BA195

BA194

BA193

BA192

BA191

BA190

BA189

BA188

BA187

BA186

BA185

BA184

BA183

BA182

BA181

BA180

BA179

BA178

BA177

BA176

BA175

Block Size

32 Kwords

(x16) Address Range

698000h-69FFFFh

690000h-697FFFh

688000h-68FFFFh

680000h-687FFFh

678000h-67FFFFh

670000h-677FFFh

668000h-66FFFFh

660000h-667FFFh

658000h-65FFFFh

650000h-657FFFh

648000h-64FFFFh

640000h-647FFFh

638000h-63FFFFh

630000h-637FFFh

628000h-62FFFFh

620000h-627FFFh

618000h-61FFFFh

610000h-617FFFh

608000h-60FFFFh

600000h-607FFFh

5F8000h-5FFFFFh

5F0000h-5F7FFFh

5E8000h-5EFFFFh

5E0000h-5E7FFFh

5D8000h-5DFFFFh

5D0000h-5D7FFFh

5C8000h-5CFFFFh

5C0000h-5C7FFFh

5B8000h-5BFFFFh

5B0000h-5B7FFFh

5A8000h-5AFFFFh

5A0000h-5A7FFFh

598000h-59FFFFh

590000h-597FFFh

588000h-58FFFFh

580000h-587FFFh

578000h-57FFFFh

570000h-577FFFh

568000h-56FFFFh

560000h-567FFFh

558000h-55FFFFh

550000h-557FFFh

548000h-54FFFFh

540000h-547FFFh

Bank 6

Bank 5

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Table 3-1. Bottom Boot Block Address Table

Bank

Block

BA174

BA173

BA172

BA171

BA170

BA169

BA168

BA167

BA166

BA165

BA164

BA163

BA162

BA161

BA160

BA159

BA158

BA157

BA156

BA155

BA154

BA153

BA152

BA151

BA150

BA149

BA148

BA147

BA146

BA145

BA144

BA143

BA142

BA141

BA140

BA139

BA138

BA137

BA136

BA135

BA134

BA133

BA132

BA131

BA130

Block Size

32 Kwords

(x16) Address Range

538000h-53FFFFh

530000h-537FFFh

528000h-52FFFFh

520000h-527FFFh

518000h-51FFFFh

510000h-517FFFh

508000h-50FFFFh

500000h-507FFFh

4F8000h-4FFFFFh

4F0000h-4F7FFFh

4E8000h-4EFFFFh

4E0000h-4E7FFFh

4D8000h-4DFFFFh

4D0000h-4D7FFFh

4C8000h-4CFFFFh

4C0000h-4C7FFFh

4B8000h-4BFFFFh

4B0000h-4B7FFFh

4A8000h-4AFFFFh

4A0000h-4A7FFFh

498000h-49FFFFh

490000h-497FFFh

488000h-48FFFFh

480000h-487FFFh

478000h-47FFFFh

470000h-477FFFh

468000h-46FFFFh

460000h-467FFFh

458000h-45FFFFh

450000h-457FFFh

448000h-44FFFFh

440000h-447FFFh

438000h-43FFFFh

430000h-437FFFh

428000h-42FFFFh

420000h-427FFFh

418000h-41FFFFh

410000h-417FFFh

408000h-40FFFFh

400000h-407FFFh

3F8000h-3FFFFFh

3F0000h-3F7FFFh

3E8000h-3EFFFFh

3E0000h-3E7FFFh

3D8000h-3DFFFFh

Bank 5

Bank 4

Bank 3

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Table 3-1. Bottom Boot Block Address Table

Bank

Block

BA129

BA128

BA127

BA126

BA125

BA124

BA123

BA122

BA121

BA120

BA119

BA118

BA117

BA116

BA115

BA114

BA113

BA112

BA111

BA110

BA109

BA108

BA107

BA106

BA105

BA104

BA103

BA102

BA101

BA100

BA99

Block Size

32 Kwords

(x16) Address Range

3D0000h-3D7FFFh

3C8000h-3CFFFFh

3C0000h-3C7FFFh

3B8000h-3BFFFFh

3B0000h-3B7FFFh

3A8000h-3AFFFFh

3A0000h-3A7FFFh

398000h-39FFFFh

390000h-397FFFh

388000h-38FFFFh

380000h-387FFFh

378000h-37FFFFh

370000h-377FFFh

368000h-36FFFFh

360000h-367FFFh

358000h-35FFFFh

350000h-357FFFh

348000h-34FFFFh

340000h-347FFFh

338000h-33FFFFh

330000h-337FFFh

328000h-32FFFFh

320000h-327FFFh

318000h-31FFFFh

310000h-317FFFh

308000h-30FFFFh

300000h-307FFFh

2F8000h-2FFFFFh

2F0000h-2F7FFFh

2E8000h-2EFFFFh

2E0000h-2E7FFFh

2D8000h-2DFFFFh

2D0000h-2D7FFFh

2C8000h-2CFFFFh

2C0000h-2C7FFFh

2B8000h-2BFFFFh

2B0000h-2B7FFFh

2A8000h-2AFFFFh

2A0000h-2A7FFFh

298000h-29FFFFh

290000h-297FFFh

288000h-28FFFFh

280000h-287FFFh

278000h-27FFFFh

270000h-277FFFh

Bank 3

BA98

BA97

BA96

BA95

BA94

Bank 2

BA93

BA92

BA91

BA90

BA89

BA88

BA87

BA86

BA85

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K5L5628JT(B)M

Table 3-1. Bottom Boot Block Address Table

Bank

Block

BA84

BA83

BA82

BA81

BA80

BA79

BA78

BA77

BA76

BA75

BA74

BA73

BA72

BA71

BA70

BA69

BA68

BA67

BA66

BA65

BA64

BA63

BA62

BA61

BA60

BA59

BA58

BA57

BA56

BA55

BA54

BA53

BA52

BA51

BA50

BA49

BA48

BA47

BA46

BA45

BA44

BA43

BA42

BA41

BA40

BA39

Block Size

32 Kwords

(x16) Address Range

268000h-26FFFFh

260000h-267FFFh

258000h-25FFFFh

250000h-257FFFh

248000h-24FFFFh

240000h-247FFFh

238000h-23FFFFh

230000h-237FFFh

228000h-22FFFFh

220000h-227FFFh

218000h-21FFFFh

210000h-217FFFh

208000h-20FFFFh

200000h-207FFFh

1F8000h-1FFFFFh

1F0000h-1F7FFFh

1E8000h-1EFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

178000h-17FFFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

148000h-14FFFFh

140000h-147FFFh

138000h-13FFFFh

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

Bank 2

Bank 1

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Table 3-1. Bottom Boot Block Address Table

Bank

Block

BA38

BA37

BA36

BA35

BA34

BA33

BA32

BA31

BA30

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

BA20

BA19

BA18

BA17

BA16

BA15

BA14

BA13

BA12

BA11

BA10

BA9

Block Size

(x16) Address Range

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

007000h-007FFFh

006000h-006FFFh

005000h-005FFFh

004000h-004FFFh

003000h-003FFFh

002000h-002FFFh

001000h-001FFFh

000000h-000FFFh

32 Kwords

4 Kwords

Bank 0

BA8

BA7

BA6

4 Kwords

BA5

4 Kwords

BA4

4 Kwords

BA3

4 Kwords

BA2

4 Kwords

BA1

4 Kwords

BA0

4 Kwords

Table 3-1-2. Bottom Boot Block OTP Block Addresses

Block Address

A23 ~ A8

Block Size

128words

(x16) Address Range

OTP

000000h-00007Fh

0000h

After entering OTP block, any issued addresses should be in the range of OTP block address

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K5L5628JT(B)M

PRODUCT INTRODUCTION

The device is a 256Mbit (268,435,456 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply

operating within the range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mecha-

nism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To pro-

vide highly flexible erase and program capability, the device adopts a block memory architecture that divides its memory array into

519 blocks (32-Kword x 511 , 4-Kword x 8, ). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks

can be erased when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the pro-

grammed data, 519 memory blocks can be hardware protected. Regarding read access time, at 54MHz, the device provides a burst

access of 14.5ns with initial access times of 88.5ns at 30pF. At 66MHz, the device provides a burst access of 11ns with initial access

times of 70ns at 30pF. The command set of device is compatible with standard Flash devices. The device uses Chip Enable (CE),

Write Enable (WE), Address Valid(AVD) and Output Enable (OE) to control asynchronous read and write operation. For burst opera-

tions, the device additionally requires Ready (RDY) and Clock (CLK). Device operations are executed by selective command codes.

The command codes to be combined with addresses and data are sequentially written to the command registers using microproces-

sor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Regis-

ter contents also internally latch addresses and data necessary to execute the program and erase operations. The device is

implemented with Internal Program/Erase Routines to execute the program/erase operations. The Internal Program/Erase Routines

are invoked by program/erase command sequences. The Internal Program Routine automatically programs and verifies data at

specified addresses. The Internal Erase Routine automatically pre-programs the memory cell which is not programmed and then

executes the erase operation. The device has means to indicate the status of completion of program/erase operations. The status

can be indicated via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automati-

cally resets itself to the read mode. The device requires only 30mA as burst and asynchronous mode read current and 15 mA for pro-

gram/erase operations.

Table 4. Device Bus Operations

Operation

CE

OE

WE

A0-22

DQ0-15

RESET

CLK

AVD

Asynchronous Read Operation

L

H

Add In

I/O

H

L

Write

L

H

X

L

H

X

H

L

Add In

I/O

High-Z

X

H

L

X

Standby

X

H

X

H

X

Hardware Reset

Load Initial Burst Address

X

Add In

X

H

L

Burst

DOUT

Burst Read Operation

L

H

X

Terminate Burst Read Cycle

H

X

L

X

H

X

High-Z

I/O

X

Terminate Burst Read Cycle via RESET

X

Terminate Current Burst Read Cycle and Start

New Burst Read Cycle

Add In

H

Note : L=VIL (Low), H=VIH (High), X=Don’t Care.

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K5L5628JT(B)M

COMMAND DEFINITIONS

The device operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to

select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writ-

ing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The

defined valid register command sequences are stated in Table 5.

Table 5. Command Sequences

Command Definitions

Cycle

1st Cycle 2nd Cycle 3rd Cycle

4th Cycle

5th Cycle 6th Cycle

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

RA

RD

Asynchronous Read

1

XXXH

F0H

Reset(Note 5)

1

4

3

2

5

6

1

555H

AAH

2AAH

55H

(DA)555H

90H

(DA)X00H

ECH

Autoselect

Manufacturer ID(Note 6)

555H

AAH

2AAH

55H

(DA)555H

90H

(DA)X01H

Note6

Autoselect

Device ID(Note 6)

555H

AAH

2AAH

55H

(BA)555H

90H

(BA)X02H

00H/01H

(DA)X03H

0H/1H

Autoselect

Block Protection Verify(Note 7)

555H

AAH

2AAH

55H

(DA)555H

90H

Autoselect

Handshaking(Note 6, 8)

555H

AAH

2AAH

55H

555H

PA

Program

A0H

PD

555H

AAH

2AAH

55H

555H

Unlock Bypass

20H

XXX

PA

Unlock Bypass Program(Note 9)

Unlock Bypass Block Erase(Note 9)

Unlock Bypass Chip Erase(Note 9)

Unlock Bypass Reset

A0H

PD

XXX

BA

80H

30H

XXXH

80H

XXXH

10H

XXXH

90H

XXXH

00H

XXX

PA1

PA2

PD2

555H

80H

PA3

PD3

PA4

PD4

Quadruple word Accelerated Program(Note 10)

Chip Erase

A5H

PD1

2AAH

55H

555H

AAH

555H

AAH

555H

AAH

2AAH

55H

555H

10H

BA

555H

AAH

2AAH

55H

555H

80H

2AAH

55H

Block Erase

30H

(DA)XXXH

B0H

Erase Suspend (Note 11)

Erase Resume (Note 12)

Program Suspend (Note13)

Program Resume (Note12)

(DA)XXXH

30H

(DA)XXXH

B0H

(DA)XXXH

30H

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K5L5628JT(B)M

Table 5. Command Sequences (Continued)

Command Definitions

Cycle

1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle

Add

Block Protection/Unprotection (Note 14)

Data

XXX

60H

XXX

60H

ABP

60H

3

Add

(DA)X55H

98H

CFI Query (Note 15)

Data

1

3

4

Add

Set Burst Mode Configuration Register (Note 16)

Data

555H

AAH

2AAH

55H

(CR)555H

C0H

Addr

555H

AAH

2AAH

55H

555H

70H

Enter OTP Block Region

Data

Addr

555H

AAH

2AAH

55H

555H

75H

XXX

00H

Exit OTP Block Region

Data

Notes:

1. RA : Read Address , PA : Program Address, RD : Read Data, PD : Program Data , BA : Block Address (A23 ~ A12)

DA : Bank Address (A23 ~ A20) , ABP : Address of the block to be protected or unprotected, CR : Configuration Register Setting

2. The 4th cycle data of autoselect mode and RD are output data. The others are input data.

3. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD and Device ID.

4. Unless otherwise noted, address bits A23–A11 are don’t cares.

5. The reset command is required to return to read mode.

If a bank entered the autoselect mode during the erase suspend mode, writing the reset command returns that bank to the erase suspend mode.

If a bank entered the autoselect mode during the program suspend mode, writing the reset command returns that bank to the program suspend mode.

If DQ5 goes high during the program or erase operation, writing the reset command returns that bank to read mode or erase suspend mode if that

bank was in erase suspend mode.

6. The 3rd and 4th cycle bank address of autoselect mode must be same.

Device ID Data : "22FCH" for Top Boot Block Device, "22FDH" for Bottom Boot Block Device

7. 00H for an unprotected block and 01H for a protected block.

8. 0H for handshaking, 1H for non-handshaking

9. The unlock bypass command sequence is required prior to this command sequence.

10. Quadruple word accelerated program is invoked only at Vpp=V^ID,Vpp setup is required prior to this command sequence.

PA1, PA2, PA3, PA4 have the same A23~A2 address.

11. The system may read and program in non-erasing blocks when in the erase suspend mode.

The system may enter the autoselect mode when in the erase suspend mode.

The erase suspend command is valid only during a block erase operation, and requires the bank address.

12. The erase/program resume command is valid only during the erase/program suspend mode, and requires the bank address.

13. This mode is used only to enable Data Read by suspending the Program operation.

14. Set block address(BA) as either A6 = V^IH, A1 = VIH and A0 = VIL for unprotected or A6 = VIL, A1 = VIH and A0 = VIL for protected.

15. Command is valid when the device is in Read mode or Autoselect mode.

16. See "Set Burst Mode Congiguration Register" for details.

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K5L5628JT(B)M

DEVICE OPERATION

To write a command or command sequence (which includes programming data to the device and erasing blocks of memory), the sys-

tem must drive CLK, WE and CE to VIL and OE to VIH when providing address or data. The device provide the unlock bypass mode

to save its program time for program operation. Unlike the standard program command sequence which is comprised of four bus

cycles, only two program cycles are required to program a word in the unlock bypass mode. One block, multiple blocks, or the entire

device can be erased. Table 3 indicates the address space that each block occupies. The device’s address space is divided into six-

teen banks: Bank 0 contains the boot/parameter blocks, and the other banks(from Bank 1 to 15) consist of uniform blocks. A “bank

address” is the address bits required to uniquely select a bank. Similarly, a “block address” is the address bits required to uniquely

select a block. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Character-

istics section contains timing specification tables and timing diagrams for write operations.

Read Mode

The device automatically enters to asynchronous read mode after device power-up. No commands are required to retrieve data in

asynchronous mode. After completing an Internal Program/Erase Routine, each bank is ready to read array data. The reset com-

mand is required to return a bank to the read(or erase-suspend-read)mode if DQ5 goes high during an active program/erase opera-

tion, or if the bank is in the autoselect mode.

The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. That

means device enters burst read mode from asynchronous read mode to burst read mode using CLK and AVD signal. When the burst

read is finished(or terminated), the device return to asynchronous read mode automatically.

Asynchronous Read Mode

For the asynchronous read mode a valid address should be asserted on A0-A23, while driving AVD and CE to VIL. WE should

remain at VIH . The data will appear on DQ0-DQ15. Since the memory array is divided into sixteen banks, each bank remains

enabled for read access until the command register contents are altered.

Address access time (tAA) is equal to the delay from valid addresses to valid output data. The chip enable access time(tCE) is the

delay from the falling edge of CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of

OE to valid data at the output. To prevent the memory content from spurious altering during power transition, the initial state machine

is set for reading array data upon device power-up, or after a hardware reset.

Synchronous (Burst) Read Mode

The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the sys-

tem should determine how many clock cycles are desired for the initial word(tIACC) of each burst access and what mode of burst

operation is desired using "Burst Mode Configuration Register" command sequences. See "Set Burst Mode Configuration" for further

details. The status data also can be read during burst read mode by using AVD signal with a bank address. To initiate the synchro-

nous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed

the program or erase operation.

Continuous Linear Burst Read

The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. Note that

the device is enabled for asynchronous mode when it first powers up. The initial word is output tIAA after the rising edge of the first

CLK cycle. Subsequent words are output tBA after the rising edge of each successive clock cycle, which automatically increments the

internal address counter. Note that the device has internal address boundary that occurs every 16 words. When the device is cross-

ing the first word boundary, additional clock cycles are needed before data appears for the next address. The number of addtional

clock cycle can varies from zero to three cycles, and the exact number of additional clock cycle depends on the starting address of

burst read.(Refer to Figure 13) The RDY output indicates this condition to the system by pulsing low. The device will continue to out-

put sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until the

system asserts CE high, RESET low or AVD low in conjunction with a new address.(See Table 4.) The reset command does not ter-

minate the burst read operation.

If the host system crosses the bank boundary while reading in burst mode, and the accessed bank is not programming or erasing, a

additional clock cycles are needed as previously mentioned. If the host system crosses the bank boundary while the accessed bank

is programming or erasing, that is busy bank, the synchronous read will be terminated.

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MCP MEMORY

K5L5628JT(B)M

8-,16-Word Linear Burst Read

As well as the Continuous Linear Burst Mode, there are two(8 & 16 word) linear wrap & no-wrap mode, in which a fixed number of

words are read from consecutive addresses. In these modes, the addresses for burst read are determined by the group within which

the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given

mode.(See Table. 6)

Table 6. Burst Address Groups(Wrap mode only)

Burst Mode

8 word

Group Size

8 words

Group Address Ranges

0-7h, 8-Fh, 10-17h, ....

0-Fh, 10-1Fh, 20-2Fh, ....

16 word

16words

As an example:

In wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst

sequence would be 2-3-4-5-6-7-0-1h. The burst sequence begins with the starting address written to the device, but wraps back to

the first address in the selected group. In a similar manner, 16-word wrap mode begin their burst sequence on the starting address

written to the device, and then wrap back to the first address in the selected address group.

In no-wrap mode case, if the starting address in the 8-word mode is 2h, the no-wrap burst sequence would be 2-3-4-5-6-7-8-9h. The

burst sequence begins with the starting address written to the device, and continue to the 8th address from starting address. In a sim-

ilar manner, 16-word no-wrap mode begin their burst sequence on the starting address written to the device, and continue to the 16th

address from starting address. Also, when the address cross the word boundary in no-wrap mode, same number of additional clock

cycles as continuous linear mode is needed.

Programmable Wait State

The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD is

driven active for burst read mode. Upon power up, the number of total initial access cycles defaults to seven.

Handshaking

The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word

of burst data is ready to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable wait

state configuration.(See "Set Burst Mode Configuration Register" for details.) The rising edge of RDY after OE goes low indicates

the initial word of valid burst data. Using the autoselect command sequence the handshaking feature may be verified in the device.

Set Burst Mode Configuration Register

The device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read

mode. The burst mode configuration register must be set before the device enter burst mode.

The burst mode configuration register is loaded with a three-cycle command sequences. On the third cycle, the data should be C0h,

address bits A11-A0 should be 555h, and address bits A18-A12 set the code to be latched. The device will power up or after a hard-

ware reset with the default setting.

Table 7. Burst Mode Configuration Register Table

Address Bit

Function

Settings(Binary)

1 = RDY active one clock cycle before data

0 = RDY active with data(default)

A18

RDY Active

A17

A16

000 = Continuous(default)

001 = 8-word linear with wrap

010 = 16-word linear with wrap

011 = 8-word linear with no-wrap

100 = 16-word linear with no-wrap

101 ~ 111 = Reserve

Burst Read Mode

A15

A14

A13

000 = Data is valid on the 4th active CLK edge after AVD transition to V^IH

001 = Data is valid on the 5th active CLK edge after AVD transition to V^IH

010 = Data is valid on the 6th active CLK edge after AVD transition to V^IH

011 = Data is valid on the 7th active CLK edge after AVD transition to V^IH(default)

Programmable Wait State

100 = Reserve

101 = Reserve

110 = Reserve

111 = Reserve

A12

Programmable Wait State Configuration

This feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be avail-

able. This value is determined by the input frequency of the device. Address bits A14-A12 determine the setting. (See Burst Mode

Configuration Register Table)

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The Programmable wait state setting instructs the device to set a particular number of clock cycles for the initial access in burst

mode. Note that hardware reset will set the wait state to the default setting, that is 7 initial cycles.

Burst Read Mode Setting

The device supports five different burst read modes : continuous linear mode, 8 and 16 word linear burst modes with wrap and 8 and

16 word linear burst modes with no-wrap.

RDY Configuration

By default, the RDY pin will be high whenever there is valid data on the output. The device can be set so that RDY goes active one

data cycle before active data. Address bit A18 determine this setting. Note that RDY always go high with valid data in case of word

boundary crossing.

Table 8. Burst Address Sequences

Burst Address Sequence(Decimal)

Start

Addr.

Continuous Burst

0-1-2-3-4-5-6...

1-2-3-4-5-6-7...

2-3-4-5-6-7-8...

8-word Burst

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

16-word Burst

0

1

2

0-1-2-3-4-....-13-14-15

1-2-3-4-5-....-14-15-0

2-3-4-5-6-....-15-0-1

Wrap

.

0

1

2

0-1-2-3-4-5-6...

1-2-3-4-5-6-7...

2-3-4-5-6-7-8...

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9

0-1-2-3-4-....-13-14-15

1-2-3-4-5-....-14-15-16

2-3-4-5-6-....-15-16-17

No-wrap

.

Autoselect Mode

By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by

asynchronous read mode. The system can then read autoselect codes from the internal register(which is separate from the memory

array). Standard asynchronous read cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer

and device type by reading a binary code. In addition, this mode allows the host system to verify the block protection or unprotection.

Table 5 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank

that is in the read mode, erase-suspend-read mode or program-suspend-read mode. The autoselect command may not be written

while the device is actively programming or erasing in the device. The autoselect command sequence is initiated by first writing two

unlock cycles. This is followed by a third write cycle that contains the address and the autoselect command. Note that the block

address is needed for the verification of block protection. The system may read at any address within the same bank any number of

times without initiating another autoselect command sequence. And the burst read should be prohibited during Autoselect Mode. To

terminate the autoselect operation, write Reset command(F0H) into the command register.

Table 9. Autoselct Mode Description

Description

Manufacturer ID

Address

(DA) + 00H

(DA) + 01H

(BA) + 02H

(DA) + 03H

Read Data

ECH

Device ID

22FCH(Top Boot Block), 22FDH(Bottom Boot Block)

01H (protected), 00H (unprotected)

Block Protection/Unprotection

Handshaking

0H : handshaking, 1H : non-handshaking

Standby Mode

When the CE and RESET inputs are both held at VCC ± 0.2V or the system is not reading or writing, the device enters Stand-by mode

to minimize the power consumption. In this mode, the device outputs are placed in the high impedence state, independent of the OE

input. When the device is in either of these standby modes, the device requires standard access time (tCE ) for read access before it

is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is

completed. ICC5 in the DC Characteristics table represents the standby current specification.

Automatic Sleep Mode

The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode.

When addresses remain stable for tAA+60ns, the device automatically enables this mode. The automatic sleep mode is independent

of the CE, WE, and OE control signals. In a sleep mode, output data is latched and always available to the system. When addresses

are changed, the device provides new data without wait time. Automatic sleep mode current is equal to standby mode current.

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Output Disable Mode

When the OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state.

Block Protection & Unprotection

To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in

the device are protected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first

two cycles are written: addresses are don’t care and data is 60h. Using the third cycle, the block address (ABP) and command (60h)

is written, while specifying with addresses A6, A1 and A0 whether that block should be protected (A6 = VIL, A1 = VIH, A0 = VIL) or

unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can continue to protect or unprotect additional cycles, or

exit the sequence by writing F0h (reset command).

The device offers three types of data protection at the block level:

• The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block.

• When WP is at VIL, the two outermost blocks are protected.

• When VPP is at VIL, all blocks are protected.

Note that user never float the Vpp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL.

Hardware Reset

The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least

a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write com-

mands for the duration of the RESET pulse. The device also resets the internal state machine to asynchronous read mode. To

ensure data integrity, the interrupted operation should be reinitiated once the device is ready to accept another command sequence.

As previously noted, when RESET is held at VSS ± 0.2V, the device enters standby mode. The RESET pin may be tied to the system

reset pin. If a system reset occurs during the Internal Program or Erase Routine, the device will be automatically reset to the asyn-

chronous read mode; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. If RESET is

asserted during a program or erase operation, the device requires a time of tREADY (during Internal Routines) before the device is

ready to read data again. If RESET is asserted when a program or erase operation is not executing, the reset operation is completed

within a time of tREADY (not during Internal Routines). tRH is needed to read data after RESET returns to VIH. Refer to the AC Char-

acteristics tables for RESET parameters and to Figure 6 for the timing diagram.

Software Reset

The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The

addresses are in Don’t Care state. The reset command may be written between the sequence cycles in an erase command

sequence before erasing begins, or in a program command sequence before programming begins. If the device begins erasure or

programming, the reset command is ignored until the operation is completed. If the program command sequence is written to a bank

that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset com-

mand is valid between the sequence cycles in an autoselect command sequence. In an autoselect mode, the reset command must

be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset com-

mand returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend

mode, writing the reset command returns that bank to the program-suspend-read mode. If DQ5 goes high during a program or an

erase operation, writing the reset command returns the banks to the read mode. (or erase-suspend-read mode if the bank was in

Erase Suspend)

Program

The device can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Pro-

gram Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles

are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location

and the data to be programmed at that location are written. The device automatically generates adequate program pulses and veri-

fies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to

provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored.

Note that a hardware reset during a program operation will cause data corruption at the corresponding location.

Accelerated Program Operation

The device provides Single/Quadruple word accelerated program operations through the Vpp input. Using this mode, faster manu-

facturing throughput at the factory is possible. When VID is asserted on the Vpp input, the device automatically enters the Unlock

Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for

program operations. By removing VID returns the device to normal operation mode.

Note that Read while Accelerated Programm and Program suspend mode are not guaranteed

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Single word accelerated program operation

The system would use two-cycle program sequence (One-cycle (XXX - A0H) is for single word program command, and Next one-

cycle (PA - PD) is for program address and data ).

Quadruple word accelerated program operation

As well as Single word accelerated program, the system would use five-cycle program sequence (One-cycle (XXX - A5H) is for qua-

druple word program command, and four cycles are for program address and data).

• Only four words programming is possible

• Each program address must have the same A23~A2 address

• The device automatically generates adequate program pulses and ignores other command after program command

Unlock Bypass

The device provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase and chip

erase operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command

sequence or the assertion of VID on VPP pin. Unlike the standard program/erase command sequence that contains four/six bus

cycles, the unlock bypass program/erase command sequence needs only two bus cycles. The unlock bypass mode is engaged by

issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by

a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass pro-

gram/erase command sequence is necessary. The unlock bypass program command sequence is comprised of only two bus cycles;

writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the

only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is com-

prised of two bus cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase com-

mand(80H-10H). This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock

bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset

command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data

(00H). Then, the device returns to the read mode.

To enter the unlock bypass mode in hardware level, the VID also can be used. By assertion VID on the VPP pin, the device enters the

unlock bypass mode. Also, the all blocks are temporarily unprotected when the device using the VID for unlock bypass mode. To exit

the unlock bypass mode, just remove the asserted VID from the VPP pin.(Note that user never float the Vpp, that is, Vpp is always

connected with VIH, VIL or VID.).

Chip Erase

To erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus

cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two

more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the

entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE pulse in the

command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.

Block Erase

To erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six

bus cycles to write the command sequence shown in Table 5. After the first two "unlock" cycles, the erase setup command (80H) is

written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine

automatically pre-programs and verifies the entire memory prior to erasing it. Multiple blocks can be erased sequentially by writing

the sixth bus-cycle. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command

(30H) can be written to perform the Multi-Block Erase. For the Multi-Block Erase, only sixth cycle(block address and 30H) is

needed.(Similarly, only second cycle is needed in unlock bypass block erase.) An 50us (typical) "time window" is required between

the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block

Erase command will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time

window" to latch the Block Erase command. During the 50us of "time window", any command other than the Block Erase or the

Erase Suspend command written to the device will reset the device to read mode. After the 50 us of "time window", the Block Erase

command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the

exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command

during Block Erase operation.

The device provides accelerated erase operations through the Vpp input. When VID is asserted on the Vpp input, the device auto-

matically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to

reduce the time required for erase. By removing VID returns the device to normal operation mode.

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Erase Suspend / Resume

The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. Also, it is pos-

sible to protect or unprotect of the block that is not being erased in erase suspend mode. The Erase Suspend command is only valid

during the Block Erase operation including the time window of 50 us. The Erase Suspend command is not valid while the Chip Erase

or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation,

the device requires a maximum of 20 us(recovery time) to suspend the erase operation. Therefore system must wait for 20us(recov-

ery time) to read the data from the bank which include the block being erased. Otherwise, system can read the data immediately from

a bank which don’t include the block being erased without recovery time(max. 20us) after Erase Suspend command. And, after the

maximum 20us recovery time, the device is availble for programming data in a block that is not being erased. But, when the Erase

Suspend command is written during the block erase time window (50 us) , the device immediately terminates the block erase time

window and suspends the erase operation. The system may also write the autoselect command sequence when the device is in the

Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Sus-

pend or Erase Resume command is executed, the addresses are in Don't Care state.

Program Suspend / Resume

The device provides the Program Suspend/Resume mode. This mode is used to enable Data Read by suspending the Program

operation. The device accepts a Program Suspend command in Program mode(including Program operations performed during

Erase Suspend) but other commands are ignored. After input of the Program Suspend command, 2us is needed to enter the Pro-

gram Suspend Read mode. Therefore system must wait for 2us(recovery time) to read the data from the bank which include the

block being programmed. Othwewise, system can read the data immediately from a bank which don't include block being pro-

grammed without ecovery time(max. 2us) after Program Suspend command. Like an Erase Suspend mode, the device can be

returned to Program mode by using a Program Resume command.

Read While Write Operation

The device is capable of reading data from one bank while writing in the other banks. This is so called the Read While Write opera-

tion. An erase operation may also be suspended to read from or program to another location within the same bank(except the block

being erased). The Read While Write operation is prohibited during the chip erase operation. Figure 12 shows how read and write

cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-write current

specifications.

OTP Block Region

The OTP Block feature provides a 256-byte Flash memory region that enables permanent part identification through an Electronic

Serial Number (ESN). The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to untilize the that

block in any manner they choose. The customer-lockable OTP Block has the Protection Verify Bit (DQ0) set to a "0" for Unlocked

state or a "1" for Locked state.

The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence"

at Table8). After the system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the

addresses (FFFF80h~FFFFFFh) normally and may check the Protection Verify Bit (DQ0) by using the "Autoselect Block Protection

Verify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP Block"

Command suquence, a hardware reset or until power is removed from the device. On power-up, or following a hardware reset, the

device reverts to sending commands to main blocks. Note that the Accelerated function and unlock bypass modes are not available

when the OTP Block is enabled.

Customer Lockable

In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated

programming and Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block

is started by writing the "Enter OTP Block" Command sequence, and then the "Block Protection" Command sqeunce (Table 8) with

an OTP Block address. Hardware reset terminates Locking operation, and then makes exiting from OTP Block. The Locking opera-

tion has to be above 100us.

The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking

and none of the bits in the OTP Block space can be modified in any way.

Low VCC Write Inhibit

To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than VLKO. If the Vcc

< VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the

device will reset itself to the read mode.Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user’s

responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above VLKO.

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Write Pulse “Glitch” Protection

Noise pulses of less than 5ns (typical) on OE, CE, AVD or WE do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE = VIL , CE = VIH or WE = VIH. To initiate a write cycle, CE and WE must be a log-

ical zero while OE is a logical one.

Power-up Protection

To avoid initiation of a write cycle during VCC power-up, RESET low must be asserted during Power-up. After RESET goes high. the

device is reset to the read mode.

FLASH MEMORY STATUS FLAGS

The device has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address

must include bank address being executed internal routine operation. The status is indicated by raising the device status flag via cor-

responding DQ pins. This status read is supported in burst mode and asynchronous mode. The status data can be read during burst

read mode by using AVD signal with a bank address. That means status read is supported in synchronous mode. If status read is

performed, the data provided in the burst read is identical to the data in the initial access. To initiate the synchronous read again, a

new address and AVD pulse is needed after the host has completed status reads or the device has completed the program or erase

operation. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2.

Table 10. Hardware Sequence Flags

Status

DQ7

0

DQ6

Toggle

DQ5

DQ3

DQ2

1

Programming

0

1

Block Erase or Chip Erase

Erase Suspend Read

Toggle

Erase Suspended

Block

Toggle

(Note 1)

1

Data

Toggle

1

0

Data

0

Data

0

Non-EraseSuspended

Block

Erase Suspend Read

Data

DQ7

Data

1

In Progress

Erase Suspend

Program

Non-EraseSuspended

Block

Program Suspended

Block

Toggle

(Note 1)

Program Suspend Read

0

Non- program

Suspended Block

Data

No

Toggle

Programming

DQ7

0

Toggle

1

0

1

0

Exceeded

Time Limits

Block Erase or Chip Erase

Erase Suspend Program

(Note 2)

No

Toggle

DQ7

Notes :

1. DQ2 will toggle when the device performs successive read operations from the erase/program suspended block.

2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.

DQ7 : Data Polling

When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as

an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data

written to DQ7. When a user attempts to read the block being erased, DQ7 will be low. If the device is placed in the Erase/Program

Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is

being erase suspended, DQ7 will be high. And, if the system tries to read an address which belongs to a block that is being program

suspended, the output will be the true data of DQ7 itself. If a non-erase-suspended or non-program-suspended block address is

read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements

the data for approximately 1µs and the device then returns to the Read Mode without changing data in the block. If an attempt is

made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read

Mode without erasing the data in the block.

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DQ6 : Toggle Bit

Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state,

DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Suspend

Mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of DQ6.

If an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at DQ6. If an

attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read Mode

without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100µs and

the device then returns to the Read Mode without erasing the data in the block.

DQ5 : Exceed Timing Limits

If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.

DQ3 : Block Erase Timer

The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50µs of the block erase time win-

dow expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write

commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase

time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been

accepted, the software may check the status of DQ3 following each block erase command.

DQ2 : Toggle Bit 2

The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When

the device executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is

in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the

Erase/Program Suspend mode, DQ2 toggles only if an address in the erasing or programming block is read. If a non-erasing or non-

programmed block address is read during the Erase/Program Suspend mode, then DQ2 will produce valid data. DQ2 will go High if

the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode.

RDY: Ready

Normally the RDY signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. If RDY is low

state, data is not valid at expected time, and if high state, data is valid. Note that, if CE is low and OE is high, the RDY is high state.

Start

Yes

No

DQ7 = Data ?

No

DQ6 = Toggle ?

Yes

No

DQ5 = 1 ?

Yes

No

Yes

DQ6 = Toggle ?

DQ7 = Data ?

Yes

Fail

No

Pass

Fail

Figure 2. Toggle Bit Algorithms

Figure 1. Data Polling Algorithms

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Commom Flash Memory Interface

Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific informa-

tion of the device, such as memory size and electrical features. Once this information has been obtained, the system software will

know which command sets to use to enable flash writes, block erases, and control the flash component.

When the system writes the CFI command(98H) to address 55H , the device enters the CFI mode. And then if the system writes the

address shown in Table 11, the system can read the CFI data. Query data are always presented on the lowest-order data out-

puts(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the

reset command.

Table 11. Common Flash Memory Interface Code

Addresses

Description

Data

(Word Mode)

10H

11H

12H

0051H

0052H

0059H

Query Unique ASCII string "QRY"

13H

14H

0002H

0000H

Primary OEM Command Set

15H

16H

0040H

0000H

Address for Primary Extended Table

17H

18H

0000H

Alternate OEM Command Set (00h = none exists)

19H

1AH

0000H

Address for Alternate OEM Extended Table (00h = none exists)

Vcc Min. (write/erase)

D7-D4: volt, D3-D0: 100 millivolt

1BH

1CH

0017H

0019H

Vcc Max. (write/erase)

D7-D4: volt, D3-D0: 100 millivolt

Vpp(Acceleration Program) Supply Minimum

00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV

1DH

1EH

0085H

0095H

Vpp(Acceleration Program) Supply Maximum

00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV

Typical timeout per single word write 2^Nus

1FH

20H

21H

22H

23H

24H

25H

26H

27H

0004H

0000H

000AH

0013H

0005H

0000H

0004H

0000H

0019H

Typical timeout for Min. size buffer write 2^Nus(00H = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms(00H = not supported)

Max. timeout for word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical(00H = not supported)

Device Size = 2^Nbyte

28H

29H

0000H

Flash Device Interface description

2AH

2BH

0000H

Max. number of byte in multi-byte write = 2^N

Number of Erase Block Regions within device

2CH

0002H

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MCP MEMORY

K5L5628JT(B)M

Table 11. Common Flash Memory Interface Code (Continued)

Description

Addresses

(Word Mode)

Data

2DH

2EH

2FH

30H

0007H

0000H

0020H

0000H

Erase Block Region 1 Information

Bits 0~15: y+1=block number

Bits 16~31: block size= z x 256bytes

31H

32H

33H

34H

00FEH

0001H

0000H

0001H

Erase Block Region 2 Information

Erase Block Region 3 Information

35H

36H

37H

38H

0000H

39H

3AH

3BH

3CH

0000H

Erase Block Region 4 Information

Query-unique ASCII string "PRI"

40H

41H

42H

0050H

0052H

0049H

Major version number, ASCII

Minor version number, ASCII

43H

44H

0031H

0030H

Address Sensitive Unlock(Bits 1-0)

0 = Required, 1= Not Required

Silcon Revision Number(Bits 7-2)

45H

0000H

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46H

47H

0002H

0001H

Block Protect

00 = Not Supported, 01 = Supported

Block Temporary Unprotect 00 = Not Supported, 01 = Supported

Block Protect/Unprotect scheme 00 = Not Supported, 01 = Supported

48H

49H

0000H

0001H

Simultaneous Operation

00 = Not Supported, 01 = Supported

4AH

4BH

4CH

0001H

0000H

Burst Mode Type 00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page

Max. Operating Clock Frequency (MHz )

4EH

4FH

0042H

0000H

RWW(Read While Write) Functionality Restriction (00H = non exists , 01H = exists)

Handshaking

00 = Not Supported at both mode, 01 = Supported at Sync. Mode

10 = Supported at Async. Mode, 11 = Supported at both Mode

50H

0001H

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MCP MEMORY

K5L5628JT(B)M

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

-0.5 to +2.5

-0.5 to +9.5

-0.5 to +2.5

-30 to +125

-65 to +150

5

Unit

Vcc

Voltage on any pin relative to VSS

V

VPP

VIN

All Other Pins

Temperature Under Bias

Storage Temperature

Tbias

Tstg

IOS

TA

°C

Short Circuit Output Current

Operating Temperature

mA

°C

-30 to + 85

Notes :

1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -1.5V for periods <20ns.

Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+1.5V for periods <20ns.

2. Minimum DC input voltage is -0.5V on VPP . During transitions, this level may fall to -1.5V for periods <20ns.

Maximum DC input voltage is +9.5V on V^PPwhich, during transitions, may overshoot to +11.0V for periods <20ns.

3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )

Parameter

Symbol

Min

1.7

0

Typ.

1.8

0

Max

1.95

0

Unit

V

Supply Voltage

VCC

Supply Voltage

VSS

V

DC CHARACTERISTICS

Parameter

Symbol

ILI

Test Conditions

Min

Typ

Max

+ 1.0

35

Unit

Input Leakage Current

VPP Leakage Current

Output Leakage Current

Active Burst Read Current

VIN=VSS to VCC, VCC=VCCmax

VCC=VCCmax , VPP=9.5V

- 1.0

-

µA

ILIP

-

ILO

VOUT=VSS to VCC, VCC=VCCmax, OE=VIH

CE=VIL, OE=VIH

- 1.0

-

+ 1.0

45

µA

ICCB1

-

30

3

mA

µA

10MHz

45

Active Asynchronous

Read Current

ICC1

CE=VIL, OE=VIH

1MHz

5

Active Write Current (Note 2)

Read While Write Current

Accelerated Program Current

Standby Current

ICC2

ICC3

ICC4

ICC5

ICC6

CE=VIL, OE=VIH, WE=VIL, VPP=VIH

CE=VIL, OE=VIH

15

40

15

25

30

70

CE=VIL, OE=VIH , VPP=9.5V

CE= RESET=VCC ± 0.2V

RESET = VSS ± 0.2V

30

70

Standby Current During Reset

70

µA

CE=VSS ± 0.2V, Other Pins=VIL or VIH

VIL = VSS ± 0.2V, VIH = VCC ± 0.2V

Automatic Sleep Mode(Note 3)

ICC7

-

25

70

µA

Input Low Voltage

VIL

VIH

-0.5

VCC-0.4

-

0.4

VCC+0.4

0.1

V

Input High Voltage

-

Output Low Voltage

VOL

VOH

VID

IOL = 100 µA , VCC=VCCmin

IOH = -100 µA , VCC=VCCmin

-

Output High Voltage

VCC-0.1

8.5

-

Voltage for Accelerated Program

Low VCC Lock-out Voltage

9.0

-

9.5

VLKO

1.0

1.3

Notes:

1. Maximum ICC specifications are tested with VCC = VCCmax.

2. ICC active while Internal Erase or Internal Program is in progress.

3. Device enters automatic sleep mode when addresses are stable for tAA + 60ns.

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K5L5628JT(B)M

CAPACITANCE(TA = 25 °C, VCC = 1.8V, f = 1.0MHz)

Item

Symbol

Test Condition

Min

Max

Unit

pF

Input Capacitance

CIN

VIN=0V

-

10

Output Capacitance

Control Pin Capacitance

COUT

CIN2

VOUT=0V

VIN=0V

pF

Note : Capacitance is periodically sampled and not 100% tested.

AC TEST CONDITION

Parameter

Value

0V to VCC

5ns

Input Pulse Levels

Input Rise and Fall Times

Input and Output Timing Levels

Output Load

VCC/2

CL = 30pF

Device

Under

Test

VCC

Input & Output

VCC/2

Test Point

* CL = 30pF including scope

and Jig capacitance

0V

Input Pulse and Test Point

Output Load

AC CHARACTERISTICS

Synchronous/Burst Read

7B

(54 MHz)

7C

(66 MHz)

Parameter

Symbol

Unit

Min

Max

Min

Max

Initial Access Time

tIAA

tBA

-

88.5

-

70

11

-

ns

Burst Access Time Valid Clock to Output Delay

AVD Setup Time to CLK

AVD Hold Time from CLK

AVD High to OE Low

14.5

tAVDS

tAVDH

tAVDO

tACS

tACH

tBDH

tOE

5

7

0

5

7

4

-

5

6

0

5

6

4

-

Address Setup Time to CLK

Address Hold Time from CLK

Data Hold Time from Next Clock Cycle

Output Enable to Data

-

20

14.5

20

15

-

20

11

20

15

-

Output Enable to RDY valid

CE Disable to High Z

tOER

tCEZ

-

OE Disable to High Z

tOEZ

tCES

tRDYA

tRDYS

tCH/L

tCHCL

-

CE Setup Time to CLK

7

-

6

-

CLK to RDY Setup Time

RDY Setup Time to CLK

CLK High or Low Time

14.5

-

11

-

4

4.5

-

4

3.5

-

CLK Fall or Rise Time

3

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MCP MEMORY

K5L5628JT(B)M

SWITCHING WAVEFORMS

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

15.2 ns typ.

tCES

tCEZ

CE

CLK

tAVDS

tAVDH

AVD

A0-A23

tBDH

tACS

tBA

tACH

Hi-Z

DQ0-DQ15

Da

Da+1 Da+2

tIAA

Da+3

Da+n

tOEZ

OE

tOER

tRDYS

Hi-Z

tRDYA

Hi-Z

RDY

Figure 3. Burst Mode Read (66 MHz)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

18.5 ns typ.

tCES

tCEZ

CE

CLK

tAVDS

AVD

A0-A23

tAVDH

tBDH

tACS

tBA

tACH

Hi-Z

DQ0-DQ15

Da

Da+1 Da+2

tIAA

Da+3

Da+n

tOEZ

OE

tOER

tRDYS

Hi-Z

tRDYA

Hi-Z

RDY

Figure 4. Burst Mode Read (54 MHz)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

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MCP MEMORY

K5L5628JT(B)M

SWITCHING WAVEFORMS

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

15.2 ns typ.

tCES

CE

CLK

tAVDS

tAVDH

AVD

A0-A23

tBDH

tACS

tBA

tACH

DQ0-DQ15

tIAA

D6

D7

D0

D2

D7

D1

D3

D0

OE

tOER

tRDYS

Hi-Z

tRDYA

RDY

Figure 5. 8 word Linear Burst Mode with Wrap Around (66 MHz)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

15.2 ns typ.(66MHz)

tCES

CE

CLK

tAVDS

AVD

A0-A23

tAVDH

tBDH

tACS

tBA

tACH

DQ0-DQ15

tIAA

D6

D7

D0

D2

D7

D1

D3

D0

OE

tOER

tRDYS

Hi-Z

tRDYA

RDY

Figure 6. 8 word Linear Burst with RDY Set One Cycle Before Data (CR setting : A18=1)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

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MCP MEMORY

K5L5628JT(B)M

SWITCHING WAVEFORMS

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

15.2 ns typ(66MHz).

tCES

tCEZ

CE

CLK

tAVDS

tAVDH

AVD

A0-A23

tBDH

tACS

tBA

tACH

Hi-Z

DQ0-DQ15

D6

D7

D8

tIAA

D9

D13

tOEZ

OE

tOER

tRDYS

Hi-Z

tRDYA

Hi-Z

RDY

Figure 7. 8 word Linear Burst Mode (No Wrap Case)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

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MCP MEMORY

K5L5628JT(B)M

AC CHARACTERISTICS

Asynchronous Read

7B

7C

Parameter

Symbol

Unit

Min

Max

90

-

Min

Max

80

-

Access Time from CE Low

tCE

tAA

-

ns

Asynchronous Access Time

AVD Low Setup Time to CE Enable

AVD Low Hold Time from CE Disable

Output Enable to Output Valid

tAVDCS

tAVDCH

tOE

0

-

0

-

20

-

20

-

Read

0

Output Enable Hold

Time

t^OEH

tOEZ

Toggle and

Data Polling

10

-

10

-

ns

Output Disable to High Z(Note 1)

15

Note: 1. Not 100% tested.

SWITCHING WAVEFORMS

Asynchronous Mode Read

VIL

CLK

CE

AVD

OE

tAVDCH

tAVDCS

tOE

tOEH

WE

tCE

tOEZ

DQ0-DQ15

Valid RD

tAA

A0-A22

VA

Figure 8. Asynchronous Mode Read

Note: VA=Valid Read Address, RD=Read Data.

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MCP MEMORY

K5L5628JT(B)M

AC CHARACTERISTICS

Hardware Reset(RESET)

Parameter

All Speed Options

Symbol

Unit

Max

Min

RESET Pin Low(During Internal Routines)

to Read Mode (Note)

t^Ready

µs

-

20

RESET Pin Low(NOT During Internal Routines)

to Read Mode (Note)

ns

-

500

RESET Pulse Width

tRP

t^RH

200

20

-

ns

µs

Reset High Time Before Read (Note)

RESET Low to Standby Mode

tRPD

Note: Not 100% tested.

SWITCHING WAVEFORMS

CE, OE

RESET

tRH

tRP

tReady

Reset Timings NOT during Internal Routines

CE, OE

RESET

tReady

tRP

Reset Timings during Internal Routines

Figure 9. Reset Timings

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MCP MEMORY

K5L5628JT(B)M

AC CHARACTERISTICS

Erase/Program Operation

7B, 7C

Parameter

Symbol

Unit

Min

100

0

Typ

Max

WE Cycle Time(Note 1)

tWC

tAS

-

ns

µs

Address Setup Time(Note 2)

Address Hold Time(Note 2)

Data Setup Time

-

tAH

50

0

-

tDS

-

Data Hold Time

tDH

-

Read Recovery Time Before Write

CE Setup Time

tGHWL

t^CS

-

0

5

-

CE Hold Time

tCH

5

-

WE Pulse Width

tWP

70

30

0

-

WE Pulse Width High

tWPH

tSR/W

tPGM

-

Latency Between Read and Write Operations

Word Programming Operation

Accelerated Single word Programming Operation

Accelerated Quad word Programming Operation

Block Erase Operation (Note 3)

VPP Rise and Fall Time

-

11.5

6.5

0.7

-

t^ACCPGM

t^ACCPGM_QUAD

t^BERS

tVPP

-

µs

-

sec

ns

µs

500

1

VPP Setup Time (During Accelerated Programming)

V^CCSetup Time

tVPS

-

tVCS

µs

50

-

Notes:

1. Not 100% tested.

2. In write timing, addresses are latched on the falling edge of WE.

3. Include the preprogramming time.

FLASH Erase/Program Performance

Limits

Parameter

Unit

Comments

Min.

Typ.

0.7

Max.

32 Kword

4 Kword

-

14

Block Erase Time

Chip Erase Time

Includes 00h programming prior

to erasure

0.2

4

sec

360

11.5

6.5

-

210

120

30

-

Word Programming Time

Accelerated Sinlge Programming Time (@word)

Accelerated Quad Programming Time (@word)

Chip Programming Time

µs

1.6

Excludes system level overhead

193

109

27

Accelerated Single word Chip Programming Time

Accelerated Quad word Chip Programming Time

-

sec

-

Minimum 100,000 cycles guaran-

teed in all Bank

Erase/Program Endurance (Note 3)

100,000

-

Cycles

Notes:

1. 25°C, VCC = 1.8V, 100,000 cycles, typical pattern.

2. System-level overhead is defined as the time required to execute the two or four bus cycle command necessary to program each

word. In the preprogramming step of the Internal Erase Routine, all words are programmed to 00H before erasure.

3. 100K Program/Erase Cycle in all Bank

53

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K5L5628JT(B)M

SWITCHING WAVEFORMS

Program Operations

Program Command Sequence (last two cycles)

Read Status Data

tAS

tAH

A0:A23

555h

PA

VA

In

DQ0-DQ15

Complete

Progress

A0h

PD

tDS

tDH

CE

OE

WE

tCH

tWP

tWPH

tPGM

tCS

tWC

VIL

tVCS

CLK

VCC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A16–A23 are don’t care during command sequence unlock cycles.

4. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

5. AVD Setup/Hold Time to CE Enable are same to Asynchronous Mode Read

Figure 10. Program Operation Timing

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MCP MEMORY

K5L5628JT(B)M

Start

555h/AAh

2AAh/55h

555h/A0h

Program Address/Program Data

DATA Polling or Toggle Bit

Algorithm(See Below)

NO

Last Address?

Address = Address + 1

YES

Program Completed

Program Command Sequence (address/data)

Start

Read(DQ0~DQ7)

Valid Address

Start

Read(DQ0~DQ7)

Valid Address

Read(DQ0~DQ7)

Valid Address

DQ6 = Toggle ?

DQ7 = Data ?

No

Yes

No

DQ5 = 1 ?

Yes

DQ5 = 1 ?

Yes

Read twice(DQ0~DQ7)

Valid Address

Read(DQ0~DQ7)

Valid Address

No

Yes

DQ6 = Toggle ?

DQ7 = Data ?

Yes

Fail

No

Fail

Pass

Figure 2. Toggle Bit Algorithms

Figure 1. Data Polling Algorithms

Figure 11. Program Operation Flow Chart

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MCP MEMORY

K5L5628JT(B)M

SWITCHING WAVEFORMS

Erase Operation

Erase Command Sequence (last two cycles)

Read Status Data

555h for

chip erase

tAS

tAH

A0:A23

DQ0-DQ15

CE

2AAh

BA

VA

10h for

chip erase

In

Complete

Progress

55h

30h

tDS

tDH

tCH

OE

tWP

WE

tWPH

tBERS

tCS

tWC

VIL

CLK

VCC

tVCS

Notes:

1. BA is the block address for Block Erase.

2. Address bits A16–A23 are don’t cares during unlock cycles in the command sequence.

3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

4. AVD Setup/Hold Time to CE Enable are same to Asynchronous Mode Read

Figure 11. Chlp/Block Erase Operations

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MCP MEMORY

K5L5628JT(B)M

Start

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h(Chip Erase)

BA/30h(Block Erase)

DATA Polling or Toggle Bit

Algorithm(See Below)

Erase Completed

Figure 13. Erase Operation Flow Chart

Start

Read(DQ0~DQ7)

Valid Address

Start

Read(DQ0~DQ7)

Valid Address

Read(DQ0~DQ7)

Valid Address

DQ6 = Toggle ?

DQ7 = Data ?

No

Yes

No

DQ5 = 1 ?

Yes

Read twice(DQ0~DQ7)

Valid Address

Read(DQ0~DQ7)

Valid Address

No

Yes

DQ6 = Toggle ?

DQ7 = Data ?

Yes

No

Fail

Pass

Figure 2. Toggle Bit Algorithms

Figure 1. Data Polling Algorithms

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K5L5628JT(B)M

SWITCHING WAVEFORMS

Unlock Bypass Program Operations(Accelerated Program)

CE

WE

PA

A0:A23

DQ0-DQ15

Don’t Care

A0h

Don’t Care

PD

Don’t Care

OE

1us

tVPS

VID

tVPP

VPP

VIL or VIH

Unlock Bypass Block Erase Operations

CE

WE

BA

A0:A23

555h for

chip erase

10h for

chip erase

DQ0-DQ15

OE

Don’t Care

80h

Don’t Care

30h

Don’t Care

1us

tVPS

VID

tVPP

VPP

VIL or VIH

Notes:

1. VPP can be left high for subsequent programming pulses.

2. Use setup and hold times from conventional program operations.

3. Unlock Bypass Program/Erase commands can be used when the VID is applied to Vpp.

4. AVD Setup/Hold Time to CE Enable are same to Asynchronous Mode Read

Figure 12. Unlock Bypass Operation Timings

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MCP MEMORY

K5L5628JT(B)M

Start

Unlock Bypass Program Command

Sequence (see below)

DATA Polling or Toggle Bit

Algorithm(See Below)

NO

Last Address?

Address = Address + 1

YES

Program Completed

Unlock Bypass Reset

Command Sequence

Unlock Bypass Program

Command Sequence

(address/data)

555h/AAh

XXXh/90h

XXXh/00h

2AAh/55h

555h/20h

XXXh/A0h

Figure 15. Unlock Bypass Operation Flow Chart

Program Address/Program Data

Start

Read(DQ0~DQ7)

Valid Address

Start

Read(DQ0~DQ7)

Valid Address

Read(DQ0~DQ7)

Valid Address

DQ6 = Toggle ?

No

DQ7 = Data ?

No

Yes

No

DQ5 = 1 ?

Yes

Read twice(DQ0~DQ7)

Valid Address

Read(DQ0~DQ7)

Valid Address

No

Yes

DQ6 = Toggle ?

DQ7 = Data ?

Yes

No

Fail

Pass

Figure 2. Toggle Bit Algorithms

Figure 1. Data Polling Algorithms

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K5L5628JT(B)M

SWITCHING WAVEFORMS

Data Polling Operations

tCES

CE

CLK

tAVDS

AVD

tAVDH

tACS

A0-A23

VA

tACH

Status Data

DQ0-DQ15

tIAA

OE

tRDYS

Hi-Z

RDY

Notes:

1. VA = Valid Address. When the Internal Routine operation is complete, and Data Polling will output true data.

Figure 13. Data Polling Timings (During Internal Routine)

Toggle Bit Operations

tCES

CE

CLK

tAVDS

AVD

tAVDH

tACS

A0-A23

VA

tACH

DQ0-DQ15

Status Data

tIAA

OE

tRDYS

Hi-Z

RDY

Notes:

1. VA = Valid Address. When the Internal Routine operation is complete, the toggle bits will stop toggling.

Figure 14. Toggle Bit Timings(During Internal Routine)

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MCP MEMORY

K5L5628JT(B)M

SWITCHING WAVEFORMS

Read While Write Operations

Last Cycle in

Program or

Block Erase

Begin another

Program or Erase

Command Sequences

Read status in same bank

and/or array data from other bank

Command Sequence

tWC

tRC

tWC

CE

OE

tOE

tOEH

tGHWL

WE

tWPH

tWP

tDS

tAA

tDH

tOEH

RD

DQ0-DQ15

A0-A23

PD/30h

RD

AAh

tSR/W

PA/BA

RA

555h

Figure 15. Read While Write Operation

Note:

Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” and checking the status of the program or

erase operation in the “busy” bank.

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K5L5628JT(B)M

Crossing of First Word Boundary in Burst Read Mode

The additional clock insertion for word boundary is needed only at the first crossing of word boundary. This means that no addtional

clock cycle is needed from 2nd word boundary crossing to the end of continuous burst read. Also, the number of addtional clock cycle

for the first word boundary can varies from zero to three cycles, and the exact number of additional clock cycle depends on the start-

ing address of burst read.

The rule to determine the additional clock cycle is as follows. All addresses can be divided into 4 groups. The applied rule is "The res-

idue obtained when the address is divided by 4" or "two LSB bits of address". Using this rule, all address can be divided by 4 different

groups as shown in below table. For simplicity of terminology, "4N" stands for the address of which the residue is "0"(or the two LSB

bits are "00") and "4N+1" for the address of which the residue is "1"(or the two LSB bits are "01"), etc.

The additional clock cycles for first word boundary crossing are zero, one, two or three when the burst read start from "4N" address,

"4N+1" address, "4N+2" address or "4N+3" address respectively.

Starting Address vs. Additional Clock Cycles for first word boundary

Srarting Address Group

for Burst Read

Additional Clock Cycles for

First Word Boundary Crossing

The Residue of (Address/4)

LSB Bits of Address

4N

0

1

2

3

00

01

10

11

0 cycle

1 cycle

2 cycles

3 cycles

4N+1

4N+2

4N+3

Case 1 : Start from "4N" address group

5 cycle for initial access shown.(54MHz case)

A0-A23

C

D

E

10

11

12

13

Data Bus

F

CLK

AVD

C

D

11

12

13

14

E

F

10

No Additional Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Notes:

1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.

2. Address 000000H is also a boundry crossing.

3. No additional clock cycles are needed except for 1st boundary crossing.

Figure 16. Crossing of first word boundary in burst read mode.

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Case2 : Start from "4N+1" address group

5 cycle for initial access shown.(54MHz case)

A0-A23

Data Bus

D

E

F

10

11

12

13

CLK

AVD

D

E

11

12

13

14

F

10

Additional 1 Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Case 3 : Start from "4N+2" address group

5 cycle for initial access shown.(54MHz case)

A0-A23

Data Bus

E

F

10

11

12

13

CLK

AVD

E

F

11

12

13

14

10

Additional 2 Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Notes:

1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.

2. Address 000000H is also a boundry crossing.

3. No additional clock cycles are needed except for 1st boundary crossing.

Figure 16. Crossing of first word boundary in burst read mode.

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MCP MEMORY

K5L5628JT(B)M

Case4 : Start from "4N+3" address group

5 cycle for initial access shown.(54MHz case)

A0-A23

Data Bus

F

10

1

12

13

CLK

AVD

F

10

11

12

13

14

Additional 3 Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Notes:

1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.

2. Address 000000H is also a boundry crossing.

3. No additional clock cycles are needed except for 1st boundary crossing.

Figure 16. Crossing of first word boundary in burst read mode.

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MCP MEMORY

K5L5628JT(B)M

128M Bit(8M x16)

Synchronous Burst UtRAM M-die

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MCP MEMORY

K5L5628JT(B)M

POWER UP SEQUENCE

After applying VCC upto minimum operating voltage(2.5V), drive CS High first and then drive MRS High. Then the device gets into the

Power Up mode. Wait for minimum 200µs to get into the normal operation mode. During the Power Up mode, the standby current can

not be guaranteed. To get the stable standby current level, at least one cycle of active operation should be implemented regardless of

wait time duration. To get the appropriate device operation, be sure to keep the following power up sequence.

1. Apply power.

2. Maintain stable power(Vcc min.=2.5V) for a minimum 200µs with CS and MRS high.

Fig.3 POWER UP TIMING

200µs

VCC(Min)

VCC

VCCQ(Min)

VCCQ

Min. 0ns

MRS

Min. 200µs

Min. 0ns

CS

Power Up Mode

NormalOperation

Fig.4 STANDBY MODE STATE MACHINES

CS=UB=LB=VIL,

WE=VIL, MRS=VIL

CS=VIH

MRS=VIH

CS=VIL, UB or LB=VIL

MRS=VIH

CS=VIH

MRS=VIH

MRS=VIL

Initial State

(Wait 200µs)

Standby

Mode

PAR

Mode

MRS Setting

Power On

Active

MRS Setting

CS=VIL,

WE=VIL, MRS=VIL

Default mode after power up is Asynchronous mode(4 Page Read and Asynchronous Write). But this default mode is not 100%

guaranteed so MRS setting sequence is highly recommended after power up.

For entry to PAR mode, drive MRS pin into VIL for over 0.5µs(suspend period) during standby mode after MRS setting has

been completed(A4=1, A3=0). If MRS pin is driven into VIH during PAR mode, the device gets back to the standby mode

without wake up sequence.

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K5L5628JT(B)M

FUNCTIONAL DESCRIPTION

Table 3. ASYNCHRONOUS 4 PAGE READ & ASYNCHRONOUS WRITE MODE(A15/A14=0/0)

CS

H

L

MRS

H

OE

X¹⁾

H

WE

X¹⁾

H

LB

X¹⁾

H

UB

X¹⁾

H

DQ0~7

High-Z

Dout

DQ8~15

High-Z

Dout

Mode

Power

Standby

PAR

Deselected

L

Deselected

H

Output Disabled

Lower Byte Read

Upper Byte Read

Word Read

Active

X¹⁾

L

X¹⁾

H

L

H

L

H

L

H

L

H

L

H

L

High-Z

Dout

L

H

L

H

L

Dout

L

H

L

H

Din

High-Z

Din

Lower Byte Write

Upper Byte Write

Word Write

L

H

L

H

L

High-Z

Din

L

H

L

Din

L

H

L

High-Z

Mode Register Set

1. X must be low or high state.

2. In asynchronous mode, Clock and ADV are ignored.

3. /WAIT pin is High-Z in Asynchronous mode.

Table 5. SYNCHRONOUS BURST READ & SYNCHRONOUS BURST WRITE MODE(A15/A14=1/0)

CS

H

L

MRS

H

OE

X¹⁾

H

WE

X¹⁾

H

LB

X¹⁾

H

UB

X¹⁾

H

DQ0~7

High-Z

Dout

DQ8~15

High-Z

Dout

CLK

X²⁾

ADV

X²⁾

H

Mode

Power

Standby

PAR

Deselected

X²⁾

L

Deselected

X²⁾

H

Output Disabled

Read Command

Lower Byte Read

Upper Byte Read

Word Read

Active

X¹⁾

L

X¹⁾

H

X²⁾

L

H

X¹⁾

L

X¹⁾

H

L

H

L

H

L

H

L

H

L

High-Z

Dout

L

H

L

H

L

Dout

X¹⁾

H

X¹⁾

L

X¹⁾

H

L

H

L or

X¹⁾

L or

High-Z

Din

High-Z

Din

Write Command

Lower Byte Write

Upper Byte Write

Word Write

L

H

L

H

L

High-Z

Din

L

H

L

Din

L

H

L

High-Z

Mode Register Set

1. X must be low or high state.

2. X means "Don’t care"(can be low, high or toggling).

3. /WAIT is device output signal so does not have any affect to the mode definition. Please refer to each timing diagram for /WAIT pin function.

4. The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then implement at least one dummy

write cycle before change mode into synchronous burst read and synchronous burst write mode.

5. The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the transition from Synchronous

burst write operation to Asynchronous write operation is prohibited.

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MCP MEMORY

K5L5628JT(B)M

MODE REGISTER SETTING OPERATION

The device has several modes : Asynchronous Page Read mode, Asynchronous Write mode, Synchronous Burst Read mode, Syn-

chronous Burst Write mode, Standby mode and Partial Array Refresh(PAR) mode.

Partial Array Refresh(PAR) mode is defined through Mode Register Set(MRS) option. Mode Register Set(MRS) option also defines

Burst Length, Burst Type, Wait Polarity and Latency Count at Synchronous Burst Read/Write mode.

Mode Register Set (MRS)

The mode register stores the data for controlling the various operation modes of UtRAM. It programs Partial Array Refresh(PAR),

Burst Length, Burst Type, Latency Count and various vendor specific options to make UtRAM useful for a variety of different applica-

tions. The default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes.

The mode register is written by driving CS, ADV, WE, UB, LB and MRS to VIL and driving OE to VIH during valid address. The mode

register is divided into various fields depending on the fields of functions. The Partial Array Refresh(PAR) field uses A0~A4, Burst

Length field uses A5~A7, Burst Type uses A8, Latency Count uses A9~A11, Wait Polarity uses A13, Operation Mode uses A14~A15

and Driver Strength uses A16~A17.

Refer to the Table below for detailed Mode Register Setting. A18~A22 addresses are "Don’t care" in Mode Register Setting.

Table 6. Mode Register Setting according to field of function

Address

Function

A17~A16

A15~A14

A13

A12

A11~A9

A8

A7~A5

A4~A3

A2

A1~A0

DS

MS

WP

RFU

Latency

BT

BL

PAR

PARA

PARS

NOTE : DS(Driver Strength), MS(Mode Select), WP(Wait Polarity), Latency(Latency Count), BT(Burst Type),

BL(Burst Length), PAR(Partial Array Refresh), PARA(Partial Array Refresh Array),

PARS(Partial Array Refresh Size), RFU(Reserved for Future Use)

Table 7. Mode Register Set

Driver Strength

Mode Select

MS

A17

0

A16

0

DS

A15

0

A14

0

Full Drive

1/2 Drive

1/4 Drive

Async. 4 Page Read / Async. Write

Not Support

0

1

0

1

0

1

0

Sync. Burst Read / Sync. Burst Write**

WAIT Polarity

WP

RFU

Latency Count

Burst Type

Burst Length

A13

0

A12

RFU

Must

-

A11

0

A10

0

A9

0

Latency

A8

0

BT

A7

0

A6

1

A5

0

BL

Low Enable

0

1

3*

4

Linear

4 word

8 word

1

High Enable

0

1

Interleave

0

1

0

1

0

5

1

0

1

16 word

0

1

6

1

Full(256 word)

Partial Array Refresh

PAR Array

PARA

PAR Size

A4

1

A3

0

PAR

A2

0

A1

A0

0

PARS

PAR Enable

Bottom Array

0

1

Full Array

3/4 Array

1/2 Array

1/4 Array

1

PAR Disable

1

Top Array

1

0

1

NOTE : The address bits other than those listed in the table above are reserved for future use.

Each field has its own default mode and these default modes are written in blue-bold in the table above.

But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up.

A12 is a reserved bit for future use. A12 must be set as "0".

Not all the mode settings are tested. Per the mode settings to be tested, please contact Samsung Product Planning team.

256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns.

* Latency 3 is supported in 52.9MHz with tCD 12ns.

** The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then imple-

ment at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode.

** The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the

transition from Synchronous burst write operation to Asynchronous write operation is prohibited.

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MCP MEMORY

K5L5628JT(B)M

MRS pin Control Type Mode Register Setting Timing

In this device, MRS pin is used for two purposes. One is to get into the mode register setting and the other one is to execute Partial

Array Refresh mode.

To get into the Mode Register Setting, the system must drive MRS pin to VIL and immediately(within 0.5µs) issue a write com-

mand(drive CS, ADV, UB, LB and WE to VIL and drive OE to VIH during valid address). If the subsequent write command(WE signal

input) is not issued within 0.5µs, then the device might get into the PAR mode.

Fig.5 MODE REGISTER SETTING TIMING(OE=VIH)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

CLK

ADV

tWC

Address

tCW

tAW

CS

tBW

UB, LB

tWP

WE

tAS

tWU

tMW

MRS

Register Update Complete

Register Write Complete

Register Write Start

(MRS SETTING TIMING)

1. Clock input is ignored.

Table 8. MRS AC CHARACTERISTICS(VCC=2.5~2.7V, VCCQ=1.7~2.0V TA=-30 to 85°C, Maximum Main Clock Frequency

= 52.9MHz)

Speed

Parameter List

Symbol

Units

Min

0

Max

500

-

MRS Enable to Register Write Start

End of Write to MRS Disable

tMW

tWU

ns

MRS

0

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MCP MEMORY

K5L5628JT(B)M

ASYNCHRONOUS OPERATION

SYNCHRONOUS BURST OPERATION

Burst mode operations enable the system to get high perfor-

mance read and write operation. The address to be accessed is

latched on the rising edge of clock or ADV(whichever occurs

first). CS should be setup before the address latch. During this

first clock rising edge, WE indicates whether the operation is

going to be a Read(WE High) or a Write(WE Low).

Asynchronous 4 Page Read Operation

Asynchronous normal read operation starts when CS, OE and

UB or LB are driven to VIL under the valid address without tog-

gling page addresses(A0, A1). If the page addresses(A0, A1)

are toggled under the other valid address, the first data will be

out with the normal read cycle time(tRC) and the second, the

third and the fourth data will be out with the page cycle

time(tPC). (MRS and WE should be driven to VIH during the

asynchronous (page) read operation)

For the optimized Burst Mode to each system, the system

should determine how many clock cycles are required for the

first data of each burst access(Latency Count), how many

words the device outputs at an access(Burst Length) and which

type of burst operation(Burst Type : Linear or Interleave) is

needed. The Wait Polarity should also be determined.(See

Table "Mode Register Set")

Clock, ADV, WAIT signals are ignored during the asynchronous

(page) read operation.

Asynchronous Write Operation

Synchronous Burst Read Operation

Asynchronous write operation starts when CS, WE and UB or

LB are driven to VIL under the valid address.(MRS and OE

should be driven to VIH during the asynchronous write opera-

tion.) Clock, ADV, WAIT signals are ignored during the asyn-

chronous (page) read operation.

The Synchronous Burst Read command is implemented when

the clock rising is detected during the ADV low pulse. ADV and

CS should be set up before the clock rising. During Read com-

mand, WE should be held in VIH. The multiple clock risings(dur-

ing low ADV period) are allowed but the burst operation starts

from the first clock rising. The first data will be out with Latency

count and tCD.

Synchronous Burst Write Operation

The Synchronous Burst Write command is implemented when

the clock rising is detected during the ADV and WE low pulse.

ADV, WE and CS should be set up before the clock rising. The

multiple clock risings(during low ADV period) are allowed but

the burst operation starts from the first clock rising. The first

data will be written in the Latency clock with tDS.

Fig.6 ASYNCHRONOUS 4-PAGE READ

Fig.8 SYNCHRONOUS BURST READ(Latency 5, BL 4, WP : Low Enable)

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14

CLK

A22~A2

A1~A0

CS

ADV

Addr.

CS

UB, LB

OE

UB, LB

OE

Data out

WAIT

Fig.9 SYNCHRONOUS BURST WRITE(Latency 5, BL 4, WP : Low Enable)

Fig.7 ASYNCHRONOUS WRITE

0

1

2

3

4

5

6

7

8

9

10 11 12 13

CLK

Address

ADV

Addr.

CS

UB, LB

WE

UB, LB

WE

High-Z

Data in

High-Z

Data out

WAIT

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MCP MEMORY

K5L5628JT(B)M

SYNCHRONOUS BURST OPERATION TERMINOLOGY

Clock(CLK)

The clock input is used as the reference for synchronous burst read and write operation of UtRAM. The synchronous burst read and

write operation is synchronized to the rising edge of the clock. The clock transitions must swing between VIL and VIH.

Latency Count

The Latency Count configuration tells the device how many clocks must elapse from the burst command before the first data should

be available on its data pins. This value depends on the input clock frequency.

The supported Latency Count is as follows.

Table 9. Latency Count support : 3, 4, 5

Clock Frequency

Latency Count

Upto 66MHz

5

Upto 54MHz

4

Upto 52.9MHz

3

Table 10. Number of Clocks for 1st Data

Set Latency

Latency 3

Latency 4

Latency 5

# of Clocks for 1st data(Read)

# of Clocks for 1st data(Write)

4

2

5

3

6

4

Fig.10 Latency Configuration(Read)

T

Clock

ADV

Address

Latency 3

Data out

DQ1

DQ2

DQ1

DQ3

DQ2

DQ1

DQ4

DQ3

DQ2

DQ1

DQ5

DQ4

DQ3

DQ2

DQ6

DQ5

DQ4

DQ3

DQ7

DQ6

DQ5

DQ4

DQ8

DQ7

DQ6

DQ5

DQ9

Latency 4

DQ8

DQ7

DQ6

Data out

Latency 5

Data out

Latency 6

Data out

NOTE : The first data will always keep the Latency. From the second data, some period of wait time might be caused by WAIT pin.

Burst Length

Burst Length identifies how many data the device outputs at an access. The device supports 4 word, 8 word, 16 word and 256 word

burst read or write. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns.

The first data will be out with the set Latency + tCD. From the second data, the data will be out with tCD from each clock.

Burst Stop

Burst stop is used when the system wants to stop burst operation on special purpose. If driving CS to VIH during the burst read opera-

tion, then the burst operation will be stopped. During the burst read operation, the new burst operation can not be issued. The new

burst operation can be issued only after the previous burst operation is finished.

The burst stop feature is very useful because it enables the user to utilize the un-supported burst length such as 1 burst or 2 burst

which accounts for big portion in usage for the mobile handset application environment.

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MCP MEMORY

K5L5628JT(B)M

SYNCHRONOUS BURST OPERATION TERMINOLOGY

WAIT Control(WAIT)

The WAIT signal is the device’s output signal which indicates to the host system when the device’s data-out or data-in is valid.

To be compatible with the Flash interfaces of various microprocessor types, the WAIT polarity(WP) can be configured. The polarity

can be programmed to be either low enable or high enable.

For the timing of WAIT signal, the WAIT signal should be set active one clock prior to the data regardless of Read or Write cycle.

Fig.11 WAIT Control and Read/Write Latency Control(LATENCY : 5, Burst Length : 4, WP : Low Enable)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

CLK

ADV

CS

Latency 5

Read

Data out

DQ0

D2

DQ1

D3

DQ2

DQ3

High-Z

WAIT

Latency 5

Write

Data in

D0

D1

WAIT

Burst Type

The device supports Linear type burst sequence and Interleave type burst sequence. Linear type burst sequentially increments the

burst address from the starting address. The detailed Linear and Interleave type burst address sequence is shown in burst sequence

table in next page.

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MCP MEMORY

K5L5628JT(B)M

Table 11. Burst Sequence

Burst Address Sequence(Decimal)

Wrap¹⁾

Start

Addr.

4 word Burst

8 word Burst

Linear

16 word Burst

Linear Interleave

Full Page(256 word)

Linear

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

Interleave

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

Interleave

0-1-2-...-6-7

1-0-3-...-7-6

2-3-0-...-4-5

3-2-1-...-5-4

4-5-6-...-2-3

5-4-7-...-3-2

6-7-4-...-0-1

7-6-5-...-1-0

0

1

0-1-...-5-6-7

1-2-...-6-7-0

2-3-...-7-0-1

3-4-...-0-1-2

4-5-...-1-2-3

5-6-...-2-3-4

6-7-...-3-4-5

7-0-...-4-5-6

0-1-2-...-14-15

1-2-3-...-15-0

2-3-4-...-0-1

3-4-5-...-1-2

4-5-6-...-2-3

5-6-7-...-3-4

6-7-8-...-4-5

7-8-9-...-5-6

~

0-1-2-3-4...14-15

1-0-3-2-5...15-14

2-3-0-1-6...12-13

3-2-1-0-7...13-12

4-5-6-7-0...10-11

5-4-7-6-1...11-10

6-7-4-5-2...8-9

7-6-5-4-3...9-8

~

0-1-2-...-254-255

1-2-3-...-255-0

2

2-3-4-...-255-0-1

3-4-5-...-255-0-1-2

4-5-6-...-255-0-1-2-3

5-6-7-...-255-...-3-4

6-7-8-...-255-...-4-5

7-8-9-...-255-...-5-6

~

3

4

5

6

7

~

14

15

~

14-15-0-...-12-13

15-0-1-...-13-14

14-15-12-...-0-1

15-14-13-...-1-0

14-15-...-255-...-12-13

15-16-...-255-...-13-14

~

255

255-0-1-...-253-254

1. Wrap : Burst Address wraps within word boundary and ends after fulfilled the burst length.

2. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns.

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MCP MEMORY

K5L5628JT(B)M

LOW POWER FEATURES

Driver Strength Optimization

Internal TCSR

The optimization of output driver strength is possible through

the mode register setting to adjust for the different data load-

ings. Through this driver strength optimization, the device can

minimize the noise generated on the data bus during read oper-

ation. The device supports full drive, 1/2 drive and 1/4 drive.

The internal Temperature Compensated Self Refresh(TCSR)

feature is a very useful tool for reducing standby current in room

temperature(below 40°C). DRAM cell has weak refresh charac-

teristics in higher temperature. So high temperature requires

more refresh cycles, which lead to standby current increase.

Without internal TCSR, the refresh cycle should be set as worst

condition so as to cover high temperature(85°C) refresh char-

acteristics. But with internal TCSR, the refresh cycle below

40°C can be optimized, so the standby current in room temper-

ature can be highly reduced. This feature is really beneficial to

mobile phone because most of mobile phones are used at

below 40°C in the phone standby mode.

Partial Array Refresh(PAR) mode

The PAR mode enables the user to specify the active memory

array size. UtRAM consists of 4 blocks and user can select

1 block, 2 blocks, 3 blocks or all blocks as active memory array

through Mode Register Setting. The active memory array is

periodically refreshed whereas the disabled array is not going

to be refreshed and so the previously stored data will get lost.

Even though PAR mode is enabled through the Mode Register

Setting, PAR mode execution by MRS pin is still needed.

The normal operation can be executed even in refresh-disabled

array as long as MRS pin is not driven to low for over 0.5µs.

Driving MRS pin to high makes the device to get back to the

normal operation mode from PAR executed mode,

Fig.13 PAR MODE EXECUTION and EXIT

0.5µs

MRS

Normal

Operation

Normal

Operation

Suspend

PAR mode

MODE

CS

Refer to Fig.13 and Table 12 for PAR operation and PAR

address mapping.

Table 12. PAR MODE CHARACTERISTIC

Standby³⁾

(ISB1, <40°C) (ISB1, <85°C)

Standby³⁾

Address

Power Mode

Address

(Top Array)²⁾

Memory

Cell Data

Wait

Time(µs)

(Bottom Array)²⁾

Valid¹⁾

Standby(Full Array)

000000h ~ 7FFFFFh

000000h ~ 5FFFFFh

000000h ~ 3FFFFFh

000000h ~ 1FFFFFh

000000h ~ 7FFFFFh

200000h ~ 7FFFFFh

400000h ~ 7FFFFFh

600000h ~ 7FFFFFh

130µA

125µA

120µA

115µA

250µA

235µA

220µA

205µA

0

Partial Refresh(3/4 Block)

Partial Refresh(1/2 Block)

Partial Refresh(1/4 Block)

1. Only the data in the refreshed block are valid

2. PAR Array can be selected through Mode Register Set(See Page 66)

3. Standby mode is supposed to be set up after at least one active operation.after power up.

ISB1 is measured after 60ms from the time when standby mode is set up.

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Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 14. ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Voltage on any pin relative to Vss

Power supply voltage relative to Vss

Output power supply voltage relative to Vss

Power Dissipation

Symbol

VIN, VOUT

VCC

Ratings

Unit

-0.2 to VCC+0.3V

-0.2 to 3.0V

-0.2 to 2.5V

1.0

V

VCCQ

PD

V

W

°C

Storage temperature

TSTG

-65 to 150

-30 to 85

Operating Temperature

TA

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-

ability.

Table 15. RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

VCC

Min

2.5

Typ

2.6

1.85

0

Max

Unit

V

Power supply voltage

I/O power supply voltage

Ground

2.7

VCCQ

Vss

1.7

2.0

V

0

V

VCCQ+0.2²⁾

0.4

Input high voltage

Input low voltage

VIH

0.8 x VCCQ

-0.2³⁾

-

V

VIL

-

V

1. TA=-30 to 85°C, otherwise specified.

2. Overshoot: V^CC+1.0V in case of pulse width ≤20ns.

3. Undershoot: -1.0V in case of pulse width ≤20ns.

4. Overshoot and undershoot are sampled, not 100% tested.

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Preliminary

MCP MEMORY

K5L5628JT(B)M

Table 16. CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

VIN=0V

Min

Max

8

Unit

pF

-

Input/Output capacitance

CIO

VIO=0V

10

pF

1. Capacitance is sampled, not 100% tested.

Table 17. DC AND OPERATING CHARACTERISTICS

Symbol

ILI

Item

Test Conditions

Min

-1

Typ

Max Unit

Input Leakage Current

Output Leakage Current

VIN=Vss to VCCQ

-

1

µA

ILO

CS=VIH, MRS=VIH, OE=VIH or WE=VIL, VIO=Vss to VCCQ

-1

Average Operating

Current(Async)

Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS=VIL, MRS=VIH,

VIN=VIL or VIH

ICC2

ICC3

-

40

mA

Average Operating

Current(Sync)

Burst Length 4, Latency 3, 52.9MHz, IIO=0mA, Address transi-

tion 1 time, CS=VIL, MRS=VIH, VIN=VIL or VIH

mA

Output Low Voltage

Output High Voltage

VOL

VOH

IOL=0.1mA

IOH=-0.1mA

-

0.2

-

V

1.4

CS≥VCCQ-0.2V, MRS≥VCCQ-0.2V, Other

inputs=Vss to VCCQ

< 40°C

< 85°C

-

130

250

125

120

115

235

220

205

µA

2)

Standby Current(CMOS)

Partial Refresh Current

ISB1

3/4 Block

< 40°C

µA

1/2 Block

1/4 Block

3/4 Block

1/2 Block

1/4 Block

MRS≤0.2V, CS≥VCCQ-0.2V

Other inputs=Vss to VCCQ

1)

ISBP

< 85°C

µA

1. Full Array Partial Refresh Current(ISBP) is same as Standby Current(ISB1).

2. Standby mode is supposed to be set up after at least one active operation.after power up.

ISB1 is measured after 60ms from the time when standby mode is set up.

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Preliminary

MCP MEMORY

K5L5628JT(B)M

Vtt=0.5 x VCCQ

Figure 14. AC Output Load Circuit

AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Test Input/Output Reference)

Input pulse level: 0.2 to VCCQ-0.2V

50Ω

Input rising and falling time: 3ns

Input and output reference voltage: 0.5 x VCCQ

Output load: CL=30pF

Dout

Z0=50Ω

30pF

Table 18. ASYNCHRONOUS AC CHARACTERISTICS (VCC=2.5~2.7V, VCCQ=1.7~2.0V, TA=-30 to 85°C)

Speed

Parameter List

Symbol

Units

Min

10

70

25

-

Max

Common

CS High Pulse Width

tCSHP(A)

-

ns

Read Cycle Time

tRC

tPC

Page Read Cycle Time

-

Address Access Time

tAA

70

20

70

35

-

Page Access Time

tPA

-

Chip Select to Output

tCO

tOE

-

Output Enable to Valid Output

UB, LB Access Time

-

Async.

(Page)

Read

tBA

-

Chip Select to Low-Z Output

UB, LB Enable to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

UB, LB Disable to High-Z Output

Output Disable to High-Z Output

Output Hold

tLZ

10

5

tBLZ

tOLZ

tCHZ

tBHZ

tOHZ

tOH

tWC

tCW

tADV

tAS

-

5

-

0

12

-

0

3

Write Cycle Time

70

60

7

-

Chip Select to End of Write

ADV Minimum Low Pulse Width

Address Set-up Time to Beginning of Write

Address Valid to End of Write

UB, LB Valid to End of Write

Write Pulse Width

-

0

-

tAW

tBW

tWP

tWHP

tWR

tDW

tDH

60

55¹⁾

5

-

Async.

Write

-

WE High Pulse Width

-

Write Recovery Time

0

-

Data to Write Time Overlap

Data Hold from Write Time

30

0

-

1. tWP(min)=70ns for continuous write operation over 50 times.

77

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Preliminary

MCP MEMORY

K5L5628JT(B)M

ASYNCHRONOUS READ TIMING WAVEFORM

Fig.15 TIMING WAVEFORM OF ASYNCHRONOUS READ CYCLE (MRS=VIH, WE=VIH, WAIT=High-Z)

tRC

Address

tAA

tCSHP(A)

tOH

tCO

CS

tCHZ

tBHZ

tBA

UB, LB

tOE

OE

tOLZ

tBLZ

tLZ

tOHZ

High-Z

Data out

Data Valid

(ASYNCHRONOUS READ CYCLE)

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.

2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

3. In asynchronous read cycle, Clock, ADV and WAIT signals are ignored.

Table 19. ASYNCHRONOUS READ AC CHARACTERISTICS

Speed

Symbol

Units

Symbol

Units

Min

Max

-

Min

5

Max

-

tRC

tAA

70

-

ns

tOLZ

tBLZ

tLZ

ns

70

35

-

5

-

tCO

-

10

0

-

tBA

-

tCHZ

tBHZ

tOHZ

12

tOE

-

0

tOH

3

10

0

tCSHP(A)

-

78

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Preliminary

MCP MEMORY

K5L5628JT(B)M

ASYNCHRONOUS READ TIMING WAVEFORM

Fig.16 TIMING WAVEFORM OF PAGE READ CYCLE(MRS=VIH, WE=VIH, WAIT=High-Z)

tRC

Valid

Address

A22~A2

A1~A0

tOH

tAA

Valid

Address

Valid

Address Address Address

tPC

tCO

CS

tBA

UB, LB

tBHZ

tOE

OE

tCHZ

tOHZ

tOLZ

tBLZ

tPA

tLZ

High Z

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data out

(ASYNCHRONOUS 4 PAGE READ CYCLE)

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.

2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

3. In asynchronous 4 page read cycle, Clock, ADV and WAIT signals are ignored.

Table 20. ASYNCHRONOUS PAGE READ AC CHARACTERISTICS

Speed

Symbol

Units

Symbol

Units

Min

Max

-

Min

3

Max

tRC

tAA

tPC

tPA

tCO

tBA

tOE

70

-

ns

tOH

tOLZ

tBLZ

tLZ

-

ns

70

-

5

25

-

5

-

20

70

35

10

0

-

tCHZ

tBHZ

tOHZ

12

-

0

-

0

79

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Preliminary

MCP MEMORY

K5L5628JT(B)M

ASYNCHRONOUS WRITE TIMING WAVEFORM

Fig.17 TIMING WAVEFORM OF WRITE CYCLE(1)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled)

tWC

Address

CS

tCSHP(A)

tWR

tAW

tCW

tAW

tCW

tWR

tBW

UB, LB

WE

tWHP

tAS

tWP

tAS

tDH

tDW

Data in

Data Valid

Data out

High-Z

(ASYNCHRONOUS WRITE CYCLE - WE Controlled)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition

when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. t^ASis measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.

5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored.

6. Condition for continuous write operation over 50 times : tWP(min)=70ns

Table 21. ASYNCHRONOUS WRITE AC CHARACTERISTICS(WE Controlled)

Speed

Symbol

Units

Symbol

Units

Min

70

Max

Min

0

Max

tWC

tCW

tAW

tBW

tWP

-

ns

tAS

tWR

-

ns

60

0

60

tDW

30

0

60

tDH

55¹⁾

tCSHP(A)

10

1. tWP(min)=70ns for continuous write operation over 50 times.

80

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Preliminary

MCP MEMORY

K5L5628JT(B)M

ASYNCHRONOUS WRITE TIMING WAVEFORM

Fig.18 TIMING WAVEFORM OF WRITE CYCLE(2)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled)

tWC

Address

tWR

tCW

CS

tAW

tBW

UB, LB

tAS

tWP

WE

tDH

tDW

Data Valid

Data in

High-Z

Data out

High-Z

(ASYNCHRONOUS WRITE CYCLE - UB & LB Controlled)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition

when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. t^ASis measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.

5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored.

Table 22. ASYNCHRONOUS WRITE AC CHARACTERISTICS(UB & LB Controlled)

Speed

Symbol

Units

Symbol

Units

Min

70

Max

Min

0

Max

tWC

tCW

tAW

tBW

tWP

-

ns

tAS

tWR

tDW

tDH

-

ns

60

0

60

30

0

60

55¹⁾

1. tWP(min)=70ns for continuous write operation over 50 times.

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Preliminary

MCP MEMORY

K5L5628JT(B)M

Vtt=0.5 x VCCQ

Figure 24. AC Output Load Circuit

AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Test Input/Output Reference)

Input pulse level: 0.2 to VCCQ-0.2V

50Ω

Input rising and falling time: 3ns

Input and output reference voltage: 0.5 x VCCQ

Output load: CL=30pF

Dout

Z0=50Ω

30pF

Table 28. SYNCHRONOUS AC CHARACTERISTICS (VCC=2.5~2.7V, VCCQ=1.7~2.0V, TA=-30 to 85°C, Maximum Main Clock

Frequency=52.9MHz)

Speed

Parameter List

Clock Cycle Time

Symbol

Units

Min

18.9

-

Max

T

200

ns

Clock

ns

Burst Cycle Time

tBC

2500

Address Set-up Time to ADV Falling(Burst)

Address Hold Time from ADV Rising(Burst)

ADV Setup Time

tAS(B)

tAH(B)

tADVS

tADVH

tCSS(B)

tBEADV

tBSADV

tCSLH

tCSHP

tADHP

tWL

0

7

5

7

5

7

12

7

5

-

ADV Hold Time

-

CS Setup Time to Clock Rising(Burst)

Burst End to New ADV Falling

Burst Stop to New ADV Falling

CS Low Hold Time from Clock

CS High Pulse Width

-

Burst

Operation

(Common)

-

ADV High Pulse Width

-

Chip Select to WAIT Low

10

12

-

ADV Falling to WAIT Low

tAWL

tWH

-

Clock to WAIT High

-

Chip De-select to WAIT High-Z

UB, LB Enable to End of Latency Clock

Output Enable to End of Latency Clock

UB, LB Valid to Low-Z Output

Output Enable to Low-Z Output

Latency Clock Rising Edge to Data Output

Output Hold

tWZ

-

tBEL

1

5

-

tOEL

tBLZ

-

tOLZ

tCD

-

Burst Read

Operation

12

-

tOH

3

-

Burst End Clock to Output High-Z

Chip De-select to Output High-Z

Output Disable to Output High-Z

UB, LB Disable to Output High-Z

WE Set-up Time to Command Clock

WE Hold Time from Command Clock

WE High Pulse Width

tHZ

12

-

tCHZ

tOHZ

tBHZ

tWES

tWEH

tWHP

tBS

-

5

7

5

3

-

UB, LB Set-up Time to Clock

UB, LB Hold Time from Clock

Byte Masking Set-up Time to Clock

Byte Masking Hold Time from Clock

Data Set-up Time to Clock

-

Burst Write

Operation

tBH

-

tBMS

tBMH

tDS

-

Data Hold Time from Clock

tDHC

-

82

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Preliminary

MCP MEMORY

K5L5628JT(B)M

SYNCHRONOUS BURST OPERATION TIMING WAVEFORM

Fig.25 TIMING WAVEFORM OF BASIC BURST OPERATION [Latency=5,Burst Length=4](MRS=VIH)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

∼

CLK

ADV

tADVH

tADVS

tBEADV

tAH(B)

tAS(B)

Address

CS

Valid

Don’t Care

Valid

tCSS(B)

tBC

Undefined

Data out

Data in

DQ0 DQ1 DQ2 DQ3

D0

D1

D2

D3

D0

Burst Command Clock

Burst Read End Clock

Burst Write End Clock

Table 29. BURST OPERATION AC CHARACTERISTICS

Speed

Symbol

Units

Symbol

Units

Min

Max

200

2500

-

Min

0

Max

T

18.9

ns

tAS(B)

tAH(B)

-

ns

tBC

-

7

tADVS

tADVH

5

7

tCSS(B)

tBEADV

5

-

7

83

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November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

SYNCHRONOUS BURST READ TIMING WAVEFORM

Fig.26 TIMING WAVEFORM OF BURST READ CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH)

- CS Toggling Consecutive Burst Read

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

∼

CLK

ADV

tADVH

tADVS

tBEADV

tAH(B)

tAS(B)

Address

CS

Valid

Don’t Care

Valid

tCSHP

tCSS(B)

tBC

tBHZ

tBEL

LB, UB

OE

tBLZ

tOHZ

tOEL

tCHZ

tHZ

tOLZ

Latency 5

tCD

Undefined

tOH

Data out

WAIT

DQ0 DQ1 DQ2 DQ3

tWZ

tWL

tWH

tWL

High-Z

(SYNCHRONOUS BURST READ CYCLE - CS Toggling Consecutive Burst Read)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV

should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

4. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 30. BURST READ AC CHARACTERISTICS(CS Toggling Consecutive Burst)

Speed

Symbol

Units

Symbol

Units

Min

5

Max

Min

Max

12

-

tCSHP

tBEL

tOEL

tBLZ

tOLZ

tHZ

-

ns

clock

ns

tOHZ

tBHZ

tCD

-

ns

1

-

5

-

tOH

tWL

tWH

tWZ

3

-

5

-

ns

10

12

-

12

ns

-

tCHZ

-

ns

-

84

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November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

SYNCHRONOUS BURST READ TIMING WAVEFORM

Fig.27 TIMING WAVEFORM OF BURST READ CYCLE(2) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH)

- CS Low Holding Consecutive Burst Read

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

∼

CLK

ADV

tADVH

tADVS

tBEADV

tAH(B)

tAS(B)

Address

CS

Valid

Don’t Care

Valid

tCSS(B)

tBC

tBEL

tOEL

LB, UB

OE

tBLZ

tOLZ

Latency 5

tCD

Undefined

tOH

tHZ

Data out

WAIT

DQ0 DQ1 DQ2 DQ3

tAWL

tWH

tWL

tWH

High-Z

(SYNCHRONOUS BURST READ CYCLE - CS Low Holding Consecutive Burst Read)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV

should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

4. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address.

5. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 31. BURST READ AC CHARACTERISTICS(CS Low Holding Consecutive Burst)

Speed

Symbol

Units

Symbol

Units

Min

1

Max

Min

Max

12

-

tBEL

tOEL

tBLZ

tOLZ

tHZ

-

clock

ns

tCD

tOH

-

3

-

ns

1

5

-

tWL

10

12

5

-

ns

tAWL

tWH

-

12

ns

-

85

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

SYNCHRONOUS BURST READ TIMING WAVEFORM

Fig.28 TIMING WAVEFORM OF BURST READ CYCLE(3) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH)

- Last Data Sustaining

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

T

CLK

ADV

tADVH

tADVS

tAH(B)

tAS(B)

Address

CS

Valid

Don’t Care

tCSS(B)

tBC

tBEL

tOEL

LB, UB

OE

tBLZ

tOLZ

Latency 5

tOH

tCD

Undefined

Data out

DQ0 DQ1 DQ2 DQ3

tWL

tWH

High-Z

WAIT

(SYNCHRONOUS BURST READ CYCLE - Last Data Sustaining)

1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

3. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 32. BURST READ AC CHARACTERISTICS(Last Data Sustaining)

Speed

Symbol

Units

Symbol

Units

Min

1

Max

Min

Max

12

-

tBEL

tOEL

tBLZ

tOLZ

-

clock

ns

tCD

tOH

tWL

tWH

-

3

-

ns

1

5

10

12

5

ns

-

86

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

SYNCHRONOUS BURST WRITE TIMING WAVEFORM

Fig.29 TIMING WAVEFORM OF BURST WRITE CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH)

- CS Toggling Consecutive Burst Write

0

1

2

3

4

5

6

7

8

9

10

11

12

13

T

∼

CLK

ADV

tADVH

tADVS

tBEADV

tAH(B)

tAS(B)

Address

Valid

Don’t Care

tBC

tCSS(B)

tCSHP

CS

tBS

tBMS

tBH

tBMH

LB, UB

WE

tWEH

tWHP

tWES

tDS

tDHC

Latency 5

tWH

Latency 5

tWH

Data in

WAIT

D0

D1

D2

D3

D0

tWZ

tWL

High-Z

(SYNCHRONOUS BURST WRITE CYCLE - CS Toggling Consecutive Burst Write)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV

should be met.

2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

4. D2 is masked by UB and LB.

5. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 33. BURST WRITE AC CHARACTERISTICS(CS Toggling Consecutive Burst)

Speed

Symbol

Units

Symbol

Units

Min

5

Max

Min

Max

-

tCSHP

tBS

-

ns

tWHP

tDS

5

3

-

ns

5

-

tBH

5

tDHC

tWL

-

tBMS

tBMH

tWES

tWEH

7

10

12

7

tWH

tWZ

-

5

-

5

87

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

SYNCHRONOUS BURST WRITE TIMING WAVEFORM

Fig.30 TIMING WAVEFORM OF BURST WRITE CYCLE(2) [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH)

- CS Low Holding Consecutive Burst Write

0

1

2

3

4

5

6

7

8

9

10

11

12

13

T

∼

CLK

ADV

tADVH

tADVS

tBEADV

tAH(B)

tAS(B)

Address

CS

Valid

Don’t Care

tBC

tCSS(B)

tBS

tBMS

tBH

tBMH

LB, UB

WE

tWEH

tWHP

tWES

tDS

tDHC

Latency 5

tWH

Latency 5

tWH

Data in

WAIT

D0

D1

D2

D3

D0

tWL

tAWL

High-Z

(SYNCHRONOUS BURST WRITE CYCLE - CS Low Holding Consecutive Burst Write)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV

should be met.

2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

4. D2 is masked by UB and LB.

5. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address.

6. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 34. BURST WRITE AC CHARACTERISTICS(CS Low Holding Consecutive Burst)

Speed

Symbol

Units

Symbol

Units

Min

5

Max

Min

Max

-

tBS

tBH

-

ns

tWHP

tDS

5

3

-

ns

5

-

tBMS

tBMH

tWES

tWEH

7

tDHC

tWL

-

7

10

12

5

tAWL

tWH

-

5

-

88

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

SYNCHRONOUS BURST READ STOP TIMING WAVEFORM

Fig.31 TIMING WAVEFORM OF BURST READ STOP by CS [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

T

∼

CLK

ADV

tADVH

tADVS

tBSADV

tCSHP

tAH(B)

tAS(B)

Address

CS

Valid

Don’t Care

Valid

tCSS(B)

tCSLH

tBEL

tOEL

LB, UB

OE

tBLZ

tOLZ

Latency 5

tOH

tCHZ

tCD

Undefined

Data

DQ0

DQ1

tWZ

tWL

tWH

High-Z

WAIT

(SYNCHRONOUS BURST READ STOP TIMING)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBSADV

should be met

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

4. The burst stop operation should not be repeated for over 2.5µs.

Table 35. BURST READ STOP AC CHARACTERISTICS

Speed

Symbol

Units

Symbol

Units

Min

12

7

Max

Min

Max

12

-

tBSADV

tCSLH

tCSHP

tBEL

-

ns

tCD

tOH

tCHZ

tWL

tWH

tWZ

-

3

-

ns

5

ns

12

10

12

1

clock

ns

-

tOEL

1

-

tBLZ

5

-

tOLZ

5

ns

89

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

SYNCHRONOUS BURST WRITE STOP TIMING WAVEFORM

Fig.32 TIMING WAVEFORM OF BURST WRITE STOP by CS [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

T

∼

CLK

ADV

tADVH

tADVS

tBSADV

tCSHP

tAH(B)

tAS(B)

Don’t Care

Address

Valid

tCSS(B)

tCSLH

tBH

CS

tBS

LB, UB

WE

tWHP

tWEH

tWES

tDS

tDHC

Latency 5

tWH

Latency 5

tWH

Data in

WAIT

D0

D1

D0

D1

D2

tWZ

tWL

High-Z

(SYNCHRONOUS BURST WRITE STOP TIMING)

1. The new burst operation can be issued only after the previous burst operation is finished.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

4. The burst stop operation should not be repeated for over 2.5µs.

Table 36. BURST WRITE STOP AC CHARACTERISTICS

Speed

Symbol

Units

Symbol

Units

Min

12

7

Max

Min

Max

-

tBSADV

tCSLH

tCSHP

tBS

-

ns

tWHP

tDS

5

3

-

ns

-

5

tDHC

tWL

-

5

10

12

tBH

5

tWH

tWZ

-

tWES

tWEH

5

-

5

90

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

SYNCHRONOUS BURST READ SUSPEND TIMING WAVEFORM

Fig.33 TIMING WAVEFORM OF BURST READ SUSPEND CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH)

0

1

2

3

4

5

6

7

8

9

10

11

T

CLK

ADV

tADVH

tADVS

tAH(B)

tAS(B)

Address

CS

Valid

Don’t Care

tCSS(B)

tBC

tBEL

tOEL

LB, UB

OE

tBLZ

tOLZ

Latency 5

tOHZ

tOLZ

tOH

tCD

Undefined

tHZ

High-Z

Data out

WAIT

DQ0 DQ1

DQ1 DQ2 DQ3

tWZ

tWL

tWH

High-Z

(SYNCHRONOUS BURST READ SUSPEND CYCLE)

1. If clock input is halted during burst read operation, the data out will be suspended. During the burst read suspend period, OE high

drives data out to high-Z. If clock input is resumed, the suspended data will be out first.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. During suspend period, OE high drives DQ to High-Z and OE low drives DQ to Low-Z.

If OE stays low during suspend period, the previous data will be sustained.

4. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 37. BURST READ SUSPEND AC CHARACTERISTICS

Speed

Symbol

Units

Symbol

Units

Min

1

Max

Min

Max

12

tBEL

tOEL

tBLZ

tOLZ

tCD

-

clock

ns

tHZ

tOHZ

tWL

-

ns

1

12

5

-

10

5

-

ns

tWH

tWZ

12

-

12

-

ns

12

tOH

3

ns

91

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE

Fig.34 SYNCH. BURST READ to ASYNCH. WRITE(Address Latch Type) TIMING WAVEFORM

[Latency=5, Burst Length=4](MRS=VIH)

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21

T

CLK

ADV

tADVH

tADVS

tADV

tAH(A)

tBEADV

tAS(A)

tAH(B)

tAS(B)

Valid

Don’t Care

Valid

Address

CS

tCSS(B)

tAW

tCW

tBC

tCSS(A)

tWLRL

tWP

WE

OE

tAS

tOEL

tBEL

tBW

LB, UB

Data in

Data out

WAIT

tDH

tDW

Data Valid

Latency 5

High-Z

tCD

tOH

DQ0 DQ1 DQ2 DQ3

tHZ

High-Z

tWL

tWZ

tWH

High-Z

Read Latency 5

(SYNCHRONOUS BURST READ CYCLE)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV

should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

4. Burst Cycle Time(tBC) should not be over 2.5µs.

(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)

1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation.

Table 38. BURST READ to ASYNCH. WRITE(Address Latch Type) AC CHARACTERISTICS

Speed

Symbol

Units

Symbol

Units

Min

Max

Min

Max

tBEADV

7

-

ns

tWLRL

1

-

clock

92

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE

Fig.35 SYNCH. BURST READ to ASYNCH. WRITE(Low ADV Type) TIMING WAVEFORM

[Latency=5, Burst Length=4](MRS=VIH)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

21

T

CLK

ADV

tADVH

tADVS

tBEADV

tAH(B)

tAS(B)

Address

CS

Valid

Don’t Care

Valid Address

tWR

tAW

tCW

tCSS(B)

tBC

tWLRL

tWP

WE

OE

tAS

tOEL

tBEL

tBW

LB, UB

Data in

Data out

tDH

tDW

Data Valid

Latency 5

High-Z

tCD

tOH

DQ0 DQ1 DQ2 DQ3

tHZ

High-Z

tWL

tWZ

tWH

High-Z

Read Latency 5

WAIT

(SYNCHRONOUS BURST READ CYCLE)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV

should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

4. Burst Cycle Time(tBC) should not be over 2.5µs.

(LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)

1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation.

Table 39. BURST READ to ASYNCH. WRITE(Low ADV Type) AC CHARACTERISTICS

Speed

Symbol

Units

Symbol

Units

Min

Max

Min

Max

tBEADV

7

-

ns

tWLRL

1

-

clock

93

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE

Fig.36 ASYNCH. WRITE(Address Latch Type) to SYNCH. BURST READ TIMING WAVEFORM

[Latency=5, Burst Length=4](MRS=VIH)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

T

0

CLK

ADV

tADVH

tAH(B)

tADVS

tADV

tAH(A)

tAS(A)

tAS(B)

Address

CS

Don’t Care

tAW

tCW

Don’t Care

Valid

tBC

tCSS(A)

tCSS(B)

tWLRL

tWP

WE

OE

tAS

tOEL

tBEL

tBW

LB, UB

Data in

Data out

tDH

tDW

Data Valid

Latency 5

tCD

tOH

tHZ

High-Z

Read Latency 5

DQ0 DQ1 DQ2 DQ3

tWH

tWL

tWZ

High-Z

WAIT

(SYNCHRONOUS BURST READ CYCLE)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV

should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

4. Burst Cycle Time(tBC) should not be over 2.5µs.

(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)

1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation.

Table 40. ASYNCH. WRITE(Address Latch Type) to BURST READ AC CHARACTERISTICS

Speed

Symbol

Units

Symbol

Units

Min

Max

Min

Max

tWLRL

1

-

clock

94

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE

Fig.37 ASYNCH. WRITE(Low ADV Type) to SYNCH. BURST READ TIMING WAVEFORM

[Latency=5, Burst Length=4](MRS=VIH)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

T

0

CLK

tADVH

tAH(B)

_tADt_HA_PDVS

ADV

tAS(B)

tWC

Address

CS

Valid

Don’t Care

tAW

tCW

tWR

tBC

tCSS(B)

tWLRL

tWP

WE

OE

tAS

tOEL

tBEL

tBW

LB, UB

Data in

Data out

tDH

tDW

Data Valid

Latency 5

tCD

tOH

tHZ

High-Z

DQ0 DQ1 DQ2 DQ3

tWH

tWL

tWZ

High-Z

Read Latency 5

WAIT

(SYNCHRONOUS BURST READ CYCLE)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV

should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

4. Burst Cycle Time(tBC) should not be over 2.5µs.

(LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)

1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation.

Table 41. ASYNCH. WRITE(Low ADV Type) to BURST READ AC CHARACTERISTICS

Speed

Symbol

Units

Symbol

Units

Min

Max

Min

Max

tWLRL

1

-

clock

tADHP

5

-

ns

95

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE

Fig.38 SYNCH. BURST READ to SYNCH. BURST WRITE TIMING WAVEFORM

[Latency=5, Burst Length=4](MRS=VIH)

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21

T

CLK

ADV

tADVH

tADVS

tBEADV

tAH(B)

tAS(B)

Valid

Don’t Care

Valid

Address

CS

tCSS(B)

tBC

tCSS(B)

tWES

tWEH

WE

OE

tOEL

tBEL

tBS

tBH

LB, UB

Data in

tDS

D3

Latency 5

tDHC

D0

D1

D2

High-Z

Latency 5

High-Z

tCD

tOH

DQ0 DQ1 DQ2 DQ3

tWZ

tHZ

High-Z

Data out

WAIT

tWH

tWZ

tWL

tWH

tWL

High-Z

(SYNCHRONOUS BURST READ & WRITE CYCLE)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV

should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

4. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 42. BURST READ to BURST WRITE AC CHARACTERISTICS

Speed

Symbol

Units

Symbol

Units

Min

Max

Min

Max

tBEADV

7

-

ns

96

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE

Fig.39 SYNCH. BURST WRITE to SYNCH. BURST READ TIMING WAVEFORM

[Latency=5, Burst Length=4](MRS=VIH)

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21

T

CLK

ADV

tADVH

tADVS

tBEADV

tAH(B)

tAS(B)

Valid

Don’t Care

Valid

Address

CS

tCSS(B)

tBC

tCSS(B)

tWES

tWEH

WE

OE

tOEL

tBS

tBH

tBEL

LB, UB

tDS

Latency 5

tDHC

D0

D1

D2

D3

High-Z

Data in

Data out

WAIT

Latency 5

tCD

tOH

tHZ

DQ0 DQ1 DQ2 DQ3

High-Z

tWL

tWH

tWZ

tWH

tWL

High-Z

(SYNCHRONOUS BURST READ & WRITE CYCLE)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV

should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)

/WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

4. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 43. BURST WRITE to BURST READ AC CHARACTERISTICS

Speed

Symbol

Units

Symbol

Units

Min

Max

Min

Max

tBEADV

7

-

ns

97

Revision 1.0

November 2004

Preliminary

MCP MEMORY

K5L5628JT(B)M

PACKAGE DIMENSION

115-Ball FINE PITCH BGA Package (measured in millimeters)

#A1 INDEX MARK

8.00±0.10

0.10 MAX

A

8.00±0.10

0.80x9=7.20

(Datum A)

B

10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

0.80

#A1

(Datum B)

G

H

J

K

L

M

N

P

3.60

0.32±0.05

1.30±0.10

115-

∅

0.45±0.05

BOTTOM VIEW

TOP VIEW

∅

0.20

M A B

98

Revision 1.0

November 2004


型号：	K5L5628JTM-DH180
厂家：	SAMSUNG
描述：	Memory Circuit, 16MX16, CMOS, PBGA115, 8 X 12 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, FBGA-115 内存集成电路
文件：	总98页 (文件大小：1567K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K5L5628JTM-DH180 [SAMSUNG]

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