K6E0808V1C-J15 [SAMSUNG]
SRAM;型号: | K6E0808V1C-J15 |
厂家: | SAMSUNG |
描述: | SRAM 静态存储器 |
文件: | 总9页 (文件大小:180K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
CMOS SRAM
K6E0808V1C-C
Document Title
32Kx8 Bit High Speed Static RAM(3.3V Operating), Evolutionary Pin out.
Revision History
RevNo.
Rev. 0.0
Rev. 1.0
History
Draft Data
Remark
Preliminary
Final
Initial release with Preliminary.
Jun. 1st, 1994
Oct. 4th, 1994
Release to final Data Sheet.
1. Delete Preliminary
Rev. 2.0
Rev. 3.0
2.1. Add 28-TSOP1 Package.
Feb. 22th, 1996
Feb. 25th, 1998
Final
Final
3.1. Delete DIP Package.
3.2. Delete 20ns part
3.3. Add Capacitive load of the test environment in A.C test load
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev 3.0
February 1998
- 1 -
PRELIMINARY
CMOS SRAM
K6E0808V1C-C
32K x 8 Bit High-Speed CMOS Static RAM (3.3V Operating)
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 15, 17ns(Max.)
• Low Power Dissipation
The K6E0808V1C is a 262,144-bit high-speed Static Random
Access Memory organized as 32,768 words by 8 bits. The
K6E0808V1C uses 8 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG¢s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
Standby (TTL)
: 30mA(Max.)
(CMOS) : 0.1mA(Max.)
Operating K6E0808V1C-15 : 90mA(Max.)
K6E0808V1C-17 : 80mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
high-density
high-speed
system
applications.
The
K6E0808V1C is packaged in a 300mil 28-pin plastic SOJ or
TSOP1 forward.
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention; L-ver. only
• Standard Pin Configuration
PIN CONFIGURATION(Top View)
K6E0808V1C-J : 28-SOJ-300
K6E0808V1C-T : 28-TSOP1-0813, 4F
OE
A11
A9
1
2
3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A8
4
5
6
7
8
9
10
11
12
13
14
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
TSOP1
A1
A2
FUNCTIONAL BLOCK DIAGRAM
A14
1
2
3
4
5
6
7
8
9
28 Vcc
27 WE
26 A13
25 A8
Clk Gen.
Pre-Charge-Circuit
A12
A7
A6
A5
A4
A3
A2
A1
A3
A4
24 A9
A5
A6
23 A11
22 OE
21 A10
20 CS
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
Memory Array
512 Rows
64x8 Columns
A7
SOJ
A8
A12
A13
A14
A0 10
I/O1 11
I/O2 12
I/O3 13
Vss 14
Data
Cont.
I/O Circuit
Column Select
I/O1~I/O8
CLK
Gen.
PIN FUNCTION
A0
A1
A2
A9
A10
A11
Pin Name
A0 - A14
WE
Pin Function
Address Inputs
Write Enable
Chip Select
CS
WE
OE
CS
OE
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
I/O1 ~ I/O8
VCC
VSS
Rev 3.0
February 1998
- 2 -
PRELIMINARY
CMOS SRAM
K6E0808V1C-C
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
VIN, VOUT
VCC
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
Unit
V
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
V
PD
W
Storage Temperature
TSTG
-65 to 150
0 to 70
°C
°C
Operating Temperature
TA
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
Parameter
Min
3.0
0
Symbol
VCC
Typ
Max
3.6
Unit
V
Supply Voltage
3.3
Ground
VSS
0
-
0
V
Input High Voltage
Input Low Voltage
VIH
2.2
-0.3*
VCC+0.3**
0.8
V
VIL
-
V
* VIL(Min) = -2.0(Pulse Width £ 12ns) for I £ 20mA
** VIH(Max) = VCC+2.0V(Pulse Width £ 12ns) for I £ 20mA
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C,VCC=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Symbol
Test Conditions
VIN = VSS to VCC
Min
-2
Max
2
Unit
mA
ILI
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT = VSS to VCC
-2
2
mA
Operating Current
Standby Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN = VIH or VIL, IOUT=0mA
15ns
17ns
-
-
-
-
90
80
30
0.1
mA
ISB
Min. Cycle, CS=VIH
mA
mA
ISB1
f=0MHz, CS³ VCC-0.2V,
VIN³ VCC-0.2V or VIN£0.2V
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
-
0.4
-
V
V
IOH=-4mA
2.4
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
Test Conditions
VI/O=0V
MIN
Max
Unit
CI/O
CIN
-
-
8
7
pF
pF
VIN=0V
* Capacitance is sampled and not 100% tested.
Rev 3.0
February 1998
- 3 -
PRELIMINARY
CMOS SRAM
K6E0808V1C-C
AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
3ns
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
Output Loads(A)
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+3.3V
RL = 50W
DOUT
319W
VL = 1.5V
DOUT
30pF*
ZO = 50W
353W
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE
Parameter
K6E0808V1C-15
K6E0808V1C-17
Symbol
Unit
Min
15
-
Max
Min
17
-
Max
Read Cycle Time
tRC
tAA
-
15
15
7
-
17
17
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tLZ
-
-
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
-
-
3
-
3
-
tOLZ
tHZ
0
-
0
-
0
7
0
8
tOHZ
tOH
tPU
tPD
0
7
0
8
3
-
3
-
0
-
0
-
-
15
-
17
Rev 3.0
February 1998
- 4 -
PRELIMINARY
CMOS SRAM
K6E0808V1C-C
WRITE CYCLE
K6E0808V1C-15
K6E0808V1C-17
Parameter
Symbol
Unit
Min
15
11
0
Max
Min
17
12
0
Max
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
6
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
11
11
15
0
12
12
17
0
Write to Output High-Z
0
0
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
8
8
0
0
tOW
0
0
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Valid Data
Data Out
Previous Valid Data
Rev 3.0
February 1998
- 5 -
PRELIMINARY
CMOS SRAM
K6E0808V1C-C
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tHZ(3,4,5)
tCO
CS
tOHZ
tOE
OE
tOLZ
tOH
tLZ(4,5)
Data out
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
OE
tWR(5)
tAW
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDH
tDW
High-Z
Data in
Valid Data
tOHZ(6)
High-Z(8)
Data out
Rev 3.0
February 1998
- 6 -
PRELIMINARY
CMOS SRAM
K6E0808V1C-C
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tWR(5)
tAW
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
tDH
High-Z
Data in
Valid Data
tWHZ(6)
tOW
(10)
(9)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
tWP(2)
CS
tAS(4)
WE
tDH
tDW
High-Z
High-Z
High-Z
Data in
Data out
Valid Data
tLZ
tWHZ(6)
High-Z(8)
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end
of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
Rev 3.0
February 1998
- 7 -
PRELIMINARY
CMOS SRAM
K6E0808V1C-C
FUNCTIONAL DESCRIPTION
CS
H
L
WE
X
OE
X*
H
Mode
Not Select
Output Disable
Read
I/O Pin
High-Z
High-Z
DOUT
Supply Current
ISB, ISB1
ICC
H
L
H
L
ICC
L
L
X
Write
DIN
ICC
* NOTE : X means Don¢t Care.
DATA RETENTION CHARACTERISTICS(TA=0 to 70°C)
Parameter
VCC for Data Retention
Data Retention Current
Data Retention Set-Up Time
Recovery Time
Symbol
VDR
Test Condition
CS³ VCC - 0.2V
Min.
Typ.
Max.
3.6
0.07
-
Unit
V
2.0
-
-
-
-
-
IDR
VCC = 3.0V, CS³ VCC - 0.2V
mA
ns
tSDR
0
See Data Retention
Wave form(below)
tRDR
5
-
ms
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0V
VIH
VDR
CS³ VCC - 0.2V
CS
GND
Rev 3.0
February 1998
- 8 -
PRELIMINARY
CMOS SRAM
K6E0808V1C-C
PACKAGE DIMENSIONS
Units:millimeters/Inches
28-SOJ-300
#28
#15
6.86 ±0.25
0.270 ±0.010
8.51 ±0.12
0.335 ±0.005
+0.10
-0.05
0.20
+0.004
0.008-0.002
#1
#14
0.69
0.027
MIN
18.82
0.741
MAX
18.41 ±0.12
0.725 ±0.005
1.30
0.051
(
)
0.10
0.004
3.76
0.148
MAX
MAX
1.30
0.051
(
)
+0.10
-0.05
+0.10
0.71
0.43
-0.05
0.95
0.0375
1.27
0.050
(
)
+0.004
-0.002
+0.004
-0.002
0.017
0.028
28-TSOP1-0813.4F
Units:millimeters/Inches
13.40 ±0.20
0.528 ±0.008
+0.10
-0.05
+0.004
-0.002
0.20
0.008
0.425
(
)
#1
#28
0.017
0.55
0.0217
#14
#15
1.00 ±0.10
0.039 ±0.004
0.25
TYP
11.80 ±0.10
0.465 ±0.004
0.05
0.002
0.010
+0.10
-0.05
+0.004
-0.002
MIN
0.15
1.20
MAX
0.047
0.006
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
Rev 3.0
February 1998
- 9 -
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