K6E1004C1B-JC20 [SAMSUNG]

Standard SRAM, 256KX4, 20ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28;


型号：	K6E1004C1B-JC20
厂家：	SAMSUNG
描述：	Standard SRAM, 256KX4, 20ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28 静态存储器光电二极管内存集成电路
文件：	总9页 (文件大小：132K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

K6E1004C1B-C/B-L

CMOS SRAM

Document Title

256Kx4 Bit (with OE) High Speed Static RAM(5V Operating), Evolutionary Pin out.

Revision History

Rev.No.

Rev. 0.0

Rev.1.0

History

Draft Data

Remark

Initial release with Design Target.

Feb. 1st 1997

Jun. 1st 1997

Design Target

Preliminary

Release to Preliminary Data Sheet.

1.1. Replace Design Target to Preliminary.

Rev. 2.0

Release to Final Data Sheet.

Feb. 6th 1998

Final

2.1. Delete Preliminary.

2.2. Delete 17ns, L-version and Industrial Temperature Part.

2.3. Delete VOH1=3.95V.

2.4. Delete Data Retention Characteristics and Wave form.

2.5. Relex operating current.

Speed

15ns

17ns

20ns

120mA

110mA

100mA

Now

120mA

118mA

Rev.3.0

3.1. Add Low power Version.

Jul. 28th 1998

Final

3.2. Add Data Retention chcracteristics.

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev. 3.0

July 1998

- 1 -

PRELIMINARY

K6E1004C1B-C/B-L

CMOS SRAM

256K x 4 Bit (with OE)High-Speed CMOS Static RAM

FEATURES

• Fast Access Time 15, 20ns(Max.)

GENERAL DESCRIPTION

The K6E1004C1B is a 1,048,576-bit high-speed Static Random

• Low Power Dissipation

Access Memory organized as 262,144 words by 4 bits. The

K6E1004C1B uses 4 common input and output lines and has at

output enable pin which operates faster than address access

time at read cycle. The device is fabricated using SAMSUNG¢s

advanced CMOS process and designed for high-speed circuit

technology. It is particularly well suited for use in high-density

high-speed system applications. The K6E1004C1B is packaged

in a 400 mil 28-pin plastic SOJ.

Standby (TTL)

(CMOS) : 5mA(Max.)

1mA(Max) L-Ver. Only

: 20mA(Max.)

Operating K6E1004C1B-15 : 120mA(Max.)

K6E1004C1B-20 : 118mA(Max.)

• Single 5.0V±10% Power Supply

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• 2V Minimum Data Retention ; L-Ver. only

• Standard Pin Configuration

K6E1004C1B-J : 28-SOJ-400A

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION(Top View)

Clk Gen.

Pre-Charge Circuit

28 Vcc

27 A17

26 A16

25 A15

24 A14

23 A13

22 A12

21 A11

20 N.C

19 I/O4

18 I/O3

17 I/O2

16 I/O1

15 WE

Memory Array

512 Rows

512x4 Columns

SOJ

A9 10

A10 11

CS 12

OE 13

Vss 14

Data

Cont.

I/O Circuit &

Column Select

I/O1~I/O4

CLK

Gen.

A9 A10 A11 A12 A13 A14 A15 A16 A17

PIN FUNCTION

Pin Name

A0 - A17

Pin Function

Address Inputs

Write Enable

Chip Select

Output Enable

Data Inputs/Outputs

Power(+5.0V)

Ground

I/O1 ~ I/O4

VCC

VSS

N.C

No Connection

Rev. 3.0

July 1998

- 2 -

PRELIMINARY

K6E1004C1B-C/B-L

CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

Parameter

Voltage on Any Pin Relative to VSS

Voltage on VCC Supply Relative to VSS

Power Dissipation

Symbol

VIN, VOUT

VCC

Rating

-0.5 to 7.0

1.0

Unit

Storage Temperature

TSTG

-65 to 150

0 to 70

°C

Operating Temperature

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)

Parameter

Supply Voltage

Symbol

Min

4.5

Typ

Max

Unit

VCC

5.0

5.5

Ground

VSS

Input High Voltage

Input Low Voltage

VIH

2.2

-0.5*

VCC+0.5**

0.8

VIL

VIL(Min) = -2.0V a.c(Pulse Width £ 10ns) for I £ 20mA .

** VIH(Max) = VCC + 2.0V a.c (Pulse Width £10ns) for I £ 20mA

DC AND OPERATING CHARACTERISTICS (TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)

Parameter

Symbol

Test Conditions

VIN=VSS to VCC

Min

-2

Max

Unit

Input Leakage Current

Output Leakage Current

ILI

ILO

CS=VIH or OE=VIH or WE=VIL

VOUT=VSS to VCC

-2

Operating Current

Standby Current

ICC

Min. Cycle, 100% Duty

CS=VIL, VIN=VIH or VIL, IOUT=0mA

15ns

20ns

120

118

ISB

Min. Cycle, CS=VIH

ISB1

f=0MHz, CS³ VCC-0.2V,

VIN³ VCC-0.2V or VIN£0.2V

Normal

L-ver

Output Low Voltage Level

Output High Voltage Level

VOL

VOH

IOL=8mA

0.4

IOH=-4mA

2.4

CAPACITANCE*(TA=25°C, f=1.0MHz)

Item

Input/Output Capacitance

Input Capacitance

Symbol

Test Conditions

VI/O=0V

MIN

Max

Unit

CI/O

CIN

VIN=0V

* Capacitance is sampled and not 100% tested.

Rev. 3.0

July 1998

- 3 -

PRELIMINARY

K6E1004C1B-C/B-L

CMOS SRAM

AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)

TEST CONDITIONS

Parameter

Value

0V to 3V

3ns

Input Pulse Levels

Input Rise and Fall Times

Input and Output timing Reference Levels

Output Loads

1.5V

See below

Output Loads(A)

Output Loads(B)

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

+5.0V

480W

DOUT

255W

30pF*

5pF*

* Including Scope and Jig Capacitance

READ CYCLE

Parameter

K6E1004C1B-15

K6E1004C1B-20

Symbol

Unit

Min

Max

Min

Max

Read Cycle Time

tRC

tAA

Address Access Time

Chip Select to Output

tCO

tOE

tLZ

Output Enable to Valid Output

Chip Enable to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

Chip Selection to Power Up Time

Chip Selection to Power DownTime

tOLZ

tHZ

tOHZ

tOH

tPU

tPD

Rev. 3.0

July 1998

- 4 -

PRELIMINARY

K6E1004C1B-C/B-L

CMOS SRAM

WRITE CYCLE

K6E1004C1B-15

Min Max

K6E1004C1B-20

Parameter

Symbol

Unit

Min

Max

Write Cycle Time

tWC

tCW

tAS

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width(OE High)

Write Pulse Width(OE Low)

Write Recovery Time

tAW

tWP

tWP1

tWR

tWHZ

tDW

tDH

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

tOW

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tRC

Address

tAA

tOH

Valid Data

Data Out

Previous Valid Data

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tAA

tHZ(3,4,5)

tCO

tOHZ

tOE

tOLZ

tOH

tLZ(4,5)

Data out

Valid Data

tPU

tPD

ICC

ISB

VCC

50%

Current

Rev. 3.0

July 1998

- 5 -

PRELIMINARY

K6E1004C1B-C/B-L

CMOS SRAM

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or

VOL levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to

device.

5. Transition is measured ±200mV space from steady state voltage with Load(B). This parameter is sampled and not 100%

tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)

tWC

Address

tWR(5)

tAW

tCW(3)

tWP(2)

tAS(4)

tDW

tDH

High-Z

Valid Data

Data in

Data out

tOHZ(6)

High-Z(8)

TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)

tWC

Address

tAW

tWR(5)

tCW(3)

tAS(4)

tWP1(2)

tDW

tDH

High-Z

Valid Data

Data in

tWHZ(6)

tOW

(9)

(10)

High-Z(8)

Data out

Rev. 3.0

July 1998

- 6 -

PRELIMINARY

K6E1004C1B-C/B-L

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)

tWC

Address

tAW

tWR(5)

tCW(3)

tWP(2)

tAS(4)

tDH

tDW

High-Z

Data in

Valid Data

tLZ

tWHZ(6)

High-Z(8)

High-Z

Data out

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low A

write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of

write.

3. tCW is measured from the later of CS going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

Rev. 3.0

July 1998

- 7 -

PRELIMINARY

K6E1004C1B-C/B-L

CMOS SRAM

FUNCTIONAL DESCRIPTION

Mode

Not Select

Output Disable

Read

I/O Pin

High-Z

DOUT

Supply Current

ISB, ISB1

ICC

Write

DIN

ICC

* X means Don¢t Care.

DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)

Parameter

VCC for Data Retention

Data Retention Current

Symbol

VDR

Test Condition

CS³ VCC-0.2V

Min.

Typ.

Max.

5.5

Unit

2.0

IDR

VCC=3.0V, CS³ VCC-0.2V

VIN³ VCC-0.2V or VIN£0.2V

0.4

Data Retention Set-Up Time

Recovery Time

tSDR

tRDR

See Data Retention

Wave form(below)

* Data Retention Characteristic is for L-ver only.

DATA RETENTION WAVE FORM

CS controlled

Data Retention Mode

tSDR

tRDR

VCC

4.5V

VIH

VDR

CS³ VCC - 0.2V

GND

Rev. 3.0

July 1998

- 8 -

PRELIMINARY

K6E1004C1B-C/B-L

CMOS SRAM

Units:millimeters/Inches

PACKAGE DIMENSIONS

28-SOJ-400A

#28

#15

9.40 ±0.25

0.370 ±0.010

11.18 ±0.12

0.440 ±0.005

+0.10

-0.05

0.20

+0.10

-0.002

#14

0.008

18.82

0.741

MAX

0.69

MIN

0.027

18.41 ±0.12

0.725 ±0.005

1.27

0.050

1.32

0.052

(

)

3.76

0.148

0.10

0.004

MAX

+0.10

0.43

0.017 ^+0.004

-0.05

+0.10

-0.05

0.71

-0.002

1.27

0.050

0.95

0.0375

(

)

+0.004

-0.002

0.028

Rev. 3.0

July 1998

- 9 -

K6E1004C1B-JC20 [SAMSUNG]

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