K6F2016R3M-TC30_技术文档

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

ocument Title

CMOS SRAM

128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No. History

Draft Date

Remark

0.0

0.1

Design target

October 2, 1996

Advance

Initial draft

December 1, 1996 Preliminary

- Add KM616FV2000 Family

- Erase KM616FU1000 Family and KM616FS1000 Family supprot

2.3~3.3V operating Vcc.

- Concept change high power version to low low power version

ISB1=10mA(Max)

- Add super low power version with special handling

ISB1=2.0mA(Max)

- Reduce Icc & Icc1

Write : 25mA to 20mA at Vcc=3.6V(Max)

1.0

2.0

Finalize

- Change datasheet format

- Erase reverse type package

March 4, 1998

May 3, 1999

Final

Revise

- Add 48-mBGA type package

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 2.0

1

May 1999

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

CMOS SRAM

128Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology: Full CMOS

· Organization: 128Kx16

The K6F2016V3M, K6F2016S3M and K6F2016R3M fami-

lies are fabricated by SAMSUNG¢s advanced Full CMOS

process technology. The families support various operating

temperature ranges for user flexibility of system design. The

families also support low data retention voltage for battery

back-up operation with low data retention current.

· Power Supply Voltage

K6F2016V3M Family: 3.0V ~ 3.6V

K6F2016S3M Family: 2.3V ~ 3.3V

K6F2016R3M Family: 1.8V ~ 2.7V

· Low Data Retention Voltage: 1.5V(Min)

· Three state output status and TTL Compatible

· Package Type: 44-TSOP2-400F, 48-mBGA-6.20x13.75

PRODUCT FAMILY

Power Dissipation

Product Family Operating Temperature Vcc Range

Speed(ns)

PKG Type

Standby

Operating

(ISB1, Max) (ICC2, Max)

70¹⁾/85@VCC=3.3±0.3V

85@VCC=3.0±0.3V

K6F2016V3M-C

K6F2016S3M-C

3.0~3.6V

2.3~3.3V

80mA

50mA

Commercial(0~70°C)

Industrial(-40~85°C)

44-TSOP2-

Forward

120¹⁾/150@VCC=2.5±0.2V

300¹⁾@VCC=2.0±0.2V

K6F2016R3M-C

K6F2016V3M-I

1.8~2.7V

3.0~3.6V

20mA

10mA²⁾

70¹⁾/85@VCC=3.3±0.3V

85@VCC=3.0±0.3V

80mA

50mA

20mA

44-TSOP2

Forward

48-mBGA³⁾

K6F2016S3M-I

2.3~3.3V

1.8~2.7V

120¹⁾/150@VCC=2.5±0.2V

300¹⁾@VCC=2.0±0.2V

K6F2016R3M-I

1. The parameter is measured with 30pF test load.

2. Super low power product=2mA with special handling.

3. Availiable parts are 100ns@VCC=3.0±0.3V, 150ns@VCC=2.5±0.2V and 300ns@VCC=2.0±0.2V with 30pF test load.

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

48-mBGA Top View

1

LB

2

OE

UB

3

A0

A3

A5

N.C

4

5

6

Clk gen.

Precharge circuit.

A4

A3

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

1

A5

2

A6

A1

A4

A6

A7

A2

N.C

I/O1

I/O3

Vcc

A

B

C

D

E

F

A2

3

A4

A7

Vcc

Vss

A1

4

OE

A3

A0

5

UB

I/O9

CS

I/O2

I/O4

A2

CS

6

LB

I/OI

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

WE

A16

A15

A14

A13

A12

7

I/O16

I/O15

I/O14

I/O13

Vss

A1

Memory array

1024 rows

128´ 16 columns

I/O10 I/O11

8

Row

select

A0

9

A16

A14

A15

A12

A13

10

11

12

13

14

15

16

17

18

19

20

21

22

44-TSOP2

Forward

Vss

Vcc

I/O12

I/O13

Vcc

I/O12

I/O11

I/O10

I/O9

N.C

A8

N.C

A14

A12

A9

A16

A15

A13

A10

I/O5

I/O6

WE

Vss

I/O7

I/O8

N.C

I/O15 I/O14

Data

cont

I/O Circuit

Column select

I/O1~I/O8

I/O16

N.C

A8

G

A9

Data

cont

A10

A11

N.C

I/O9~I/O16

A11

H

Data

cont

Name

CS

Function

Chip Select Input

Name

LB

Function

A9 A8 A5 A6 A7 A11 A10

Lower Byte(I/O1~8)

Upper Byte(I/O9~16)

OE

Output Enable Input

Write Enable Input

UB

WE

Vcc Power

Vss Ground

WE

OE

UB

LB

A0~A16 Address Inputs

Control

logic

I/O1~I/O16 Data Inputs/Outputs N.C. No Connection

CS

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 2.0

May 1999

2

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

CMOS SRAM

PRODUCT LIST

Commercial Temperature Products(0~70°C)

Industrial Temperature Products(-40~85°C)

Part Name

Function

Part Name

Function

K6F2016V3M-TC70

K6F2016V3M-TC85

44-TSOP2 F, 70ns, 3.3V, LL

44-TSOP2 F, 85ns, 3.3V, LL

K6F2016V3M-TI70

K6F2016V3M-TI85

44-TSOP2 F, 70ns, 3.3V, LL

44-TSOP2 F, 85ns, 3.3V, LL

K6F2016S3M-TC12

K6F2016S3M-TC15

44-TSOP2 F, 120/85ns, 2.5/3.0V, LL

44-TSOP2 F, 150/85ns, 2.5/3.0V, LL

K6F2016S3M-TI12

K6F2016S3M-TI15

K6F2016S3M-ZI15

44-TSOP2 F, 120/85ns, 2.5/3.0V, LL

44-TSOP2 F, 150/85ns, 2.5/3.0V, LL

48-mBGA, 2.5V/3.0V, 150/100ns

K6F2016R3M-TC30

44-TSOP2 F, 300ns, 2.0/2.5V, LL

K6F2016R3M-TI30

K6F2016R3M-ZI30

44-TSOP2 F, 300ns, 2.0/2.5V, LL

48-mBGA, 1.8V/2.5V, 300ns

FUNCTIONAL DESCRIPTION

CS

H

L

OE

X¹⁾

H

WE

X¹⁾

H

LB

X¹⁾

H

UB

X¹⁾

H

I/O1~8

High-Z

Dout

I/O9~16

High-Z

Dout

Mode

Power

Standby

Active

Deselected

Output Disabled

Lower Byte Read

Upper Byte Read

Word Read

X¹⁾

L

X¹⁾

H

L

H

L

H

L

High-Z

Dout

L

H

L

Dout

X¹⁾

L

H

Din

High-Z

Din

Lower Byte Write

Upper Byte Write

Word Write

L

H

L

High-Z

Din

L

Din

1. X means don¢t care. (Must be in low or high state)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

VIN,VOU

VCC

Ratings

-0.2 to 3.6V²⁾

-0.2 to 4.0V³⁾

1.0

Unit

V

Remark

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

-

V

PD

W

Storage temperature

TSTG

TA

-55 to 150

0 to 70

°C

Operating Temperature

°C K6F2016V3M-C, K6F2016S3M-C, K6F2016R3M-C

-40 to 85

°C

K6F2016V3M-I, K6F2016S3M-I, K6F2016R3M-I

-

Soldering temperature and time

TSOLDER 260°C, 5sec (Lead Only)

-

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. VIN/VOUT=-0.2 to 3.9V for K6F2016V3M Family.

3. VCC=-0.2 to 4.6V for K6F2016V3M Family

Revision 2.0

3

May 1999

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

Product

Min

3.0

2.3

1.8

0

Typ

3.3

Max

3.6

3.3

2.7

0

Unit

K6F2016V3M Family

K6F2016S3M Family

K6F2016R3M Family

All Family

Supply voltage

Vcc

V

2.5/3.0

2.0/2.5

0

Ground

Vss

VIH

V

K6F2016V3M Family

Vcc=3.3±0.3V

2.2

2.0

1.6

Vcc=3.0±0.3V

Vcc=2.5±0.2V

Vcc=2.0±0.2V

K6F2016S3M Family

Vcc+0.2²⁾

Input high voltage

-

K6F2016R3M Family

-0.2³⁾

Input low voltage

Note

VIL

All Family

0.4

V

1 Commercial Product : TA=0 to 70°C, unless otherwise specified

Industrial Product : TA=-40 to 85°C, unless otherwise specified

2. Overshoot : Vcc + 1.0V in case of pulse width £20ns

3. Undershoot : -1.0V in case of pulse width £20ns

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

VIN=0V

Min

Max

8

Unit

pF

-

Input/Output capacitance

CIO

VIO=0V

10

pF

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Test Conditions

Min

Typ

Max Unit

Input leakage current

VIN=Vss to Vcc

-1

-

1

mA

Output leakage current

Operating power supply current

ILO

CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS=VIL, VIN=VIL or VIH, Read

-1

ICC

-

3

mA

Read

Write

-

7

Cycle time=1ms, 100% duty, IIO=0mA,

CS£0.2V, VIN£0.2V or VIN³ VCC-0.2V

ICC1

ICC2

mA

-

20

70

60

20

0.4

-

Average operating current

Vcc=3.3V@70ns

Vcc=2.7V@120ns

Vcc=2.2V@300ns

-

Cycle time=Min, 100% duty,

IIO=0mA, CS=VIL, VIN=VIL or VIH

-

2.1mA at Vcc=3.0/3.3V

-

Output low voltage

Output high voltage

VOL

VOH

IOL

V

0.5mA at Vcc=2.5V

0.33mA at Vcc=2.0V

-1.0mA at Vcc=3.0/3.3V

-0.5mA at Vcc=2.5V

-0.44mA at Vcc=2.0V

-

2.4

2.0

1.6

-

IOH

-

Standby Current(TTL)

ISB

CS=VIH, Other inputs=VIL or VIH

0.3

10¹⁾

mA

Standby Current(CMOS)

ISB1

CS³ Vcc-0.2V, Other inputs=0~Vcc

-

mA

1. Super low power product=2mA with special handling.

Revision 2.0

May 1999

4

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

CMOS SRAM

AC OPERATING CONDITIONS

3)

VTM

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level : 0.4 to 2.2V for Vcc=3.3V, 3.0V, 2.5V

0.4 to 1.8V for Vcc=2.0V

2)

R1

Input rising and falling time : 5ns

Input and output reference voltage : 1.5V for Vcc=3.3V, 3.0V

1.1V for Vcc=2.5V

1)

3)

CL

R2

0.9V for Vcc=2.0V

1. Including scope and jig capacitance

Output load (See right) : CL=100pF+1TTL

CL=30pF+1TTL

2. R1=3070W, R2=3150W

3. VTM =2.8V for VCC=3.0/3.3V

=2.3V for VCC=2.5V

=1.8V for VCC=2.0V

AC CHARACTERISTICS (Commercial product :TA=0 to 70°C, Industrial product : TA=-40 to 85°C

K6F2016V3M Family : Vcc=3.0~3.6V, K6F2016S3M Family : Vcc=2.3~3.3V,

K6F2016R3M Family : Vcc=1.8~2.7V)

Speed Bins

Parameter List

Symbol

Units

70ns

85ns

100ns

120ns

150ns

300ns

Min Max Min Max Min Max Min Max Min Max Min Max

Read cycle time

tRC

tAA

70

-

70

35

-

85

-

85

45

-

100

-

120

-

150

-

300

-

ns

Address access time

100

120

150

300 ns

150 ns

Chip select to output

tCO

-

100

-

120

-

150

-

Output enable to valid output

UB, LB Access Time

tOE

-

50

-

60

-

75

-

tBA

-

Read

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

tLZ

10

5

10

5

10

5

20

0

20

0

50

30

0

-

ns

tOLZ, tBLZ

tHZ

-

0

25

-

0

25

-

0

30

-

35

-

40

-

60

-

Output disable to high-Z output tOHZ, tBHZ

0

Output hold from address change

Write cycle time

tOH

tWC

tCW

tAS

10

70

65

0

15

85

70

0

15

100

80

0

15

120

100

0

15

150

120

0

30

300

0

-

Chip select to end of write

Address set-up time

-

Address valid to end of write

Write pulse width

tAW

tWP

tBW

tWR

tWHZ

tDW

tDH

65

55

65

0

-

70

60

70

0

-

80

70

80

0

-

100

80

100

0

-

120

100

120

0

-

300

200

300

0

-

Write

UB, LB Valid to End of Write

Write recovery time

-

Write to output high-Z

Data to write time overlap

Data hold from write time

End write to output low-Z

0

25

-

0

25

-

0

30

-

0

35

-

0

40

-

0

60

-

30

0

35

0

40

0

50

0

60

0

120

0

-

tOW

5

-

5

-

5

-

5

-

5

-

20

-

DATA RETENTION CHARACTERISTICS

Item

Vcc for data retention

Data retention current

Data retention set-up time

Recovery time

Symbol

VDR

Test Condition

CS³ Vcc-0.2V

Vcc=3.0V, CS³ Vcc-0.2V

Min

Typ

Max

Unit

1.5

-

3.6

V

10¹⁾

-

IDR

mA

tSDR

0

See data retention waveform

ns

tRDR

tRC

-

1. Super low power product=2mA with special handling.

Revision 2.0

May 1999

5

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

CMOS SRAM

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO

CS

tHZ

tBA

UB, LB

OE

tBHZ

tOHZ

tOE

tOLZ

tBLZ

tLZ

Data out

High-Z

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 2.0

May 1999

6

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tCW(2)

tWR(4)

CS

tAW

tBW

UB, LB

tWP(1)

WE

tAS(3)

tDW

tDH

High-Z

Data in

Data Valid

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

tWC

Address

tAS(3)

tCW(2)

tWR(4)

CS

tAW

tBW

UB, LB

WE

tWP(1)

tDW

tDH

Data Valid

Data in

Data out

High-Z

Revision 2.0

May 1999

7

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

tWC

Address

tCW(2)

tWR(4)

CS

tAW

tBW

UB, LB

tAS(3)

tWP(1)

WE

tDH

tDW

Data in

Data Valid

High-Z

Data out

High-Z

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.

DATA RETENTION WAVE FORM

CS controlled

Data Retention Mode

tSDR

tRDR

VCC

3.0/2.7/2.3/1.8V

2.2V

VDR

CS³ VCC - 0.2V

CS

GND

Revision 2.0

May 1999

8

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

CMOS SRAM

PACKAGE DIMENSIONS

Units: millimeters(inches)

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

0~8°

0.25

0.010

(

)

#44

#23

0.45 ~0.75

0.018 ~ 0.030

11.76±0.20

0.463±0.008

0.50

0.020

(

)

#1

#22

1.00±0.10

0.039±0.004

18.81

0.741

1.20

0.047

MAX.

18.41±.10

0.725±0.004

0.10

0.004

MAX

0.35±0.10

0.014±0.004

0.80

0.0315

0.805

0.032

(

)

Revision 2.0

May 1999

9

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

CMOS SRAM

PACKAGE DIMENSIONS

48 BALL MICRO BALL GRID ARRAY- 0.75mm ball pitch

Units: millimeters

Top View

B

Bottom View

Ball #A1

B

6

5

4

3

2

1

A

B

C

D

E

F

Ball #A1

G

H

B1

B/2

SRAM Die

Elastomer

Detail A

A

Side View

D

Y

C

Elastomer

0.42/Typ.

Die

Min

Typ

0.75

6.20

3.75

Max

A

B

-

6.10

-

Notes.

5.90

1. Bump counts: 48(8row x 6column)

2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)

B1

C

-

3. All tolerence are +/-0.050 unless otherwise

specified.

7.90

13.75

5.25

0.35

0.80

0.55

0.25

-

8010

-

C1

D

-

4. Typ: Typical

0.30

0.40

0.81

-

5. Y is coplanarity: 0.08(Max)

E

-

E1

E2

Y

-

0.08

Revision 2.0

May 1999

10


型号：	K6F2016R3M-TC30
厂家：	SAMSUNG
描述：	Standard SRAM, 128KX16, 300ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44 静态存储器光电二极管
文件：	总10页 (文件大小：191K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K6F2016R3M-TC30 [SAMSUNG]

相关型号：

K6F2016R3M-TI30

K6F2016R4A-ZI100

K6F2016R4A-ZI700

K6F2016R4D-FF70

K6F2016R4D-FF85

K6F2016R4D-FF850

K6F2016R4E-EF70

K6F2016R4E-EF85

K6F2016R4E-EF850

K6F2016R4G

K6F2016R4G-F

K6F2016R4G-FF70