K6F4016U6G [SAMSUNG]
256Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM; 256Kx16位超低功耗和低电压全CMOS静态RAM
| 型号： | K6F4016U6G |
| 厂家： | 
SAMSUNG |
| 描述： | 256Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM |
| 文件： | 总9页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
K6F4016U6G Family
CMOS SRAM
Document Title
256Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial Draft
June 11, 2003
Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 0.0
June 2003
- 1 -
Preliminary
K6F4016U6G Family
CMOS SRAM
256K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: Full CMOS
· Organization: 256K x16 bit
· Power Supply Voltage: 2.7~3.3V
· Low Data Retention Voltage: 1.5V(Min)
· Three State Outputs
The K6F4016U6G families are fabricated by SAMSUNG¢s
advanced full CMOS process technology. The families support
industrial temperature range and 48 ball Chip Scale Package
for user flexibility of system design. The family also supports
low data retention voltage for battery back-up operation with
low data retention current.
· Package Type: 48-TBGA-6.00x7.00
PRODUCT FAMILY
Power Dissipation
Product Family Operating Temperature Vcc Range
Speed
PKG Type
Standby
(ISB1, Typ.)
Operating
(ICC1, Max)
551)/70ns
3mA2)
K6F4016U6G-F
Industrial(-40~85°C)
2.7~3.3V
4mA
48-TBGA-6.00x7.00
1. The parameter is measured with 30pF test load.
2. Typical value is measured at VCC=3.0V, TA=25°C and not 100% tested.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Clk gen.
Precharge circuit.
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
CS2
I/O1
I/O3
Vcc
Vcc
Vss
I/O9
CS1
I/O2
I/O4
I/O5
I/O6
WE
Row
Addresses
Memory
Cell
Array
Row
select
I/O10
Vss
I/O11
I/O12
I/O13
I/O14
DNU
A8
A5
A6
A17
DNU
A14
A12
A9
A7
I/O Circuit
Column select
Data
cont
Vcc
A16
A15
A13
A10
Vss
I/O1~I/O8
Data
cont
I/O9~I/O16
I/O15
I/O16
DNU
I/O7
I/O8
DNU
Data
cont
G
H
Column Addresses
A11
CS1
CS2
OE
48-TBGA: Top View (Ball Down)
Control Logic
WE
UB
Name
Function
Name
Vcc
Vss
UB
Function
Power
CS1, CS2 Chip Select Inputs
LB
OE
WE
Output Enable Input
Write Enable Input
Address Inputs
Ground
Upper Byte(I/O9~16)
Lower Byte(I/O1~8)
Do Not Use
A0~A17
LB
I/O1~I/O16 Data Inputs/Outputs
DNU
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 0.0
June 2003
- 2 -
Preliminary
K6F4016U6G Family
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
Function
K6F4016U6G-EF55
K6F4016U6G-EF70
48-TBGA, 55ns, 3.0V
48-TBGA, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
CS1
H
X1)
X1)
L
CS2
X1)
L
OE
X1)
X1)
X1)
H
WE
X1)
X1)
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Standby
Standby
Active
Deselected
Deselected
X1)
H
Deselected
X1)
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
L
X1)
L
L
H
H
H
Active
L
H
L
H
H
Active
L
H
L
H
H
L
High-Z
Dout
Active
L
H
L
H
L
L
Dout
Active
X1)
X1)
X1)
L
H
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
L
H
L
H
L
High-Z
Din
Active
L
H
L
L
L
Din
Active
1. X means don¢t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC
Ratings
-0.3 to VCC+0.3V(Max. 3.6V)
-0.3 to 3.6
Unit
V
V
PD
1.0
W
°C
°C
Storage temperature
TSTG
-65 to 150
Operating Temperature
TA
-40 to 85
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted within recommended operating condition. Exposure to absolute maximum rating conditions for extended period may affect reliability.
Revision 0.0
June 2003
- 3 -
Preliminary
K6F4016U6G Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
2.7
0
Typ
Max
3.3
Unit
V
Supply voltage
Ground
3.0
Vss
0
-
0
V
Vcc+0.32)
0.6
Input high voltage
Input low voltage
VIH
2.2
-0.33)
V
VIL
-
V
Note:
1. Industrial Product: TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+2.0V in case of pulse width £20ns.
3. Undershoot: -2.0V in case of pulse width £20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN=0V
VIO=0V
-
-
Input/Output capacitance
CIO
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Typ1)
Symbol
Item
Test Conditions
Min
Max
Unit
Input leakage current
ILI
VIN=Vss to Vcc
-1
-1
-
1
1
mA
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH,
VIO=Vss to Vcc
Output leakage current
ILO
-
-
mA
Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V, LB£0.2V
or/and UB£0.2V, CS2³ Vcc-0.2V, VIN£0.2V or VIN³ VCC-0.2V
ICC1
-
4
mA
Average operating current
Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL,
CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL or VIH
70ns
55ns
-
-
-
-
-
-
22
27
0.4
-
ICC2
mA
Output low voltage
Output high voltage
VOL
VOH
IOL = 2.1mA
IOH = -1.0mA
-
V
V
2.4
Other input =0~Vcc
Standby Current (CMOS)
ISB1
1) CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or
2) 0V£CS2£0.2V(CS2 controlled)
-
3
10
mA
1. Typical values are measured at VCC=3.0V, TA=25°C and not 100% tested.
Revision 0.0
June 2003
- 4 -
Preliminary
K6F4016U6G Family
CMOS SRAM
3)
VTM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
2)
2)
R1
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL= 100pF+1TTL
CL= 30pF+1TTL
1)
CL
R2
1. Including scope and jig capacitance
2. R1=3070W, R2=3150W
3. VTM =2.8V
AC CHARACTERISTICS ( Vcc=2.7~3.3V, Industrial product:TA=-40 to 85°C )
Speed
Parameter List
Symbol
Units
55ns
70ns
Min
55
-
Max
Min
70
-
Max
Read cycle time
tRC
tAA
-
55
55
25
55
-
-
70
70
35
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select to output
tCO
tOE
-
-
Output enable to valid output
UB, LB Access Time
-
-
tBA
-
-
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
tLZ
10
10
5
10
10
5
Read
tBLZ
tOLZ
tHZ
-
-
-
-
0
20
20
20
-
0
25
25
25
-
tBHZ
tOHZ
tOH
tWC
tCW
tAS
0
0
0
0
10
55
45
0
10
70
60
0
-
-
Chip select to end of write
Address set-up time
-
-
-
-
Address valid to end of write
UB, LB Valid to End of Write
Write pulse width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
45
45
40
0
-
60
60
50
0
-
-
-
Write
-
-
Write recovery time
-
-
Write to output high-Z
0
20
-
0
20
-
Data to write time overlap
Data hold from write time
End write to output low-Z
25
0
30
0
-
-
tOW
5
-
5
-
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
Test Condition
Min
Typ
Max
Unit
V
CS1³ Vcc-0.2V1), VIN³ 0V
1.5
-
-
-
-
-
3.3
Vcc=1.5V, CS1³ Vcc-0.2V1), VIN³ 0V
IDR
3
-
mA
tSDR
tRDR
0
See data retention waveform
ns
tRC
-
1. 1) CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or
2) 0£CS2£0.2V(CS2 controlled)
Revision 0.0
June 2003
- 5 -
Preliminary
K6F4016U6G Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS1
CS2
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 0.0
June 2003
- 6 -
Preliminary
K6F4016U6G Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS1
tCW(2)
tWR(4)
CS2
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
tAS(3)
tCW(2)
tAW
tWR(4)
CS1
CS2
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
Revision 0.0
June 2003
- 7 -
Preliminary
K6F4016U6G Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
CS1
tCW(2)
tAW
tWR(4)
CS2
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
2.7V
2.2V
VDR
CS1³ VCC-0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
2.7V
CS2
tSDR
tRDR
VDR
CS2£0.2V
0.4V
GND
Revision 0.0
June 2003
- 8 -
Preliminary
K6F4016U6G Family
CMOS SRAM
Unit: millimeters
PACKAGE DIMENSION
48 TAPE BALL GRID ARRAY(0.75mm ball pitch)
Top View
B
Bottom View
B
B1
6
5
4
3
2
1
A
B
#A1
C
D
E
F
G
H
B/2
Detail A
A
Side View
D
Y
C
Min
Typ
0.75
6.00
3.75
7.00
5.25
0.45
0.90
0.55
0.35
-
Max
-
A
B
-
5.90
-
Notes.
6.10
-
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
B1
C
6.90
-
7.10
-
C1
D
4. Typ: Typical
0.40
0.80
-
0.50
1.00
-
5. Y is coplanarity: 0.08(Max)
E
E1
E2
Y
0.30
-
0.40
0.08
Revision 0.0
June 2003
- 9 -
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