K6F8016U3M-TF550 [SAMSUNG]
Standard SRAM, 512KX16, 55ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;型号: | K6F8016U3M-TF550 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 512KX16, 55ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
文件: | 总9页 (文件大小:147K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K6F8016U3M Family
CMOS SRAM
Document Title
512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial draft
July 23, 1999
Preliminary
1.0
Finalized
April 17, 2000
Final
- Errata correction
- Change for tWHZ : 25 to 20ns for 70ns product.
- Change for tDW : 20 to 25ns for 55ns product.
25 to 30ns for 70ns product.
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
April 2000
K6F8016U3M Family
CMOS SRAM
512K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: Full CMOS
· Organization: 512K x16
The K6F8016U3M families are fabricated by SAMSUNG¢s
advanced full CMOS process technology. The families support
various operating temperature ranges and have small package
for user flexibility of system design. The families also support
low data retention voltage for battery back-up operation with low
data retention current.
· Power Supply Voltage: 2.7~3.3V
· Low Data Retention Voltage: 1.5V(Min)
· Three state output and TTL Compatible
· Package Type: 44-TSOP2-400F/R
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature Vcc Range
Speed
PKG Type
Standby
(ISB1, Typ.)
Operating
(ICC1, Max)
K6F8016U3M-B
K6F8016U3M-F
Commercial(0~70°C)
Industrial(-40~85°C)
551)/70ns
2.7~3.3V
0.5mA
4mA
44-TSOP2-400F/R
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A4
A3
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
A4
A5
A5
A6
Clk gen.
Precharge circuit.
2
A3
A6
A2
3
3
A2
A7
A7
A1
4
4
A1
OE
OE
Vcc
Vss
A0
5
5
A0
UB
UB
CS
6
6
LB
CS
LB
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A18
A17
A16
A15
A14
7
7
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
A8
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A18
A17
A16
A15
A14
I/O16
I/O15
I/O14
I/O13
Vss
8
8
Row
Addresses
Memory array
1024 rows
512´ 16 columns
9
9
Row
select
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
20
21
22
44-TSOP2
Forward
44-TSOP2
Reverse
Vcc
I/O12
I/O11
I/O10
I/O9
A8
I/O Circuit
Column select
Data
cont
A9
A9
I/O1~I/O8
A10
A11
A12
A13
A10
A11
Data
cont
A12
A13
I/O9~I/O16
Data
cont
Name
CS
Function
Name
Function
Column Addresses
Chip Select Input
Vcc Power
Vss Ground
OE
Output Enable Input
Write Enable Input
Address Inputs
CS1
CS2
OE
WE
UB
LB
Upper Byte(I/O9~16)
Lower Byte(I/O1~8)
A0~A18
Control Logic
WE
UB
I/O1~I/O16 Data Inputs/Outputs
LB
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.0
April 2000
K6F8016U3M Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Industrial Temperature Products(-40~85°C)
Part Name
Function
Part Name
Function
K6F8016U3M-TB55
K6F8016U3M-TB70
44-TSOP2-F, 55ns, 3.0V
44-TSOP2-F, 70ns, 3.0V
K6F8016U3M-TF55
K6F8016U3M-TF70
44-TSOP2-F, 55ns, 3.0V
44-TSOP2-F, 70ns, 3.0V
K6F8016U3M-RB55
K6F8016U3M-RB70
44-TSOP2-R, 55ns, 3.0V
44-TSOP2-R, 70ns, 3.0V
K6F8016U3M-RF55
K6F8016U3M-RF70
44-TSOP2-R, 55ns, 3.0V
44-TSOP2-R, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
CS
H
L
OE
X
H
X
L
WE
X
LB
X
X
H
L
UB
X
X
H
H
L
I/O1~8
High-Z
High-Z
High-Z
Dout
I/O9~16
Mode
Deselected
Power
High-Z
High-Z
High-Z
High-Z
Dout
Standby
H
X
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Active
Active
Active
Active
Active
Active
Active
Active
L
L
H
H
H
L
L
L
H
L
High-Z
Dout
L
L
L
Dout
L
L
H
L
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
X
X
X
L
L
H
L
High-Z
Din
L
L
L
Din
Note : X means don¢t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
Ratings
-0.2 to VCC+0.5V
-0.2 to 4.0
1.0
Unit
VIN,VOUT
VCC
V
V
PD
W
°C
°C
Storage temperature
TSTG
TA
-65 to 150
-40 to 85
Operating Temperature
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
April 2000
K6F8016U3M Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
2.7
0
Typ
Max
Unit
V
Supply voltage
Ground
3.0
3.3
0
Vss
0
-
V
Vcc+0.22)
0.6
Input high voltage
Input low voltage
Note:
VIH
2.2
V
-0.23)
VIL
-
V
1. Commercial products: TA=0 to 70°C, otherwise specified.
Industrial products: TA=-40 to 85°C, otherwise specified.
2. Overshoot: VCC+2.0V in case of pulse width £20ns.
3. Undershoot: -2.0V in case of pulse width £20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
pF
-
-
Input/Output capacitance
CIO
VIO=0V
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min
-1
-1
-
Typ
Max
Unit
mA
Input leakage current
VIN=Vss to Vcc
-
-
-
1
1
2
Output leakage current
Operating power supply current
ILO
CS=VIH, or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS=VIL, WE=VIH, VIN=VIH or VIL
mA
ICC
mA
Cycle time=1ms, 100%duty, IIO=0mA, CS£0.2V,
VIN£0.2V or VIN³ VCC-0.2V
ICC1
ICC2
-
-
-
-
4
mA
mA
Average operating current
Cycle time=Min, IIO=0mA, 100% duty,
CS=VIL, VIN=VIL or VIH
40
Output low voltage
VOL
VOH
ISB
IOL = 2.1mA
-
2.4
-
-
-
0.4
-
V
V
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
IOH = -1.0mA
CS=VIH, Other inputs=VIH or VIL
CS³ Vcc-0.2V, Other inputs=0~Vcc
-
0.3
mA
mA
251)
ISB1
-
0.5
1. Super low power product=10mA with special handling.
4
Revision 1.0
April 2000
K6F8016U3M Family
CMOS SRAM
3)
VTM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
2)
R1
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
1)
2)
CL
R2
1. Including scope and jig capacitance
2. R1=3070W, R2=3150W
3. VTM =2.8V
AC CHARACTERISTICS (Vcc=2.7~3.3V, Commercial Products: TA=0 to 70°C, Industrial products: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
55ns
70ns
Min
55
-
Max
Min
70
-
Max
Read Cycle Time
tRC
tAA
-
55
55
25
25
-
-
70
70
35
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
-
-
Output Enable to Valid Output
UB, LB Access Time
-
-
tBA
-
-
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tLZ
10
5
10
5
Read
tBLZ
tOLZ
tHZ
-
-
5
-
5
-
0
20
20
20
-
0
25
25
25
-
tBHZ
tOHZ
tOH
tWC
tCW
tAS
0
0
0
0
10
55
45
0
10
70
60
0
-
-
Chip Select to End of Write
Address Set-up Time
-
-
-
-
Address Valid to End of Write
UB, LB Valid to End of Write
Write Pulse Width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
45
45
40
0
-
60
60
50
0
-
-
-
Write
-
-
Write Recovery Time
-
-
Write to Output High-Z
0
20
-
0
20
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
25
0
30
0
-
-
tOW
5
-
5
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
CS1³ Vcc-0.2V1)
Min
1.5
-
Typ
Max
Unit
V
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
VDR
-
0.5
-
3.6
62)
-
Vcc=1.5V, CS1³ Vcc-0.2V1)
IDR
mA
tSDR
0
See data retention waveform
ns
tRDR
tRC
-
-
1. CS1³ Vcc-0.2V,CS2³ Vcc-0.2V(CS1 controlled) or CS2³ Vcc-0.2V(CS2 controlled).
2. Super low power product=4mA with special handling.
5
Revision 1.0
April 2000
K6F8016U3M Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
April 2000
K6F8016U3M Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS
tWR(4)
tCW(2)
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
WE
tWP(1)
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
7
Revision 1.0
April 2000
K6F8016U3M Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
CS
tCW(2)
tWR(4)
tAW
tBW
UB, LB
WE
tAS(3)
tWP(1)
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
2.7V
2.2V
VDR
CS³ VCC - 0.2V
CS
GND
8
Revision 1.0
April 2000
K6F8016U3M Family
CMOS SRAM
Unit: millimeters
PACKAGE DIMENSION
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0~8°
0.25
0.010
(
)
#44
#23
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
0.50
0.020
(
)
#1
#22
1.00±0.10
0.039±0.004
18.81
0.741
1.20
0.047
MAX.
MAX.
18.41±0.10
0.725±0.004
0.10
0.004
MAX
0.35± 0.10
0.014±0.004
0.80
0.0315
0.805
0.032
(
)
0~8°
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0.25
0.010
(
)
#1
#22
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
0.50
)
(
0.020
#44
#23
1.00±0.10
0.039±0.004
18.81
0.741
1.20
0.047
MAX.
MAX.
18.41± 0.10
0.725±0.004
0.10
0.004
MAX
0.35±0.10
0.014±0.004
0.80
0.0315
0.805
0.032
(
)
9
Revision 1.0
April 2000
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