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K6R1004V1B-JC08 [SAMSUNG]

Standard SRAM, 256KX4, 8ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32;
K6R1004V1B-JC08
型号： K6R1004V1B-JC08
厂家： SAMSUNG    SAMSUNG
描述：

Standard SRAM, 256KX4, 8ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

静态存储器 光电二极管 内存集成电路
文件： 总8页 (文件大小：125K)
中文：  中文翻译
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Preliminary  
PRELIMINARY  
CMOS SRAM  
K6R1004V1B-C  
Document Title  
256Kx4 Bit (with OE) High Speed Static RAM(3.3V Operating), Revolutionary Pin out.  
Revision History  
RevNo.  
Rev. 0.0  
Rev.1.0  
History  
Remark  
Draft Data  
Initial release with Design Target.  
Design Target  
Preliminary  
Apr. 1st, 1997  
Jun. 1st, 1997  
Feb. 25th, 1998  
Release to Preliminary Data Sheet.  
1.1. Replace Design Target to Preliminary.  
Final  
Rev.2.0  
Release to Final Data Sheet.  
2.1. Delete Preliminary.  
2.2. Delete L-version.  
2.3. Delete Data Retention Characteristics and Waveform.  
2.4. Delete Industrial Temperature Range Part.  
2.5. Delete TSOP2 Package.  
2.6. Add Capacitive load of the test environment in A.C test load.  
2.7. Change D.C characteristics.  
Previous spec.  
(8/10/12ns part)  
150/140/130mA  
30mA  
Changed spec.  
(8/10/12ns part)  
150/145/140mA  
50mA  
Items  
ICC  
ISB  
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the  
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-  
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.  
Rev 2.0  
February 1998  
- 1 -  
Preliminary  
PRELIMINARY  
CMOS SRAM  
K6R1004V1B-C  
256K x 4 Bit (with OE)High-Speed CMOS Static RAM(3.3V Operating)  
FEATURES  
• Fast Access Time 8,10,12ns(Max.)  
• Low Power Dissipation  
Standby (TTL)  
(CMOS) : 5mA(Max.)  
Operating K6R1004V1B-8 : 150mA(Max.)  
K6R1004V1B-10 : 145mA(Max.)  
K6R1004V1B-12 : 140mA(Max.)  
• Single 3.3±0.3V Power Supply  
• TTL Compatible Inputs and Outputs  
• Fully Static Operation  
GENERAL DESCRIPTION  
The K6R1004V1B is a 1,048,576-bit high-speed Static Random  
Access Memory organized as 262,144 words by 4 bits. The  
K6R1004V1B uses 4 common input and output lines and has  
an output enable pin which operates faster than address  
access time at read cycle. The device is fabricated using SAM-  
SUNG¢s advanced CMOS process and designed for high-  
speed circuit technology. It is particularly well suited for use in  
: 50mA(Max.)  
high-density  
high-speed  
system  
applications.  
The  
K6R1004V1B is packaged in a 400 mil 32-pin plastic SOJ.  
- No Clock or Refresh required  
• Three State Outputs  
• Center Power/Ground Pin Configuration  
• Standard Pin Configuration  
K6R1004V1B-J : 32-SOJ-400  
PIN CONFIGURATION(Top View)  
A17  
A16  
A15  
A14  
A13  
OE  
N.C  
A0  
1
2
3
4
5
6
7
8
9
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A1  
FUNCTIONAL BLOCK DIAGRAM  
A2  
A3  
CS  
I/O1  
Vcc  
Vss  
CLK. Gen.  
Pre-Charge Circuit  
I/O4  
Vss  
Vcc  
I/O3  
A12  
A11  
A10  
A9  
SOJ  
A0  
A1  
A2  
I/O2 10  
WE 11  
A4 12  
A5 13  
A6 14  
A7 15  
N.C 16  
Memory Array  
256 Rows  
1024x4 Columns  
A3  
A4  
A5  
A6  
A7  
A8  
N.C  
Data  
Cont.  
I/O Circuit &  
Column Select  
I/O1~I/O4  
CLK  
Gen.  
PIN FUNCTION  
A8 A9 A10 A11 A12 A13 A14 A15 A16A17  
Pin Name  
A0 - A17  
WE  
Pin Function  
Address Inputs  
Write Enable  
Chip Select  
CS  
WE  
OE  
CS  
OE  
Output Enable  
Data Inputs/Outputs  
Power(+3.3V)  
Ground  
I/O1 ~ I/O4  
VCC  
VSS  
N.C  
No Connection  
Rev 2.0  
February 1998  
- 2 -  
Preliminary  
PRELIMINARY  
CMOS SRAM  
K6R1004V1B-C  
ABSOLUTE MAXIMUM RATINGS*  
Parameter  
Symbol  
VIN, VOUT  
VCC  
Rating  
-0.5 to 4.6  
-0.5 to 4.6  
1.0  
Unit  
V
Voltage on Any Pin Relative to VSS  
Voltage on VCC Supply Relative to VSS  
Power Dissipation  
V
PD  
W
Storage Temperature  
TSTG  
-65 to 150  
0 to 70  
°C  
°C  
Operating Temperature  
TA  
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress ating only and  
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.  
Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)  
Parameter  
Min  
3.0  
0
Symbol  
Typ  
Max  
Unit  
V
Supply Voltage  
VCC  
3.3  
3.6  
Ground  
VSS  
0
-
0
VCC + 0.3**  
0.8  
V
V
Input High Voltage  
Input Low Voltage  
VIH  
2.0  
-0.3*  
V
VIL  
-
*
VIL(Min)=-2.0V a.c(Pulse Width £ 6ns) for I £ 20mA.  
** VIH(Max)=VCC + 2.0V a.c (Pulse Width £ 6ns) for I £ 20mA.  
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)  
Parameter  
Input Leakage Current  
Output Leakage Current  
Symbol  
Test Conditions  
VIN=VSS to VCC  
Min  
-2  
Max  
2
Unit  
mA  
ILI  
ILO  
CS=VIH or OE=VIH or WE=VIL  
VOUT=VSS to VCC  
-2  
2
mA  
Operating Current  
ICC  
Min. Cycle, 100% Duty  
CS=VIL, VIN=VIH or VIL,  
IOUT=0mA  
8ns  
10ns  
12ns  
-
-
-
-
-
150  
145  
140  
50  
mA  
mA  
Standby Current  
ISB  
Min. Cycle, CS=VIH  
ISB1  
f=0MHz, CS³ VCC-0.2V,  
5
VIN³ VCC-0.2V or VIN£0.2V  
Output Low Voltage Level  
Output High Voltage Level  
VOL  
VOH  
IOL=8mA  
-
0.4  
-
V
V
IOH=-4mA  
2.4  
CAPACITANCE*(TA=25°C, f=1.0MHz)  
Item  
Symbol  
Test Conditions  
VI/O=0V  
MIN  
Max  
8
Unit  
Input/Output Capacitance  
Input Capacitance  
CI/O  
CIN  
-
-
pF  
pF  
VIN=0V  
6
* Capacitance is sampled and not 100% tested.  
Rev 2.0  
February 1998  
- 3 -  
Preliminary  
PRELIMINARY  
CMOS SRAM  
K6R1004V1B-C  
AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)  
TEST CONDITIONS  
Parameter  
Value  
Input Pulse Levels  
0V to 3V  
3ns  
Input Rise and Fall Times  
Input and Output timing Reference Levels  
Output Loads  
1.5V  
See below  
Output Loads(B)  
Output Loads(A)  
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ  
+3.3V  
RL = 50W  
DOUT  
319W  
VL = 1.5V  
DOUT  
30pF*  
ZO = 50W  
353W  
5pF*  
* Capacitive Load consists of all components of the  
test environment.  
* Including Scope and Jig Capacitance  
READ CYCLE  
K6R1004V1B-8  
K6R1004V1B-10  
K6R1004V1B-12  
Parameter  
Symbol  
Unit  
Min  
Max  
Min  
10  
-
Max  
Min  
12  
-
Max  
Read Cycle Time  
tRC  
tAA  
tCO  
tOE  
tLZ  
8
-
-
8
8
4
-
-
10  
10  
5
-
12  
12  
6
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
-
-
-
Output Enable to Valid Output  
Chip Enable to Low-Z Output  
Output Enable to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
Output Hold from Address Change  
Chip Selection to Power Up Time  
Chip Selection to Power DownTime  
-
-
-
3
3
-
3
-
tOLZ  
tHZ  
0
0
0
3
0
-
-
0
-
0
-
4
4
-
0
5
0
6
tOHZ  
tOH  
tPU  
0
5
0
6
3
-
3
-
-
0
-
0
-
tPD  
8
-
10  
-
12  
Rev 2.0  
February 1998  
- 4 -  
Preliminary  
PRELIMINARY  
CMOS SRAM  
K6R1004V1B-C  
WRITE CYCLE  
Parameter  
K6R1004V1B-8  
K6R1004V1B-10  
K6R1004V1B-12  
Unit  
Symbol  
Min  
8
Max  
Min  
10  
7
Max  
Min  
12  
8
Max  
Write Cycle Time  
tWC  
tCW  
tAS  
-
-
-
-
-
-
-
4
-
-
-
-
-
-
-
-
-
-
5
-
-
-
-
-
-
-
-
-
-
6
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Select to End of Write  
Address Set-up Time  
6
0
0
0
Address Valid to End of Write  
Write Pulse Width(OE High)  
Write Pulse Width(OE Low)  
Write Recovery Time  
tAW  
tWP  
tWP1  
tWR  
tWHZ  
tDW  
tDH  
6
7
8
6
7
8
8
10  
0
12  
0
0
Write to Output High-Z  
0
0
0
Data to Write Time Overlap  
Data Hold from Write Time  
End Write to Output Low-Z  
4
5
6
0
0
0
tOW  
3
3
3
TIMMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)  
tRC  
Address  
tAA  
tOH  
Valid Data  
Data Out  
Previous Valid Data  
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
tRC  
Address  
tAA  
tHZ(3,4,5)  
tCO  
CS  
tOHZ  
tOE  
OE  
tOLZ  
tOH  
tLZ(4,5)  
Data out  
Valid Data  
tPU  
tPD  
ICC  
ISB  
VCC  
50%  
50%  
Current  
Rev 2.0  
February 1998  
- 5 -  
Preliminary  
PRELIMINARY  
CMOS SRAM  
K6R1004V1B-C  
NOTES(READ CYCLE)  
1. WE is high for read cycle.  
2. All read cycle timing is referenced from the last valid address to the first transition address.  
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or  
VOL levels.  
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to  
device.  
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.  
6. Device is continuously selected with CS=VIL.  
7. Address valid prior to coincident with CS transition low.  
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.  
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)  
tWC  
Address  
tWR(5)  
tAW  
OE  
tCW(3)  
CS  
tWP(2)  
tAS(4)  
WE  
tDH  
tDW  
High-Z  
Data in  
Data out  
Valid Data  
tOHZ(6)  
High-Z(8)  
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)  
tWC  
Address  
tAW  
tWR(5)  
tCW(3)  
CS  
tAS(4)  
tWP1(2)  
WE  
tDW  
tDH  
High-Z  
Data in  
Valid Data  
tWHZ(6)  
tOW  
(9)  
(10)  
High-Z(8)  
Data out  
Rev 2.0  
February 1998  
- 6 -  
Preliminary  
PRELIMINARY  
CMOS SRAM  
K6R1004V1B-C  
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)  
tWC  
Address  
tAW  
tWR(5)  
tCW(3)  
CS  
tWP(2)  
tAS(4)  
WE  
tDH  
tDW  
High-Z  
High-Z  
Data in  
Valid Data  
tLZ  
tWHZ(6)  
High-Z(8)  
High-Z  
Data out  
NOTES(WRITE CYCLE)  
1. All write cycle timing is referenced from the last valid address to the first transition address.  
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;  
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end  
of write.  
3. tCW is measured from the later of CS going low to end of write.  
4. tAS is measured from the address valid to the beginning of write.  
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.  
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase  
of the output must not be applied because bus contention can occur.  
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.  
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.  
9. Dout is the read data of the new address.  
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be  
applied.  
FUNCTIONAL DESCRIPTION  
CS  
WE  
X
OE  
X*  
H
Mode  
Not Select  
Output Disable  
Read  
I/O Pin  
High-Z  
High-Z  
DOUT  
Supply Current  
H
ISB, ISB1  
ICC  
L
H
L
H
L
ICC  
L
L
X
Write  
DIN  
ICC  
* X means Don¢t Care.  
Rev 2.0  
February 1998  
- 7 -  
Preliminary  
PRELIMINARY  
CMOS SRAM  
K6R1004V1B-C  
Units:millimeters/Inches  
PACKAGE DIMENSIONS  
32-SOJ-400  
#32  
#17  
9.40 ±0.25  
0.370 ±0.010  
11.18 ±0.12  
0.440 ±0.005  
+0.10  
-0.05  
0.20  
0.008 +0.004  
#1  
#16  
-0.002  
0.69  
MIN  
21.36  
0.841  
MAX  
0.027  
20.95 ±0.12  
0.825 ±0.005  
1.30  
0.051  
1.30  
0.051  
(
(
)
)
0.10  
0.004  
3.76  
0.148  
MAX  
MAX  
+0.10  
-0.05  
+0.10  
0.71  
0.43  
-0.05  
1.27  
0.050  
0.95  
0.0375  
0.028 +0.004  
(
)
+0.004  
-0.002  
0.017  
-0.002  
Rev 2.0  
February 1998  
- 8 -  

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