K6R1016V1C-TP150 [SAMSUNG]
Standard SRAM, 64KX16, 15ns, CMOS, PDSO44;型号: | K6R1016V1C-TP150 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 64KX16, 15ns, CMOS, PDSO44 静态存储器 光电二极管 |
文件: | 总11页 (文件大小:141K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev. No.
Rev. 0.0
Rev. 1.0
History
Remark
Preliminary
Final
Draft Data
Aug. 5. 1998
Sep. 7. 1998
Initial release with Preliminary.
Release to Final Data Sheet.
1.1. Delete Preliminary.
1.2. Changed DC characteristics.
Item
Previous
85mA
83mA
Changed
95mA
93mA
ICC
12ns
15ns
20ns
80mA
90mA
Rev. 2.0
Rev. 2.1
Added 48-fine pitch BGA.
Changed device part name for FP-BGA.
Sep. 17. 1998
Nov. 5. 1998
Final
Final
Item
Symbol
Previous
Changed
F
Z
ex) K6R1016V1C-Z -> K6R1016V1C-F
Rev. 2.2
Rev. 3.0
Changed device ball name for FP-BGA.
Dec. 10. 1998
Mar. 2. 1999
Final
Final
Previous
I/O1 ~ I/O8
I/O9 ~ I/O16
Changed
I/O9 ~ I/O16
I/O1 ~ I/O8
1. Added 10ns speed for FP-BGA only.
2. Changed Standby Current.
Item
Previous
0.3mA
Changed
0.5mA
Standby Current(Isb1)
3. Added Data Retention Characteristics.
Rev. 3.1
Rev. 3.2
Added 10ns speed for all packages(44SOJ / 44TSOP2 / 48FPBGA)
Apr. 24. 2000
Aug. 25. 2000
Final
Final
Supply Voltage Change
1. Only 10ns Bin : 3.15V ~ 3.6V
2. The Rest Bin : 3.0V ~ 3.6V
Rev. 3.3
VIH/VIL Change
Oct. 2. 2000
Final
Previous
Changed
Max
Item
Min
2.0
Max
Min
2.0
VIH
VIL
VCC+0.5
0.8
VCC+0.3
0.8
-0.5
-0.3
Rev. 4.0
Delete 20ns speed bin
Sep. 24. 2001
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. Ifyou have any questions,
please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision 4.0
- 1 -
September 2001
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 10,12,15ns(Max.)
• Low Power Dissipation
The K6R1016V1C is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits. The
K6R1016V1C uses 16 common input and output lines and has
at output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control (UB, LB). The device is fabricated
using SAMSUNG¢s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
K6R1016V1C is packaged in a 400mil 44-pin plastic SOJ or
TSOP2 forward or 48-Fine pitch BGA.
Standby (TTL)
:
30mA(Max.)
(CMOS) :
5mA(Max.)
0.5mA(Max.) L-ver. only
Operating * K6R1016V1C-10: 105mA(Max.)
K6R1016V1C-12: 95mA(Max.)
K6R1016V1C-15: 93mA(Max.)
• Single 3.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention: L-ver. only
• Center Power/Ground Pin Configuration
• Data Byte Control: LB: I/O1~ I/O8, UB: I/O9~ I/O16
• Standard Pin Configuration:
K6R1016V1C-J: 44-SOJ-400
K6R1016V1C-T: 44-TSOP2-400BF
K6R1016V1C-F: 48-Fine pitch BGA with 0.75 Ball pitch
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
K6R1016V1C-C10/C12/C15
Commercial Temp.
Industrial Temp.
Clk Gen.
Pre-Charge Circuit
K6R1016V1C-I10/I12/I15
A0
A1
A2
A3
A4
A5
A6
A7
A8
Memory Array
512 Rows
128x16 Columns
PIN FUNCTION
Pin Name
Pin Function
Address Inputs
Data
Cont.
I/O Circuit &
Column Select
I/O1~I/O8
A0 - A15
WE
Write Enable
Chip Select
Data
Cont.
I/O 9~I/O16
CS
Gen.
CLK
OE
Output Enable
A9 A10 A11 A12 A13 A14 A15
LB
Lower-byte Control(I/O1~I/O8)
Upper-byte Control(I/O9~I/O16)
Data Inputs/Outputs
Power(+3.3V)
UB
I/O1 ~ I/O16
VCC
WE
OE
VSS
Ground
UB
LB
N.C
No Connection
CS
Revision 4.0
September 2001
- 2 -
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
PIN CONFIGURATION(TOP VIEW)
1
2
3
4
5
6
A0
A1
1
2
3
4
5
6
7
8
9
44 A15
43 A14
42 A13
41 OE
40 UB
39 LB
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
CS
N.C
I/O9
A2
A3
I/O1
A4
CS
I/O1
I/O2
I/O3
I/O2
Vss
I/O3
I/O4
I/O5
I/O6
N.C
A8
A5
A6
I/O11
I/O12
I/O13
I/O14
WE
I/O10
Vcc
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 Vss
33 Vcc
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 N.C
27 A12
26 A11
25 A10
24 A9
N.C
N.C
A14
A12
A9
A7
I/O4 10
Vcc 11
Vss 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE 17
A5 18
SOJ/
Vcc
I/O7
I/O8
N.C
N.C
A15
A13
A10
Vss
TSOP2
I/O15
I/O16
N.C
G
H
A11
A6 19
A7 20
48-CSP
A8 21
N.C 22
23 N.C
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
Unit
V
-0.5 to 4.6
-0.5 to 4.6
1
V
Pd
W
Storage Temperature
TSTG
TA
-65 to 150
0 to 70
°C
°C
°C
Commercial
Operating Temperature
Industrial
TA
-40 to 85
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA= 0 to 70°C)
Parameter
Symbol
Min
3.15
3.0
Typ
3.3
3.3
0
Max
Unit
V
VCC(1)
VCC(2)
VSS
Supply Voltage
3.6
Supply Voltage
Ground
3.6
V
0
0
V
Input High Voltage
Input Low Voltage
(1) For K6R1016V1C-10 only.
VIH
2.0
-
VCC+0.3(3)
0.8
V
VIL
-0.3(4)
-
V
(2) For all speed grades except K6R1016V1C-10.
(3) VIH(Max) = VCC + 2.0V a.c(Pulse Width £ 8ns) for I £ 20mA
(4) VIL(Min) = -2.0V a.c(Pulse Width £ 8ns) for I £ 20mA.
Revision 4.0
- 3 -
September 2001
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
*DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3V+0.3V/-0.15V, unless otherwise specfied)
Parameter
Symbol
Test Conditions
VIN=VSS to VCC
Min
Max
Unit
Input Leakage Current
ILI
-2
2
mA
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
Output Leakage Current
Operating Current
ILO
-2
2
mA
ICC
Min. Cycle, 100% Duty
10ns
12ns
15ns
-
105
95
93
30
5
mA
CS=VIL, VIN = VIH or VIL, IOUT=0mA
-
-
Standby Current
ISB
mA
mA
Min. Cycle, CS =VIH
-
ISB1
Normal
L-Ver.
-
-
f=0MHz, CS ³ VCC-0.2V,
VIN³ VCC-0.2V or VIN £0.2V
0.5
0.4
-
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
-
V
V
IOH=-4mA
2.4
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
CI/O
Test Conditions
VI/O=0V
MIN
Max
Unit
Input/Output Capacitance
Input Capacitance
-
-
8
6
pF
pF
CIN
VIN=0V
* Capacitance is sampled and not 100% tested.
AC CHARACTERISTICS(TA=0 to 70°C, Vcc=3.3V+0.3V/-0.15V, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
0V to 3V
3ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
* The above test conditions are also applied at industrial temperature range.
Output Loads(B)
Output Loads(A)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+3.3V
RL = 50W
DOUT
319W
VL = 1.5V
DOUT
30pF*
ZO = 50W
353W
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
Revision 4.0
- 4 -
September 2001
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
READ CYCLE*
K6R1016V1C-10
K6R1016V1C-12
K6R1016V1C-15
Unit
Parameter
Symbol
Min
10
-
Max
Min
12
-
Max
Min
Max
Read Cycle Time
tRC
tAA
-
10
10
5
-
12
12
6
15
-
-
15
15
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tBA
-
-
-
Output Enable to Valid Output
UB, LB Access Time
-
-
-
-
5
-
6
-
7
Chip Enable to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
tLZ
3
0
0
0
0
0
3
0
-
-
3
0
0
0
0
0
3
0
-
-
3
0
0
-
-
tBLZ
tOLZ
tHZ
-
-
-
-
-
-
5
6
7
tOHZ
tBHZ
tOH
tPU
5
6
-
7
5
6
-
7
-
-
3
0
-
-
-
-
-
tPD
10
12
15
* The above parameters are also guaranteed at industrial temperature range.
WRITE CYCLE*
K6R1016V1C-10
K6R1016V1C-12
K6R1016V1C-15
Parameter
Symbol
Unit
Min
10
7
Max
Min
12
8
Max
Min
15
9
Max
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
-
5
-
-
-
-
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
-
7
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set-up Time
0
0
0
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
UB , LB Valid to End of Write
Write Recovery Time
tAW
tWP
tWP1
tBW
tWR
tWHZ
tDW
tDH
7
8
9
7
8
9
10
7
12
8
15
9
0
0
0
Write to Output High-Z
0
0
0
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
5
6
7
0
0
0
tOW
3
3
3
* The above parameters are also guaranteed at industrial temperature range.
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL
tRC
Address
tAA
tOH
Data Out
Valid Data
Previous Valid Data
Revision 4.0
- 5 -
September 2001
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tHZ(3,4,5)
tCO
CS
tBHZ(3,4,5)
tBA
UB, LB
tBLZ(4,5)
tOHZ
tOH
tOE
OE
tOLZ
tLZ(4,5)
Data out
High-Z
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CStransition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE=Clock)
tWC
tAW
Address
tWR(5)
OE
CS
tCW(3)
tBW
UB, LB
tAS(4)
WE
tWP(2)
tDW
tDH
High-Z
Data in
High-Z
Valid Data
tOHZ(6)
Data out
Revision 4.0
September 2001
- 6 -
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tBW
UB, LB
tWP1(2)
tAS(4)
WE
tDW
tDH
High-Z
Valid Data
Data in
(9)
(10)
tWHZ(6)
tOW
High-Z
Data out
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
CS
tAW
tWR(5)
tCW(3)
tBW
UB, LB
WE
tAS(4)
tWP(2)
tDW
tDH
High-Z
High-Z
High-Z
Data in
Data out
Valid Data
tLZ
tWHZ(6)
High-Z(8)
Revision 4.0
September 2001
- 7 -
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC
Address
tAW
tCW(3)
tWR(5)
CS
tBW
UB, LB
tAS(4)
tWP(2)
WE
tDW
tDH
High-Z
High-Z
Data in
Data out
Valid Data
tBLZ
tWHZ(6)
High-Z(8)
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE
going low; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write
to the end of write.
3. tCW is measured from the later of CSgoing low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tW R is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
I/O Pin
CS
WE
OE
LB
UB
Mode
Supply Current
I/O1~I/O8
High-Z
I/O9~I/O16
High-Z
H
L
L
L
X
H
X
H
X*
H
X
X
X
H
L
X
X
H
H
L
Not Select
ISB, ISB1
ICC
Output Disable
High-Z
High-Z
L
Read
Write
DOUT
High-Z
DOUT
DIN
High-Z
DOUT
DOUT
High-Z
DIN
ICC
ICC
H
L
L
L
L
X
L
H
L
H
L
High-Z
DIN
L
DIN
* X means Don¢t Care.
Revision 4.0
- 8 -
September 2001
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)
Parameter
VCC for Data Retention
Data Retention Current
Symbol
VDR
Test Condition
CS³ VCC-0.2V
Min.
2.0
-
Typ.
Max.
3.6
Unit
V
-
-
IDR
VCC=3.0V, CS³ VCC-0.2V
VIN³ VCC-0.2V or VIN£0.2V
0.4
mA
VCC=2.0V, CS³ VCC-0.2V
VIN³ VCC-0.2V or VIN£0.2V
-
-
0.3
Data Retention Set-Up Time
Recovery Time
tSDR
tRDR
See Data Retention
Wave form(below)
0
5
-
-
-
-
ns
ms
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-ver only.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0V
VIH
VDR
CS³ VCC - 0.2V
CS
GND
Revision 4.0
- 9 -
September 2001
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
Units:millimeters/Inches
PACKAGE DIMENSIONS
44-SOJ-400
#44
#23
9.40 ± 0.25
0.370 ± 0.010
11.18 ±0.12
0.440 ±0.005
+0.10
-0.05
0.20
+0.004
-0.002
0.008
#1
#22
28.98
MAX
0.69
MIN
0.027
1.141
25.58 ± 0.12
1.125 ±0.005
1.19
)
(
0.047
3.76
1.27
MAX
0.148
(
)
0.050
0.10
0.004
MAX
+0.10
- 0.05
0.43
+0.10
0.71 -0.05
0.95
0.0375
0.017+0.004
1.27
0.050
-0.002
(
)
0.028 +0.004
-0.002
44-TSOP2-400BF
Units:millimeters/Inches
0~8°
0.25
0.010
TYP
#23
#44
0.45 ~0.75
0.018 ~ 0.030
11.76 ±0.20
0.463 ± 0.008
0.50
0.020
(
)
#1
#22
18.81
0.741
MAX
0.125 + 0.075
- 0.035
18.41 ± 0.10
0.725± 0.004
0.005+ 0.003
- 0.001
1.00 ±0.10
1.20
0.047
MAX
0.039± 0.004
0.10
0.004
MAX
+ 0.10
- 0.05
+0.004
- 0.002
0.05
0.002
0.30
MIN
0.80
0.0315
0.805
0.032
(
)
0.012
Revision 4.0
September 2001
- 10
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
PACKAGE OUTLINE
(Units : millimeter)
Top View
Bottom View
B
A1 INDEX MARK
0.50
B1
B
0.50
6
5
4
3
2
1
A
B
#A1
C
D
E
F
G
H
B/2
Detail A
A
Side View
D
Y
C
Min
Typ
0.75
6.00
3.75
7.00
5.25
0.35
1.05
0.80
0.25
-
Max
-
A
B
-
Notes.
5.90
6.10
-
1. Bump counts: 48(8row x 6column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerance are +/-0.050 unless
otherwise specified.
B1
C
-
6.90
7.10
-
C1
D
-
4. Typ: Typical
0.30
0.40
1.20
-
5. Y is coplanarity: 0.08(Max)
E
-
E1
E2
Y
-
0.20
-
0.30
0.08
Revision 4.0
September 2001
- 11
相关型号:
K6R1016V1D
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges.
SAMSUNG
K6R1016V1D-EC08/10
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges.
SAMSUNG
K6R1016V1D-EC100
Standard SRAM, 64KX16, 10ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TBGA-48
SAMSUNG
K6R1016V1D-EI08/10
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges.
SAMSUNG
K6R1016V1D-EI100
Standard SRAM, 64KX16, 10ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TBGA-48
SAMSUNG
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