K6R4004C1D-J [SAMSUNG]
512Kx8 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges.; 512Kx8位高速静态RAM ( 3.3V工作) 。工作在商用和工业温度范围。型号: | K6R4004C1D-J |
厂家: | SAMSUNG |
描述: | 512Kx8 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges. |
文件: | 总10页 (文件大小:245K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
CMOS SRAM
K6R4008V1D
Document Title
512Kx8 Bit High Speed Static RAM(3.3V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
RevNo.
Rev. 0.0
Rev. 0.1
Rev. 0.2
History
Draft Data
Remark
Initial release with Preliminary.
Add Low Ver.
Aug. 20. 2001
Sep. 19. 2001
Nov. 3. 2001
Preliminary
Preliminary
Preliminary
Change Icc, Isb and Isb1
Item
8ns
Previous
110mA
90mA
Current
80mA
65mA
55mA
45mA
100mA
85mA
75mA
65mA
20mA
1.2mA
10ns
ICC(Commercial)
12ns
80mA
15ns
8ns
70mA
130mA
115mA
100mA
85mA
10ns
12ns
15ns
ISB
ICC(Industrial)
30mA
0.5mA
ISB1(L-ver.)
Rev. 0.3
Rev. 1.0
Nov.23. 2001
Dec.18. 2001
July. 26, 2004
Preliminary
Final
1. Correct AC parameters : Read & Write Cycle mA
2. Delete Low Ver.
3. Delete Data Retention Characteristics
1. Delete 12ns,15ns speed bin.
2. Change Icc for Industrial mode.
Item
Previous
100mA
85mA
Current
90mA
75mA
8ns
ICC(Industrial)
10ns
Final
1. Add the Lead Free Package type.
Rev. 2.0
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. 2.0
- 1 -
July 2004
PRELIMINARY
CMOS SRAM
K6R4008V1D
4Mb Async. Fast SRAM Ordering Information
Org.
Part Number
K6R4004C1D-J(K)C(I) 10
K6R4004V1D-J(K)C(I) 08/10
K6R4008C1D-J(K,T,U)C(I) 10
VDD(V)
Speed ( ns )
PKG
Temp. & Power
5
3.3
5
10
8/10
10
J : 32-SOJ
1M x4
K : 32-SOJ(LF) C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
,Normal Power Range
L : Commercial Temperature
,Low Power Range
P : Industrial Temperature
,Low Power Range
J : 36-SOJ
K : 36-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
512K x8
K6R4008V1D-J(K,T,U)C(I) 08/10
K6R4016C1D-J(K,T,U,E)C(I) 10
K6R4016V1D-J(K,T,U,E)C(I,L,P) 08/10
3.3
5
8/10
10
J : 44-SOJ
K : 44-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
E : 48-TBGA
256K x16
3.3
8/10
Rev. 2.0
- 2 -
July 2004
PRELIMINARY
CMOS SRAM
K6R4008V1D
512K x 8 Bit High-Speed CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 8,10ns(Max.)
• Low Power Dissipation
The K6R4008V1D is a 4,194,304-bit high-speed Static Random
Access Memory organized as 524,288 words by 8 bits. The
K6R4008V1D uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6R4008V1D is packaged
in a 400 mil 36-pin plastic SOJ and 44-pin plastic TSOP type II.
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6R4008V1D-08 : 80mA(Max.)
K6R4008V1D-10 : 65mA(Max.)
• Single 3.3 0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4008V1D-J : 36-SOJ-400
K6R4008V1D-K : 36-SOJ-400(Lead-Free)
K6R4008V1D-T : 44-TSOP2-400BF
K6R4008V1D-U : 44-TSOP2-400BF(Lead-Free)
• Operating in Commercial and Industrial Temperature range.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Memory Array
1024 Rows
512 x 8 Columns
Data
I/O Circuit
I/O1~I/O8
Cont.
Column Select
CLK
Gen.
A10 A11 A12 A13 A14 A15 A16 A17 A18
CS
WE
OE
Rev. 2.0
- 3 -
July 2004
PRELIMINARY
CMOS SRAM
K6R4008V1D
PIN CONFIGURATION (Top View)
N.C
N.C
A0
A1
A2
A3
A4
CS
I/O1
I/O2 10
Vcc 11
Vss 12
I/O3 13
I/O4 14
WE 15
A5 16
A6 17
A7 18
A8 19
A9 20
N.C 21
N.C 22
1
2
3
4
5
6
7
8
9
44 N.C
43 N.C
42 N.C
41 A18
40 A17
39 A16
38 A15
37 OE
36 I/O8
35 I/O7
34 Vss
33 Vcc
32 I/O6
31 I/O5
30 A14
29 A13
28 A12
27 A11
26 A10
25 N.C
24 N.C
23 N.C
A0
A1
1
2
3
4
5
6
7
8
9
36 N.C
35 A18
34 A17
33 A16
32 A15
31 OE
30 I/O8
29 I/O7
28 Vss
27 Vcc
26 I/O6
25 I/O5
24 A14
23 A13
22 A12
21 A11
20 A10
19 N.C
A2
A3
A4
CS
I/O1
I/O2
Vcc
36-SOJ
44-TSOP2
Vss 10
I/O3 11
I/O4 12
WE 13
A5 14
A6 15
A7 16
A8 17
A9 18
PIN FUNCTION
Pin Name
A0 - A18
WE
Pin Function
Address Inputs
Write Enable
Chip Select
CS
OE
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
I/O1 ~ I/O8
VCC
VSS
N.C
No Connection
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
Unit
V
V
PD
W
Storage Temperature
TSTG
TA
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Commercial
Industrial
TA
-40 to 85
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Rev. 2.0
- 4 -
July 2004
PRELIMINARY
CMOS SRAM
K6R4008V1D
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Parameter
Supply Voltage
Symbol
VCC
Min
3.0
Typ
Max
Unit
V
3.3
3.6
Ground
VSS
0
0
-
0
VCC+0.3***
0.8
V
Input High Voltage
Input Low Voltage
VIH
2.0
V
VIL
-0.3**
-
V
*
The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3 0.3V, unless otherwise specified)
Parameter
Symbol
ILI
Test Conditions
Min
-2
Max
2
Unit
µA
Input Leakage Current
Output Leakage Current
VIN=VSS to VCC
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
2
µA
Operating Current
Standby Current
ICC
Min. Cycle, 100% Duty
Com.
Ind.
8ns
10ns
8ns
-
-
-
-
-
-
80
65
90
75
20
5
mA
CS=VIL, VIN=VIH or VIL, IOUT=0mA
10ns
ISB
Min. Cycle, CS=VIH
mA
ISB1
f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
-
0.4
-
V
V
IOH=-4mA
2.4
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
CI/O
Test Conditions
TYP
-
-
Max
8
Unit
pF
pF
VI/O=0V
VIN=0V
CIN
6
* Capacitance is sampled and not 100% tested.
Rev. 2.0
- 5 -
July 2004
PRELIMINARY
CMOS SRAM
K6R4008V1D
AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3 0.3V, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
Input Pulse Levels
0V to 3V
3ns
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
*The above test conditions are also applied at industrial temperature range.
Output Loads(A)
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+3.3V
RL = 50Ω
DOUT
VL = 1.5V
30pF*
319Ω
DOUT
ZO = 50Ω
353Ω
5pF*
* Including Scope and Jig Capacitance
* Capacitive Load consists of all components of the
test environment.
READ CYCLE*
K6R4008V1D-08
K6R4008V1D-10
Parameter
Symbol
Unit
Min
8
-
Max
Min
10
-
Max
Read Cycle Time
tRC
tAA
-
8
8
4
-
-
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tLZ
-
-
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
-
-
3
0
0
0
3
0
-
3
-
tOLZ
tHZ
-
0
-
4
4
-
0
5
tOHZ
tOH
tPU
tPD
0
5
3
-
-
0
-
8
-
10
* The above parameters are also guaranteed at industrial temperature range.
Rev. 2.0
- 6 -
July 2004
PRELIMINARY
CMOS SRAM
K6R4008V1D
WRITE CYCLE*
K6R4008V1D-08
Max
K6R4008V1D-10
Max
Parameter
Symbol
Unit
Min
8
Min
10
7
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
4
-
-
-
-
-
-
-
-
-
-
5
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set-up Time
6
0
0
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
6
7
6
7
8
10
0
0
Write to Output High-Z
0
0
Data to Write Time Overlap
Data Hold from Write Time
End of Write to Output Low-Z
4
5
0
0
tOW
3
3
* The above parameters are also guaranteed at industrial temperature range.
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Valid Data
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tCO
tHZ(3,4,5)
CS
tOHZ
tDH
tOE
OE
tOLZ
tLZ(4,5)
Data out
High-Z
Valid Data
tPU
tPD
ICC
ISB
VCC
Current
50%
50%
NOTES(WRITE CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
Rev. 2.0
- 7 -
July 2004
PRELIMINARY
CMOS SRAM
K6R4008V1D
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
OE
tWR(5)
tAW
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
tDH
High-Z
Data in
Valid Data
tOHZ(6)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tWR(5)
tAW
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
tDH
High-Z
Data in
Valid Data
tWHZ(6)
tOW
(10)
(9)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP(2)
WE
tDH
tDW
High-Z
High-Z
High-Z
Data in
Data out
Valid Data
tLZ
tWHZ(6)
High-Z(8)
Rev. 2.0
- 8 -
July 2004
PRELIMINARY
CMOS SRAM
K6R4008V1D
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write
ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the
output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS
WE
OE
X*
H
Mode
Not Select
Output Disable
Read
I/O Pin
High-Z
High-Z
DOUT
Supply Current
H
X
ISB, ISB1
ICC
L
H
L
H
L
ICC
L
L
X
Write
DIN
ICC
* X means Don′t Care.
Rev. 2.0
July 2004
- 9 -
PRELIMINARY
CMOS SRAM
K6R4008V1D
Units:millimeters/Inches
PACKAGE DIMENSIONS
36-SOJ-400
#36
#19
9.40 0.25
11.18 0.12
0.440 0.005
0.370 0.010
+0.10
0.20
0.008
-0.05
+0.004
#1
#18
-0.002
0.69
MIN
0.027
23.90
0.941
MAX
23.50 0.12
0.925 0.005
1.19
0.047
1.27
(
(
)
)
3.76
0.148
0.10
MAX
MAX
0.004
0.050
+0.10
0.43
0.017
-0.05
+0.10
-0.05
+0.004
0.71
0.028
0.95
1.27
-0.002
(
)
+0.004
-0.002
0.0375
0.050
44-TSOP2-400BF
Units:millimeters/Inches
0~8°
0.25
TYP
0.010
#23
#44
0.45 ~0.75
0.018 ~ 0.030
11.76 0.20
0.463 0.008
0.50
(
)
0.020
#1
#22
18.81
MAX
+ 0.075
- 0.035
+ 0.003
- 0.001
0.125
0.005
0.741
18.41 0.10
0.725 0.004
1.00 0.10
1.20
0.047
MAX
0.039 0.004
0.10
MAX
+0.10
−0.05
0.05
0.004
0.30
0.012
MIN
0.002
0.80
0.0315
0.805
(
)
+0.004
0.032
−0.002
Rev. 2.0
- 10
July 2004
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