K6T1008V2E-RB700 [SAMSUNG]
Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 20 MM, REVERSE, TSOP1-32;
| 型号： | K6T1008V2E-RB700 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 20 MM, REVERSE, TSOP1-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K6T1008V2E, K6T1008U2E Family
CMOS SRAM
Document Title
128Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
1.0
Design target
September 9, 1998
April 13, 1998
Preliminary
Final
Finalize
- Change ICC1: 3 to 4mA
2.0
2.01
3.0
Revised
August 1, 2000
Final
Final
Final
- Add reverse package type from TSOP package.
Errata correction
- Removed T’ TL Compatible’from Features
October 24, 2001
November 6, 2001
Revised
- Added K6T1008V2E-YB55, K6T1008V2E-YF55 product.
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
CMOS SRAM
128Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: TFT
· Organization: 128Kx8
The K6T1008V2E and K6T1008U2E families are fabricated
by SAMSUNG¢s advanced CMOS process technology. The
families support various operating temperature ranges and
have various package types for user flexibility of system
design. The families also support low data retention voltage
for battery back-up operation with low data retention current.
· Power Supply Voltage
K6T1008V2E Family: 3.0V ~ 3.6V
K6T1008U2E Family: 2.7V ~ 3.3V
· Low Data Retention Voltage: 2V(Min)
· Three State Outputs
· Package Type: 32-SOP-525,
32-TSOP1-0820F/R, 32-TSOP1-0813.4F/R
PRODUCT FAMILY
Power Dissipation
Product Family Operating Temperature Vcc Range
Speed
PKG Type
Standby
(ISB1, Max)
Operating
(ICC2, Max)
551)/701)/100ns
701)/100ns
K6T1008V2E-B
K6T1008U2E-B
K6T1008V2E-F
K6T1008U2E-F
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
Commercial(0~70°C)
Industrial(-40~85°C)
32-SOP-525
32-TSOP1-0820F/R
32-TSOP1-0813.4F/R
10mA
30mA
551)/701)/100ns
701)/100ns
1. The parameters are tested with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A11
A9
1
2
3
4
5
6
7
8
32
OE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A8
Clk gen.
Precharge circuit.
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
VCC
A15
CS2
WE
NC
A16
A14
A12
A7
1
32
32-TSOP
32-STSOP
Type1-Forward
2
31
9
3
30
10
11
12
13
14
15
16
29
4
Memory array
1024 rows
128´ 8 columns
28
A13
A8
5
Row
select
A6
A5
A4
A1
A2
A3
27
6
A6
26
A9
A5
7
32-SOP 25
A11
OE
8
A4
16
17
A3
A2
A1
A0
A4
A5
A6
24
23
22
21
20
19
18
17
9
A3
15
14
13
12
11
10
9
8
7
6
5
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A2
10
11
12
13
14
15
16
A7
A1
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS1
A10
OE
A12
A14
A16
NC
VCC
A15
CS2
WE
A13
A8
A0
32-TSOP
I/O1
I/O2
I/O3
VSS
I/O1
I/O8
Data
cont
I/O Circuit
32-STSOP
Type1-Reverse
Column select
4
3
2
1
Data
cont
A9
A11
Name
A0~A16
WE
Function
Address Inputs
CS1
Control
logic
CS2
WE
Write Enable Input
Chip Select Input
Output Enable Input
Data Inputs/Outputs
Power
CS1,CS2
OE
OE
I/O1~I/O8
Vcc
Vss
Ground
NC
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Industrial Temperature Products(-40~85°C)
Part Name
Function
Part Name
Function
K6T1008V2E-GB70
K6T1008V2E-GB10
K6T1008V2E-TB70
K6T1008V2E-TB10
K6T1008V2E-RB70
K6T1008V2E-RB10
K6T1008V2E-YB55
K6T1008V2E-YB70
K6T1008V2E-YB10
K6T1008V2E-NB70
K6T1008V2E-NB10
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
K6T1008V2E-GF70
K6T1008V2E-GF10
K6T1008V2E-TF70
K6T1008V2E-TF10
K6T1008V2E-RF70
K6T1008V2E-RF10
K6T1008V2E-YF55
K6T1008V2E-YF70
K6T1008V2E-YF10
K6T1008V2E-NF70
K6T1008V2E-NF10
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP-F, 70ns, 3.3V
32-TSOP-F, 100ns, 3.3V
32-TSOP-R, 70ns, 3.3V
32-TSOP-R, 100ns, 3.3V
32-sTSOP-F, 55ns, 3.3V
32-sTSOP-F, 70ns, 3.3V
32-sTSOP-F, 100ns, 3.3V
32-sTSOP-R, 70ns, 3.3V
32-sTSOP-R, 100ns, 3.3V
32-TSOP-F, 70ns, 3.3V
32-TSOP-F, 100ns, 3.3V
32-TSOP-R, 70ns, 3.3V
32-TSOP-R, 100ns, 3.3V
32-sTSOP-F, 55ns, 3.3V
32-sTSOP-F, 70ns, 3.3V
32-sTSOP-F, 100ns, 3.3V
32-sTSOP-R, 70ns, 3.3V
32-sTSOP-R, 100ns, 3.3V
K6T1008U2E-GB70
K6T1008U2E-GB10
K6T1008U2E-TB70
K6T1008U2E-TB10
K6T1008U2E-RB70
K6T1008U2E-RB10
K6T1008U2E-YB70
K6T1008U2E-YB10
K6T1008U2E-NB70
K6T1008U2E-NB10
32-SOP, 70ns, 3.0V
32-SOP, 100ns, 3.0V
K6T1008U2E-GF70
K6T1008U2E-GF10
K6T1008U2E-TF70
K6T1008U2E-TF10
K6T1008U2E-RF70
K6T1008U2E-RF10
K6T1008U2E-YF70
K6T1008U2E-YF10
K6T1008U2E-NF70
K6T1008U2E-NF10
32-SOP, 70ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP-F, 70ns, 3.0V
32-TSOP-F, 100ns, 3.0V
32-TSOP-R, 70ns, 3.0V
32-TSOP-R, 100ns, 3.0V
32-sTSOP-F, 70ns, 3.0V
32-sTSOP-F, 100ns, 3.0V
32-sTSOP-R, 70ns, 3.0V
32-sTSOP-R, 100ns, 3.0V
32-TSOP-F, 70ns, 3.0V
32-TSOP-F, 100ns, 3.0V
32-TSOP-R, 70ns, 3.0V
32-TSOP-R, 100ns, 3.0V
32-sTSOP-F, 70ns, 3.0V
32-sTSOP-F, 100ns, 3.0V
32-sTSOP-R, 70ns, 3.0V
32-sTSOP-R, 100ns, 3.0V
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O
Mode
Power
Standby
Standby
Active
X1)
L
X1)
X1)
H
High-Z
High-Z
High-Z
Dout
Deselected
Deselected
Output Disabled
Read
X1)
L
X1)
H
X1)
H
H
H
H
L
L
L
H
L
Active
X1)
Din
Write
Active
1. X means don¢t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
VIN,VOUT
VCC
Ratings
Unit
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
-0.5 to VCC+0.5
-0.3 to 4.6
1.0
V
V
-
-
-
-
PD
W
°C
°C
°C
Storage temperature
TSTG
-65 to 150
0 to 70
K6T1008V2E-B, K6T1008U2E-B
K6T1008V2E-F, K6T1008U2E-F
Operating Temperature
TA
-40 to 85
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Product
Min
Typ
Max
Unit
K6T1008V2E Family
K6T1008U2E Family
3.0
2.7
3.3
3.0
3.6
3.3
Supply voltage
Vcc
V
Ground
Vss
VIH
VIL
All Family
0
0
-
0
V
V
V
Input high voltage
Input low voltage
Note:
K6T1008V2E, K6T1008U2E Family
K6T1008V2E, K6T1008U2E Family
2.2
Vcc+0.3
0.6
-0.33)
-
1. Commercial Product: TA=0 to 70°C, otherwise specified
Industrial Product: TA=-40 to 85°C, otherwise specified
2. Overshoot: Vcc+2.0V in case of pulse width£30ns
3. Undershoot: -2.0V in case of pulse width£30ns
4. Overshoot and undershoot are sampled, not 100% tested.
1
)
CAPACITANCE (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
Test Condition
VIN=0V
Min
Max
Unit
CIN
CIO
-
-
8
pF
pF
Input/Output capacitance
VIO=0V
10
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
VIN=Vss to Vcc
-1
-1
-
-
-
-
1
1
4
mA
mA
Output leakage current
Operating power supply current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read
ICC
mA
Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V, CS2³ Vcc-0.2V,
VIN£0.2V or VIN³ VCC-0.2V
ICC1
ICC2
-
-
-
4
mA
Average operating current
Cycle time=70ns, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH,
VIN=VIH or VIL
25
30 mA
Output low voltage
VOL
VOH
ISB
IOL=2.1mA
-
2.4
-
-
-
-
0.4
-
V
V
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
IOH=-1.0mA
CS1=VIH, CS2=VIL, Other inputs = VIH or VIL
CS1³ Vcc-0.2V, CS2³ Vcc-0.2V or CS2£0.2V, Other inputs=0~Vcc
0.3 mA
ISB1
-
0.2 10 mA
4
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
1)
CL
Input and output reference voltage: 1.5V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS (K6T1008V2E Family: VCC=3.0~3.6V, K6T1008U2E Family: VCC=2.7~3.3V
Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
55ns
70ns
100ns
Min
55
-
Max
Min
70
-
Max
Min
Max
Read cycle time
tRC
tAA
-
55
55
25
-
-
70
70
35
-
100
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
100
Chip select to output
tCO1, tCO2
tOE
-
-
-
100
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
-
-
-
50
-
Read
tLZ
10
5
10
5
10
5
tOLZ
tHZ
-
-
-
0
25
25
-
0
25
25
-
0
30
30
-
tOHZ
tOH
0
0
0
10
55
45
0
10
70
60
0
15
100
80
0
tWC
tCW
tAS
-
-
-
Chip select to end of write
Address set-up time
-
-
-
-
-
-
Address valid to end of write
Write pulse width
tAW
45
40
0
-
60
55
0
-
80
70
0
-
tWP
-
-
-
Write
Write recovery time
tWR
tWHZ
tDW
tDH
-
-
-
Write to output high-Z
0
25
-
0
25
-
0
30
-
Data to write time overlap
Data hold from write time
End write to output low-Z
20
0
30
0
40
0
-
-
-
tOW
5
-
5
-
5
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
VDR
Test Condition
Min
2.0
-
Typ
Max
Unit
V
CS1³ Vcc-0.2V1)
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
-
0.2
-
3.6
10
-
Vcc=3.0V, CS1³ Vcc-0.2V1)
IDR
mA
tSDR
0
See data retention waveform
ms
tRDR
5
-
-
1. CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or CS2£0.2V(CS2 controlled)
5
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tWR(4)
tCW(2)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
CS1
tCW(2)
tAS(3)
tWR(4)
tAW
CS2
tWP(1)
WE
tDW
tDH
Data in
Data out
Data Valid
High-Z
High-Z
7
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
CS1
tAS(3)
tCW(2)
tWR(4)
tAW
CS2
tCW(2)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR is applied in case a write ends with CS1 or WE going high .
tWR2 is applied in case a write ends with CS2 going low.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0/2.7V1)
2.2V
VDR
CS³ VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
3.0/2.7V1)
CS2
tSDR
tRDR
VDR
CS2£0.2V
0.4V
GND
1. 3.0V for K6T1008V2E Family, 2.7V for K6T1008U2E Family
8
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#32
#17
14.12±0.30
0.556±0.012
11.43±0.20
0.450±0.008
#1
#16
0.80±0.20
0.031±0.008
+0.10
0.20
-0.05
2.74±0.20
20.87
0.822
MAX
0.108±0.008
+0.004
-0.002
0.008
3.00
MAX
0.118
20.47±0.20
0.806±0.008
0.10 MAX
0.004 MAX
+0.100
-0.050
0.41
0.71
0.028
1.27
0.050
+0.004
-0.002
0.05
0.002
(
)
0.016
MIN
9
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
CMOS SRAM
Units: millimeter(inch)
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
13.40±0.20
0.528±0.008
+0.10
-0.05
+0.004
-0.002
0.20
0.008
#1
#32
0.25
0.010
(
)
0.50
0.0197
#16
#17
1.00±0.10
0.039±0.004
0.25
0.010
0.05
0.002
MIN
TYP
11.80±0.10
0.465±0.004
+0.10
-0.05
+0.004
-0.002
0.15
1.20
MAX
0.047
0.006
0~8°
0.50
0.020
0.45~0.75
0.018~0.030
(
)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)
13.40±0.20
0.528±0.008
+0.10
-0.05
+0.004
-0.002
0.20
0.008
#16
#17
0.25
0.010
(
)
0.50
0.0197
#1
#32
1.00±0.10
0.039±0.004
0.25
0.010
0.05
0.002
TYP
11.80±0.10
0.465±0.004
MIN
+0.10
-0.05
+0.004
-0.002
0.15
1.20
MAX
0.047
0.006
0~8°
0.50
0.020
0.45~0.75
0.018~0.030
(
)
10
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
CMOS SRAM
Units: millimeter(inch)
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
+0.10
-0.05
+0.004
20.00±0.20
0.787±0.008
0.20
0.008
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#17
#16
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
18.40±0.10
0.724±0.004
TYP
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820R)
+0.10
-0.05
20.00±0.20
0.787±0.008
0.20
+0.004
-0.002
0.008
#16
#17
0.25
0.010
(
)
0.50
0.0197
#1
#32
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
18.40±0.10
0.724±0.004
0.25
0.010
TYP
+0.10
-0.05
0.15
+0.004
-0.002
0.006
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
11
Revision 3.0
November 2001
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