K6X8008C2B [SAMSUNG]

1Mx8 bit Low Power and Low Voltage CMOS Static RAM; 1Mx8位低功耗和低电压CMOS静态RAM


型号：	K6X8008C2B
厂家：	SAMSUNG
描述：	1Mx8 bit Low Power and Low Voltage CMOS Static RAM 1Mx8位低功耗和低电压CMOS静态RAM
文件：	总9页 (文件大小：133K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K6X8008C2B Family

CMOS SRAM

Document Title

1Mx8 bit Low Power and Low Voltage CMOS Static RAM

Revision History

Revision No. History

Draft Date

Remark

0.0

Initial draft

October 31, 2002

Preliminary

0.1

Revised

December 11, 2002 Preliminary

September 16, 2003 Final

- Deleted 44-TSOP2-400R package type.

- Added Commercial product.

1.0

Finalized

- Changed ICC from 10mA to 6mA

- Changed ICC1 from 10mA to 7mA

- Changed ICC2 from 50mA to 35mA

- Changed ISB from 3mA to 0.4mA

- Changed ISB1(Commercial) from 40mA to 25mA

- Changed ISB1(industrial) from 40mA to 25mA

- Changed ISB1(Automotive) from 50mA to 40mA

- Changed IDR(Commercial) from 30mA to 15mA

- Changed IDR(industrial) from 30mA to 15mA

- Changed IDR(Automotive) from 40mA to 30mA

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 1.0

September 2003

K6X8008C2B Family

CMOS SRAM

1Mx8 bit Low Power full CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology: Full CMOS

· Organization: 1M x8

The K6X8008C2B families are fabricated by SAMSUNG¢s

advanced full CMOS process technology. The families sup-

port various operating temperature range for user flexibility of

system design. The families also support low data retention

voltage for battery back-up operation with low data retention

current.

· Power Supply Voltage: 4.5~5.5V

· Low Data Retention Voltage: 2.0V(Min)

· Three state output and TTL Compatible

· Package Type: 44-TSOP2-400F

PRODUCT FAMILY

Power Dissipation

Product Family

Operating Temperature

Vcc Range

Speed

PKG Type

Standby

(ISB1, Max)

Operating

(ICC2, Max)

K6X8008C2B-B

K6X8008C2B-F

K6X8008C2B-Q

Commercial(0~70°C)

Industrial(-40~85°C)

Automotive(-40~125°C)

25mA

40mA

4.5~5.5V

55¹⁾/70ns

35mA

44-TSOP2-400F

1. The parameter is measured with 50pF test load.

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

Clk gen.

Precharge circuit.

CS2

Vcc

Vss

CS1

Row

Addresses

Memory array

Row

select

I/O1

I/O2

Vcc

Vss

I/O3

I/O4

I/O8

I/O7

Vss

Vcc

I/O6

I/O5

44-TSOP2

Forward

Data

cont

I/O Circuit

Column select

A19

A18

A17

A16

A15

I/O1~I/O8

A10

A11

A12

A13

A14

Data

cont

Column Addresses

Name

Function

Name

Vcc

Function

CS1, CS2 Chip Select Inputs

Power

Ground

CS1

CS2

Output Enable Input

Write Enable Input

Vss

A0~A19 Address Inputs

NC No Connect

Control Logic

I/O1~I/O8 Data Inputs/Outputs

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 1.0

September 2003

K6X8008C2B Family

CMOS SRAM

PRODUCT LIST

Commercial Products(0~70°C)

Industrial Products(-40~85°C)

Automotive Products(-40~125°C)

Part Name

Function

Part Name

Function

Part Name

Function

K6X8008C2B-TB55

K6X8008C2B-TB70

44-TSOP2-F, 55ns, LL

44-TSOP2-F, 70ns, LL

K6X8008C2B-TF55

K6X8008C2B-TF70

44-TSOP2-F, 55ns, LL

44-TSOP2-F, 70ns, LL

K6X8008C2B-TQ55

K6X8008C2B-TQ70

44-TSOP2-F, 55ns, L

44-TSOP2-F, 70ns, L

FUNCTIONAL DESCRIPTION

CS1

CS2

I/O1~8

Mode

Power

Standby

Active

High-Z

Dout

Deselected

Output Disabled

Read

Active

Din

Write

Active

Note: X means don¢t care. (Must be low or high state)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

Ratings

Unit

Remark

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

VIN, VOUT

VCC

-0.5 to VCC+0.5V(max.7.0V)

-0.3 to 7.0

1.0

°C

Storage temperature

TSTG

-65 to 150

0 to 70

K6X8008C2B-B

K6X8008C2B-F

K6X8008C2B-Q

Operating Temperature

-40 to 85

-40 to 125

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 1.0

September 2003

K6X8008C2B Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Supply voltage

Ground

Symbol

Vcc

Product

Min

4.5

Typ

Max

5.5

Unit

K6X8008C2B Family

All Family

5.0

Vss

Vcc+0.5²⁾

0.8

Input high voltage

Input low voltage

Note:

VIH

K6X8008C2B Family

2.2

-0.5³⁾

VIL

1. Commercial Product: TA=0 to 70°C, otherwise specified.

Industrial Product: TA=-40 to 85°C, otherwise specified.

Automotive Product: TA=-40 to 125°C, otherwise specified.

2. Overshoot: VCC+3.0V in case of pulse width £30ns.

3. Undershoot: -3.0V in case of pulse width £30ns.

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested.

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Test Conditions

Min Typ Max Unit

Input leakage current

VIN=Vss to Vcc

-1

Output leakage current

Operating power supply current

ILO

CS1=VIH, CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS1=VIL, CS2=VIH, WE=VIH, VIN=VIH or VIL

ICC

Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V,

CS2³ Vcc-0.2V, VIN£0.2V or VIN³ VCC-0.2V

ICC1

ICC2

Average operating current

Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH,

VIN=VIL or VIH

35 mA

Output low voltage

Output high voltage

Standby Current(TTL)

VOL

VOH

ISB

IOL = 2.1mA

2.4

0.4

IOH = -1.0mA

CS1=VIH, CS2=VIL, Other inputs=VIH or VIL

0.4 mA

K6X8008C2B-B

Other input =0~Vcc,

Standby Current(CMOS)

ISB1

1) CS1³ Vcc-0.2V, CS2³ Vcc-0.2V (CS1 con-

trolled) or 2) 0V£CS2£0.2V(CS2 controlled)

K6X8008C2B-F

K6X8008C2B-Q

Revision 1.0

September 2003

K6X8008C2B Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Input/Output Reference)

Input pulse level: 0.8 to 2.4V

Input rising and falling time: 5ns

)

Input and output reference voltage: 1.5V

Output load(see right): CL=100pF+1TTL

CL=50pF+1TTL

1.Including scope and jig capacitance

AC CHARACTERISTICS

(VCC=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40 to 125°C)

Speed Bins

Parameter List

Symbol

Units

55ns

70ns

Min

Max

Min

Max

Read Cycle Time

tRC

tAA

Address Access Time

Chip Select to Output

tCO

tOE

tLZ

Output Enable to Valid Output

Chip Select to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

Write Cycle Time

Read

tOLZ

tHZ

tOHZ

tOH

tWC

tCW

tAS

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width

tAW

tWP

tWR

tWHZ

tDW

tDH

tOW

Write

Write Recovery Time

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

DATA RETENTION CHARACTERISTICS

Item

Symbol

Test Condition

Min

Typ

Max

Unit

CS1³ Vcc-0.2V¹⁾

Vcc for data retention

VDR

2.0

5.5

K6X8008C2B-B

K6X8008C2B-F

K6X8008C2B-Q

Vcc=3.0V, CS1³ Vcc-0.2V¹⁾

Data retention current

IDR

Data retention set-up time

Recovery time

tSDR

tRDR

See data retention waveform

1. CS¹³ Vcc-0.2V,CS2³ Vcc-0.2V(CS1 controlled) or CS2³ Vcc-0.2V(CS2 controlled).

Revision 1.0

September 2003

K6X8008C2B Family

CMOS SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS¹=OE=VIL, CS2=WE=VIH)

tRC

Address

tAA

tOH

Data Out

Data Valid

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO1

CS1

tHZ(1,2)

CS2

tCO2

tOE

tOHZ

tOLZ

tLZ

High-Z

Data out

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 1.0

September 2003

K6X8008C2B Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tWR(4)

tCW(2)

CS1

tAW

CS2

tCW(2)

tWP(1)

tAS(3)

tDW

tDH

Data Valid

Data in

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)

tWC

Address

CS1

tCW(2)

tAS(3)

tWR(4)

tAW

CS2

tWP(1)

tDW

tDH

Data in

Data out

Data Valid

High-Z

Revision 1.0

September 2003

K6X8008C2B Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

tWC

Address

CS1

tAS(3)

tCW(2)

tWR(4)

tAW

CS2

tCW(2)

tWP(1)

tDH

tDW

Data Valid

Data in

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,

CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,

tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS¹going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS¹or WE going high tWR2 applied

in case a write ends as CS2 going to low.

DATA RETENTION WAVE FORM

CS1 controlled

Data Retention Mode

tSDR

tRDR

VCC

4.5V

2.2V

VDR

CS1³ VCC - 0.2V

CS1

GND

CS2 controlled

Data Retention Mode

VCC

4.5V

CS2

tSDR

tRDR

VDR

CS2£0.2V

0.4V

GND

Revision 1.0

September 2003

K6X8008C2B Family

CMOS SRAM

PACKAGE DIMENSIONS

Unit: millimeters(inches)

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

0~8°

0.25

0.010

(

)

#44

#23

0.45 ~0.75

0.018 ~ 0.030

11.76±0.20

0.463±0.008

0.50

0.020

(

)

#22

1.00±0.10

0.039±0.004

18.81

0.741

1.20

0.047

MAX.

18.41±0.10

0.725±0.004

0.10

0.004

MAX

0.35± 0.10

0.014±0.004

0.80

0.0315

0.805

0.032

(

)

Revision 1.0

September 2003

K6X8008C2B [SAMSUNG]

相关型号：

K6X8008C2B-B

K6X8008C2B-F

K6X8008C2B-Q

K6X8008C2B-TB55

K6X8008C2B-TB550

K6X8008C2B-TB70

K6X8008C2B-TB700

K6X8008C2B-TF55

K6X8008C2B-TF70

K6X8008C2B-TF700

K6X8008C2B-TF70T

K6X8008C2B-TQ55