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K7A161800A-QI20 [SAMSUNG]

Cache SRAM, 1MX18, 3.1ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100;
K7A161800A-QI20
型号： K7A161800A-QI20
厂家： SAMSUNG    SAMSUNG
描述：

Cache SRAM, 1MX18, 3.1ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100

时钟 静态存储器 内存集成电路
文件： 总28页 (文件大小：699K)
中文：  中文翻译
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K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
Document Title  
512Kx36/x32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM  
Revision History  
Rev. No.  
History  
Draft Date  
Remark  
0.0  
0.1  
0.2  
Initial draft  
1. Add JTAG Scan Order  
1. Add x32 org and industrial temperature .  
2. Add 165FBGA package  
1. Speed Bin Merge  
Feb. 23. 2001  
May. 10. 2001 Preliminary  
Aug. 31. 2001  
Dec. 26. 2001  
Preliminary  
Preliminary  
Preliminary  
0.3  
From K7A1636(32/18)09A to K7A1636(32/18)00A  
2. AC parameter change  
tOH(min)/tHZC(min) from 0.8 to 1.5 at -25  
tOH(min)/tHZC(min) from 1.0 to 1.5 at -22  
tOH(min)/tHZC(min) from 1.0 to 1.5 at -20  
1.0  
2.0  
1. Final spec release  
May. 10. 2002 Final  
May. 22. 2002 Final  
1. Release Icc.  
part #  
-25  
From  
440  
400  
370  
340  
280  
To  
470  
430  
400  
350  
290  
-22  
-20  
-16  
-14  
- 1 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
16Mb SB/SPB Synchronous SRAM Ordering Information  
Speed  
Org.  
Part Number  
Mode  
VDD  
SB ; Access Time(ns)  
SPB ; Cycle Time(MHz)  
PKG  
Temp  
K7B161825A-Q(H/F)C(I)65/75/85  
K7A161880A-QC(I)14  
SB  
3.3  
1.8  
3.3  
3.3  
3.3  
1.8  
3.3  
3.3  
3.3  
1.8  
3.3  
3.3  
6.5/7.5/8.5ns  
138MHz  
SPB(2E1D)  
1Mx18  
K7A161800A-Q(H/F)C(I)25/22/20/16/14 SPB(2E1D)  
250/225/200/167/138MHz  
250/225/200/167/138MHz  
6.5/7.5/8.5ns  
C
(Commercial  
Temperature  
Range)  
K7A161801A-QC(I)25/22/20/16/14  
K7B163225A-QC(I)65/75/85  
K7A163280A-QC(I)14  
SPB(2E2D)  
SB  
Q : 100TQFP  
H : 119BGA  
F : 165FBGA  
SPB(2E1D)  
SPB(2E1D)  
SPB(2E2D)  
SB  
138MHz  
512Kx32  
512Kx36  
K7A163200A-QC(I)25/22/20/16/14  
K7A163201A-QC(I)25/22/20/16/14  
K7B163625A-Q(H/F)C(I)65/75/85  
K7A163680A-QC(I)14  
250/225/200/167/138MHz  
250/225/200/167/138MHz  
6.5/7.5/8.5ns  
I
(Industrial  
Temperature  
Range)  
SPB(2E1D)  
138MHz  
K7A163600A-Q(H/F)C(I)25/22/20/16/14 SPB(2E1D)  
K7A163601A-QC(I)25/22/20/16/14 SPB(2E2D)  
250/225/200/167/138MHz  
250/225/200/167/138MHz  
- 2 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
512Kx36/x32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM  
FEATURES  
GENERAL DESCRIPTION  
• Synchronous Operation.  
• 2 Stage Pipelined operation with 4 Burst.  
• On-Chip Address Counter.  
The K7A163600A , K7A163200A and K7A161800A are  
18,874,368-bit Synchronous Static Random Access Mem-  
ory designed for high performance second level cache of  
Pentium and Power PC based System.  
• Self-Timed Write Cycle.  
• On-Chip Address and Control Registers.  
• VDD= 3.3V +0.165V/-0.165V Power Supply.  
• I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O  
or 2.5V+0.4V/-0.125V for 2.5V I/O.  
• 5V Tolerant Inputs Except I/O Pins.  
• Byte Writable Function.  
• Global Write Enable Controls a full bus-width write.  
• Power Down State via ZZ Signal.  
• LBO Pin allows a choice of either a interleaved burst or a linear  
burst.  
It is organized as 512K(1M) words of 36(32/18) bits and  
integrates address and control registers, a 2-bit burst  
address counter and added some new functions for high  
performance cache RAM applications; GW, BW, LBO, ZZ.  
Write cycles are internally self-timed and synchronous.  
Full bus-width write is done by GW, and each byte write is  
performed by the combination of WEx and BW when GW is  
high. And with CS1 high, ADSP is blocked to control sig-  
nals.  
• Three Chip Enables for simple depth expansion with No Data Con-  
tention only for TQFP ; 2cycle Enable, 1cycle Disable.  
• Asynchronous Output Enable Control.  
• ADSP, ADSC, ADV Burst Control Pins.  
• TTL-Level Three-State Output.  
• 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package)  
• 165FBGA(11x15 ball aray) with body size of 13mmx15mm.  
• Operating in commeical and industrial temperature range.  
Burst cycle can be initiated with either the address status  
processor (ADSP) or address status cache controller  
(ADSC) inputs. Subsequent burst addresses are generated  
internally in the system¢s burst sequence and are con-  
trolled by the burst address advance(ADV) input.  
LBO pin is DC operated and determines burst sequence  
(linear or interleaved).  
ZZ pin controls Power Down State and reduces Stand-by  
current regardless of CLK.  
FAST ACCESS TIMES  
The K7A163600A , K7A163200A and K7A161800A are  
fabricated using SAMSUNG¢s high performance CMOS  
technology and is available in a 100pin TQFP, 119BGA  
and 165FBGA package. Multiple power and ground pins  
are utilized to minimize ground bounce.  
PARAMETER  
Cycle Time  
Symbol -25 -22 -20 -16 -14 Unit  
tCYC  
tCD  
4.0  
2.6  
2.6  
4.4  
2.8  
2.8  
5.0 6.0 7.2  
3.1 3.5 4.0  
3.1 3.5 4.0  
ns  
ns  
ns  
Clock Access Time  
Output Enable Access Time  
tOE  
LOGIC BLOCK DIAGRAM  
CLK  
LBO  
512Kx36/32 , 1Mx18  
BURST CONTROL  
LOGIC  
BURST  
MEMORY  
ADDRESS  
COUNTER  
ADV  
ADSC  
A¢0~A¢1  
ARRAY  
A0~A1  
A2~A18  
or A2~A19  
A
0
~A18  
ADDRESS  
REGISTER  
or A  
0~A19  
ADSP  
DATA-IN  
REGISTER  
CS  
CS  
CS  
1
2
2
GW  
BW  
OUTPUT  
REGISTER  
CONTROL  
LOGIC  
BUFFER  
WEx  
(x=a,b,c,d or a,b)  
OE  
ZZ  
DQa  
0
~ DQd  
7
or DQa0 ~ DQb7  
DQPa,DQPb  
DQPa ~ DQPd  
- 3 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
PIN CONFIGURATION(TOP VIEW)  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQPb/NC  
DQb7  
DQb6  
VDDQ  
VSSQ  
DQb5  
DQb4  
DQb3  
DQb2  
VSSQ  
VDDQ  
DQb1  
DQb0  
VSS  
NC/DQPc  
DQc0  
DQc1  
VDDQ  
VSSQ  
DQc2  
DQc3  
DQc4  
DQc5  
VSSQ  
VDDQ  
DQc6  
DQc7  
N.C.  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
100 Pin TQFP  
N.C.  
VDD  
ZZ  
VDD  
N.C.  
VSS  
(20mm x 14mm)  
DQd0  
DQd1  
VDDQ  
VSSQ  
DQd2  
DQd3  
DQd4  
DQd5  
VSSQ  
VDDQ  
DQd6  
DQd7  
NC/DQPd  
DQa7  
DQa6  
VDDQ  
VSSQ  
DQa5  
DQa4  
DQa3  
DQa2  
VSSQ  
VDDQ  
DQa1  
DQa0  
DQPa/NC  
K7A163600A(512Kx36)  
K7A163200A(512Kx32)  
PIN NAME  
SYMBOL  
PIN NAME  
TQFP PIN NO.  
SYMBOL  
PIN NAME  
TQFP PIN NO.  
A0 - A18  
Address Inputs  
32,33,34,35,36,37,42 VDD  
43,44,45,46,47,48,49 VSS  
50,81,82,99,100  
Power Supply(+3.3V) 15,41,65,91  
Ground  
17,40,67,90  
ADV  
ADSP  
ADSC  
CLK  
CS1  
CS2  
Burst Address Advance  
Address Status Processor 84  
Address Status Controller 85  
83  
No Connect  
14,16,38,39,66  
N.C.  
Data Inputs/Outputs  
52,53,56,57,58,59,62,63  
68,69,72,73,74,75,78,79  
2,3,6,7,8,9,12,13  
18,19,22,23,24,25,28,29  
51,80,1,30  
DQa0~a7  
DQb0~b7  
DQc0~c7  
DQd0~d7  
DQPa~Pd  
or N.C  
Clock  
89  
98  
97  
92  
Chip Select  
Chip Select  
Chip Select  
CS2  
WEx(x=a,b,c,d) Byte Write Inputs  
93,94,95,96  
OE  
Output Enable  
86  
88  
87  
64  
31  
VDDQ  
VSSQ  
GW  
BW  
ZZ  
Global Write Enable  
Byte Write Enable  
Power Down Input  
Burst Mode Control  
Output Power Supply 4,11,20,27,54,61,70,77  
(3.3V or 2.5V)  
Output Ground  
5,10,21,26,55,60,71,76  
LBO  
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.  
- 4 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
PIN CONFIGURATION(TOP VIEW)  
A10  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
N.C.  
N.C.  
N.C.  
VDDQ  
VSSQ  
N.C.  
1
2
3
4
5
6
7
8
N.C.  
N.C.  
VDDQ  
VSSQ  
N.C.  
DQPa  
DQa7  
DQa6  
VSSQ  
VDDQ  
DQa5  
DQa4  
VSS  
N.C.  
DQb0  
DQb1  
VSSQ  
VDDQ  
DQb2  
DQb3  
N.C.  
VDD  
N.C.  
VSS  
DQb4  
DQb5  
VDDQ  
VSSQ  
DQb6  
DQb7  
DQPb  
N.C.  
VSSQ  
VDDQ  
N.C.  
N.C.  
N.C.  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
100 Pin TQFP  
(20mm x 14mm)  
N.C.  
VDD  
ZZ  
DQa3  
DQa2  
VDDQ  
VSSQ  
DQa1  
DQa0  
N.C.  
N.C.  
VSSQ  
VDDQ  
N.C.  
N.C.  
N.C.  
K7A161800A(1Mx18)  
PIN NAME  
SYMBOL  
PIN NAME  
TQFP PIN NO.  
SYMBOL  
PIN NAME  
TQFP PIN NO.  
A0 - A19  
Address Inputs  
32,33,34,35,36,37,42 VDD  
43,44,45,46,47,48,49 VSS  
50 80,81,82,99,100  
Power Supply(+3.3V) 15,41,65,91  
Ground  
17,40,67,90  
ADV  
ADSP  
ADSC  
CLK  
CS1  
Burst Address Advance  
Address Status Processor 84  
Address Status Controller  
Clock  
Chip Select  
83  
No Connect  
1,2,3,6,7,14,16,25,28,29  
30,38,39,51,52,53,56,57  
66,75,78,79,95,96  
N.C.  
85  
89  
98  
97  
Data Inputs/Outputs  
58,59,62,63,68,69,72,73  
8,9,12,13,18,19,22,23  
74,24  
DQa0 ~ a7  
DQb0 ~ b7  
DQPa, Pb  
CS2  
CS2  
Chip Select  
Chip Select  
92  
WEx(x=a,b) Byte Write Inputs  
93,94  
86  
OE  
Output Enable  
Output Power Supply 4,11,20,27,54,61,70,77  
(3.3V or 2.5V)  
VDDQ  
VSSQ  
GW  
BW  
ZZ  
Global Write Enable  
Byte Write Enable  
Power Down Input  
Burst Mode Control  
88  
87  
64  
31  
Output Ground  
5,10,21,26,55,60,71,76  
LBO  
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.  
- 5 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)  
K7A163600A(512Kx36)  
1
2
A
3
A
4
ADSP  
ADSC  
VDD  
NC  
5
6
A
7
A
B
C
D
E
F
VDDQ  
NC  
A
VDDQ  
NC  
A
A
A
A
NC  
A
A
A
A
NC  
DQc  
DQc  
VDDQ  
DQc  
DQc  
VDDQ  
DQd  
DQd  
VDDQ  
DQd  
DQd  
NC  
DQPc  
DQc  
DQc  
DQc  
DQc  
VDD  
DQd  
DQd  
DQd  
DQd  
DQPd  
A
VSS  
VSS  
VSS  
WEc  
VSS  
NC  
VSS  
WEd  
VSS  
VSS  
VSS  
LBO  
A
VSS  
VSS  
VSS  
WEb  
VSS  
NC  
VSS  
WEa  
VSS  
VSS  
VSS  
NC  
A
DQPb  
DQb  
DQb  
DQb  
DQb  
VDD  
DQa  
DQa  
DQa  
DQa  
DQPa  
A
DQb  
DQb  
VDDQ  
DQb  
DQb  
VDDQ  
DQa  
DQa  
VDDQ  
DQa  
DQa  
NC  
CS1  
OE  
G
H
J
ADV  
GW  
VDD  
CLK  
NC  
K
L
M
N
P
R
T
BW  
A1*  
A0*  
VDD  
A
NC  
NC  
NC  
ZZ  
U
VDDQ  
TMS  
TDI  
TCK  
TDO  
NC  
VDDQ  
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.  
PIN NAME  
SYMBOL  
PIN NAME  
SYMBOL  
PIN NAME  
Power Supply(+3.3V)  
A
Address Inputs  
VDD  
VSS  
A0, A1  
Burst Count Address  
Ground  
ADV  
Burst Address Advance  
Address Status Processor  
Address Status Controller  
Clock  
Chip Select  
Byte Write Inputs  
N.C.  
No Connect  
ADSP  
ADSC  
CLK  
CS1  
WEx  
DQa  
DQb  
DQc  
DQd  
Data Inputs/Outputs  
Data Inputs/Outputs  
Data Inputs/Outputs  
Data Inputs/Outputs  
Data Inputs/Outpus  
(x=a,b,c,d)  
DQPa~Pd  
OE  
Output Enable  
VDDQ  
Output Power Supply  
(2.5V or 3.3V)  
GW  
BW  
ZZ  
Global Write Enable  
Byte Write Enable  
Power Down Input  
Burst Mode Control  
LBO  
TCK  
TMS  
TDI  
JTAG Test Clock  
JTAG Test Mode Select  
JTAG Test Data Input  
JTAG Test Data Output  
TDO  
- 6 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)  
K7A161800A(1Mx18)  
1
2
A
3
A
4
ADSP  
ADSC  
VDD  
NC  
5
A
6
A
7
A
B
C
D
E
F
VDDQ  
NC  
VDDQ  
NC  
A
A
A
A
NC  
A
A
A
A
NC  
DQb  
NC  
NC  
DQb  
NC  
DQb  
NC  
VDD  
DQb  
NC  
DQb  
NC  
DQPb  
VSS  
VSS  
VSS  
WEb  
VSS  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
LBO  
A
VSS  
VSS  
VSS  
VSS  
VSS  
NC  
VSS  
WEa  
VSS  
VSS  
VSS  
NC  
A
DQPa  
NC  
DQa  
NC  
DQa  
VDD  
NC  
DQa  
NC  
DQa  
NC  
A
NC  
CS1  
OE  
DQa  
VDDQ  
DQa  
NC  
VDDQ  
NC  
G
H
J
ADV  
GW  
VDD  
CLK  
NC  
DQb  
VDDQ  
NC  
VDDQ  
DQa  
NC  
K
L
DQb  
VDDQ  
DQb  
NC  
M
N
P
R
T
BW  
VDDQ  
NC  
A1*  
A0*  
DQa  
NC  
NC  
VDD  
NC  
A
A
NC  
A
ZZ  
U
VDDQ  
TMS  
TDI  
TCK  
TDO  
NC  
VDDQ  
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.  
PIN NAME  
SYMBOL  
PIN NAME  
SYMBOL  
PIN NAME  
Power Supply(+3.3V)  
A
A0,A1  
Address Inputs  
VDD  
VSS  
Burst Count Address  
Ground  
ADV  
Burst Address Advance  
Address Status Processor  
Address Status Controller  
Clock  
N.C.  
No Connect  
ADSP  
ADSC  
CLK  
DQa  
DQb  
DQPa~Pb  
Data Inputs/Outputs  
Data Inputs/Outputs  
Data Inputs/Outpus  
CS1  
Chip Select  
WEx  
Byte Write Inputs  
(x=a,b)  
VDDQ  
Output Power Supply  
(2.5V or 3.3V)  
OE  
Output Enable  
GW  
BW  
ZZ  
Global Write Enable  
Byte Write Enable  
Power Down Input  
Burst Mode Control  
LBO  
TCK  
TMS  
TDI  
JTAG Test Clock  
JTAG Test Mode Select  
JTAG Test Data Input  
JTAG Test Data Output  
TDO  
- 7 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
165-PIN FGBA PACKAGE CONFIGURATIONS(TOP VIEW)  
K7A163600A(512Kx36)  
1
2
3
4
5
6
7
8
ADSC  
OE  
9
10  
A
11  
NC  
CS2  
NC  
A
CS1  
WEc  
WEd  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
A
WEb  
WEa  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
NC  
BW  
ADV  
ADSP  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
A
B
C
D
E
F
NC  
A
CS2  
CLK  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
A
GW  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
TDO  
TCK  
A
NC  
DQPc  
DQc  
DQc  
DQc  
DQc  
NC  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
A
NC  
DQb  
DQb  
DQb  
DQb  
NC  
DQa  
DQa  
DQa  
DQa  
NC  
A
DQPb  
DQb  
DQb  
DQb  
DQb  
ZZ  
DQc  
DQc  
DQc  
DQc  
VSS  
DQd  
DQd  
DQd  
DQd  
NC  
G
H
J
DQd  
DQd  
DQd  
DQd  
DQPd  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
A
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
A
DQa  
DQa  
DQa  
DQa  
DQPa  
A
K
L
M
N
P
R
NC  
TDI  
A1*  
LBO  
NC  
A
A
TMS  
A0*  
A
A
A
A
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.  
PIN NAME  
SYMBOL  
PIN NAME  
SYMBOL  
PIN NAME  
Power Supply(+3.3V)  
A
Address Inputs  
VDD  
VSS  
A0, A1  
Burst Count Address  
Ground  
ADV  
Burst Address Advance  
Address Status Processor  
Address Status Controller  
Clock  
Chip Select  
Byte Write Inputs  
N.C.  
No Connect  
ADSP  
ADSC  
CLK  
CS1  
WEx  
DQa  
DQb  
DQc  
DQd  
Data Inputs/Outputs  
Data Inputs/Outputs  
Data Inputs/Outputs  
Data Inputs/Outputs  
Data Inputs/Outpus  
(x=a,b,c,d)  
DQPa~Pd  
OE  
Output Enable  
VDDQ  
Output Power Supply  
(2.5V or 3.3V)  
GW  
BW  
ZZ  
Global Write Enable  
Byte Write Enable  
Power Down Input  
Burst Mode Control  
LBO  
TCK  
TMS  
TDI  
JTAG Test Clock  
JTAG Test Mode Select  
JTAG Test Data Input  
JTAG Test Data Output  
TDO  
- 8 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
165-PIN FGBA PACKAGE CONFIGURATIONS(TOP VIEW)  
K7A161800A(1Mx18)  
1
NC  
2
3
4
5
6
7
8
ADSC  
OE  
9
10  
A
11  
A
CS2  
A
CS1  
WEb  
NC  
NC  
BW  
ADV  
ADSP  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
A
B
C
D
E
F
NC  
A
CS2  
WEa  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
NC  
CLK  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
A
GW  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
TDO  
TCK  
A
NC  
DQPa  
DQa  
DQa  
DQa  
DQa  
ZZ  
NC  
NC  
DQb  
DQb  
DQb  
DQb  
VSS  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
A
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
A
NC  
NC  
NC  
NC  
NC  
NC  
DQa  
DQa  
DQa  
DQa  
NC  
A
NC  
NC  
NC  
G
H
J
NC  
NC  
DQb  
DQb  
DQb  
DQb  
DQPb  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
A
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
A
NC  
NC  
NC  
NC  
NC  
A
K
L
M
N
P
R
TDI  
A1*  
LBO  
A
A
TMS  
A0*  
A
A
A
A
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.  
PIN NAME  
SYMBOL  
PIN NAME  
SYMBOL  
PIN NAME  
Power Supply(+3.3V)  
A
A0,A1  
Address Inputs  
VDD  
VSS  
Burst Count Address  
Ground  
ADV  
Burst Address Advance  
Address Status Processor  
Address Status Controller  
Clock  
N.C.  
No Connect  
ADSP  
ADSC  
CLK  
DQa  
DQb  
DQPa~Pb  
Data Inputs/Outputs  
Data Inputs/Outputs  
Data Inputs/Outpus  
CS1  
Chip Select  
WEx  
Byte Write Inputs  
(x=a,b)  
VDDQ  
Output Power Supply  
(2.5V or 3.3V)  
OE  
Output Enable  
GW  
BW  
ZZ  
Global Write Enable  
Byte Write Enable  
Power Down Input  
Burst Mode Control  
LBO  
TCK  
TMS  
TDI  
JTAG Test Clock  
JTAG Test Mode Select  
JTAG Test Data Input  
JTAG Test Data Output  
TDO  
- 9 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
FUNCTION DESCRIPTION  
The K7A163600A , K7A163200A and K7A161800A are synchronous SRAM designed to support the burst address accessing  
sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock  
edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.  
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with  
ADV.  
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ  
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.  
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address  
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-  
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-  
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output  
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address  
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to  
control signals by disabling CS1.  
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx  
when GW is high.  
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-  
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled  
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the  
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte  
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7  
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-  
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;  
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.  
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).  
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external  
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state  
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is  
selected.  
BURST SEQUENCE TABLE  
(Interleaved Burst)  
Case 4  
Case 1  
Case 2  
Case 3  
LBO PIN  
HIGH  
First Address  
A1  
A0  
A1  
A0  
A1  
A0  
A1  
A0  
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address  
BQ TABLE  
(Linear Burst)  
Case 1  
Case 2  
Case 3  
Case 4  
LBO PIN  
LOW  
First Address  
A1  
A0  
A1  
A0  
A1  
A0  
A1  
A0  
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address  
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.  
ASYNCHRONOUS TRUTH TABLE  
Operation  
ZZ  
H
L
OE  
X
I/O STATUS  
High-Z  
Notes  
1. X means "Don¢t Care".  
2. ZZ pin is pulled down internally  
3. For write cycles that following read cycles, the output buffers must be  
disabled with OE, otherwise data bus contention will occur.  
4. Sleep Mode means power down state of which stand-by current does  
not depend on cycle time.  
Sleep Mode  
L
DQ  
Read  
L
H
X
High-Z  
Write  
L
Din, High-Z  
High-Z  
5. Deselected means power down state of which stand-by current  
depends on cycle time.  
Deselected  
L
X
- 10 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
TRUTH TABLES  
SYNCHRONOUS TRUTH TABLE  
CS1  
H
L
CS2  
X
L
CS2 ADSP ADSC ADV WRITE CLK  
ADDRESS ACCESSED  
N/A  
OPERATION  
Not Selected  
X
X
H
X
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N/A  
Not Selected  
L
X
L
L
N/A  
Not Selected  
L
X
X
L
N/A  
Not Selected  
L
X
H
H
H
X
X
X
X
X
X
X
X
L
N/A  
Not Selected  
L
X
L
External Address  
External Address  
External Address  
Next Address  
Next Address  
Next Address  
Next Address  
Current Address  
Current Address  
Current Address  
Current Address  
Begin Burst Read Cycle  
Begin Burst Write Cycle  
Begin Burst Read Cycle  
Continue Burst Read Cycle  
Continue Burst Read Cycle  
Continue Burst Write Cycle  
Continue Burst Write Cycle  
Suspend Burst Read Cycle  
Suspend Burst Read Cycle  
Suspend Burst Write Cycle  
Suspend Burst Write Cycle  
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
Notes : 1. X means "Don¢t Care".  
2. The rising edge of clock is symbolized by • .  
3. WRITE = L means Write operation in WRITE TRUTH TABLE.  
WRITE = H means Read operation in WRITE TRUTH TABLE.  
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).  
WRITE TRUTH TABLE(x36 / x32)  
GW  
H
BW  
H
L
WEa  
X
WEb  
X
WEc  
X
WEd  
X
OPERATION  
READ  
H
H
H
H
H
READ  
H
L
L
H
H
H
WRITE BYTE a  
WRITE BYTE b  
WRITE BYTE c and d  
WRITE ALL BYTEs  
WRITE ALL BYTEs  
H
L
H
L
H
H
H
L
H
H
L
L
H
L
L
L
L
L
L
X
X
X
X
X
Notes : 1. X means "Don¢t Care".  
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).  
WRITE TRUTH TABLE(x18)  
GW  
H
BW  
H
L
WEa  
X
WEb  
X
OPERATION  
READ  
H
H
H
READ  
H
L
L
H
WRITE BYTE a  
WRITE BYTE b  
WRITE ALL BYTEs  
WRITE ALL BYTEs  
H
L
H
L
H
L
L
L
L
X
X
X
Notes : 1. X means "Don¢t Care".  
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).  
- 11 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
ABSOLUTE MAXIMUM RATINGS*  
PARAMETER  
Voltage on VDD Supply Relative to VSS  
Voltage on VDDQ Supply Relative to VSS  
Voltage on Input Pin Relative to VSS  
Voltage on I/O Pin Relative to VSS  
Power Dissipation  
SYMBOL  
VDD  
RATING  
-0.3 to 4.6  
VDD  
UNIT  
V
VDDQ  
VIN  
V
-0.3 to VDD+0.3  
-0.3 to VDDQ+0.3  
1.6  
V
VIO  
V
PD  
W
Storage Temperature  
TSTG  
TOPR  
TOPR  
TBIAS  
-65 to 150  
0 to 70  
°C  
°C  
°C  
°C  
Commercial  
Industrial  
Operating Temperature  
-40 to 85  
-10 to 85  
Storage Temperature Range Under Bias  
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only  
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not  
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
OPERATING CONDITIONS at 3.3V I/O(0°C £ TA £ 70°C)  
PARAMETER  
Supply Voltage  
Ground  
SYMBOL  
MIN  
3.135  
3.135  
0
Typ.  
3.3  
3.3  
0
MAX  
3.465  
3.465  
0
UNIT  
VDD  
V
V
V
VDDQ  
VSS  
* The above parameters are also guaranteed at industrial temperature range.  
OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)  
PARAMETER  
Supply Voltage  
Ground  
SYMBOL  
MIN  
3.135  
2.375  
0
Typ.  
3.3  
2.5  
0
MAX  
3.465  
2.9  
UNIT  
VDD  
V
V
V
VDDQ  
VSS  
0
* The above parameters are also guaranteed at industrial temperature range.  
CAPACITANCE*(TA=25°C, f=1MHz)  
PARAMETER  
Input Capacitance  
SYMBOL  
CIN  
TEST CONDITION  
VIN=0V  
MIN  
MAX  
UNIT  
-
-
5
7
pF  
pF  
Output Capacitance  
COUT  
VOUT=0V  
*Note : Sampled not 100% tested.  
VIH  
VSS  
VSS-1.0V  
20% tCYC(MIN)  
- 12 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)  
MIN  
MAX  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
VDD = Max ; VIN=VSS to VDD  
UNIT NOTES  
Input Leakage Current(except ZZ)  
Output Leakage Current  
IIL  
-2  
-2  
-
+2  
mA  
mA  
IOL  
Output Disabled, VOUT=VSS to VDDQ  
+2  
-25  
-22  
-20  
-16  
-14  
-25  
-22  
-20  
-16  
-14  
470  
430  
400  
350  
290  
120  
110  
100  
90  
-
Device Selected, IOUT=0mA,  
ZZ£VIL , Cycle Time ³ tCYC Min  
Operating Current  
ICC  
-
mA  
mA  
1,2  
-
-
-
-
Device deselected, IOUT=0mA,  
ZZ£VIL, f=Max,  
ISB  
-
All Inputs£0.2V or ³ VDD-0.2V  
-
Standby Current  
-
90  
Device deselected, IOUT=0mA, ZZ£0.2V,  
f = 0, All Inputs=fixed (VDD-0.2V or 0.2V)  
ISB1  
ISB2  
-
-
70  
60  
mA  
mA  
Device deselected, IOUT=0mA, ZZ³ VDD-  
0.2V, f=Max, All Inputs£VIL or ³ VIH  
Output Low Voltage(3.3V I/O)  
Output High Voltage(3.3V I/O)  
Output Low Voltage(2.5V I/O)  
Output High Voltage(2.5V I/O)  
Input Low Voltage(3.3V I/O)  
nput High Voltage(3.3V I/O)  
Input Low Voltage(2.5V I/O)  
Input High Voltage(2.5V I/O)  
VOL  
VOH  
VOL  
VOH  
VIL  
IOL=8.0mA  
IOH=-4.0mA  
IOL=1.0mA  
IOH=-1.0mA  
-
0.4  
V
V
V
V
V
V
V
V
2.4  
-
-
0.4  
-
2.0  
-0.3*  
2.0  
-0.3*  
1.7  
0.8  
VDD+0.3**  
0.7  
3
3
VIH  
VIL  
VIH  
VDD+0.3**  
Notes : 1. The above parameters are also guaranteed at industrial temperature range.  
2. Reference AC Operating Conditions and Characteristics for input and timing.  
3. Data states are all zero.  
4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V.  
VIH  
VSS  
VSS-1.0V  
20% tCYC(MIN)  
TEST CONDITIONS  
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, T  
A=0to70°C)  
PARAMETER  
VALUE  
0 to 3.0V  
0 to 2.5V  
1.0V/ns  
1.0V/ns  
1.5V  
Input Pulse Level(for 3.3V I/O)  
Input Pulse Level(for 2.5V I/O)  
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)  
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)  
Input and Output Timing Reference Levels for 3.3V I/O  
Input and Output Timing Reference Levels for 2.5V I/O  
Output Load  
VDDQ/2  
See Fig. 1  
* The above parameters are also guaranteed at industrial temperature range.  
- 13 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
Output Load(A)  
Output Load(B),  
(for tLZC, tLZOE, tHZOE & tHZC)  
+3.3V for 3.3V I/O  
/+2.5V for 2.5V I/O  
RL=50W  
Dout  
VL=1.5V for 3.3V I/O  
319W / 1667W  
VDDQ/2 for 2.5V I/O  
30pF*  
Dout  
Zo=50W  
353W / 1538W  
5pF*  
* Including Scope and Jig Capacitance  
Fig. 1  
AC TIING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)  
-25  
-22  
-20  
-16  
-14  
Parameter  
Symbol  
Unit  
MIN MAX Min Max MIN MAX Min Max Min Max  
Cycle Time  
tCYC  
tCD  
4.0  
-
-
4.4  
-
-
5.0  
-
-
6.0  
-
-
7.2  
-
-
ns  
ns  
Clock Access Time  
2.6  
2.8  
3.1  
3.5  
4.0  
Output Enable to Data Valid  
tOE  
-
2.6  
-
2.8  
-
3.1  
-
3.5  
-
4.0  
ns  
Clock High to Output Low-Z  
tLZC  
tOH  
0
-
0
-
0
-
0
-
0
-
ns  
Output Hold from Clock High  
Output Enable Low to Output Low-Z  
Output Enable High to Output High-Z  
Clock High to Output High-Z  
Clock High Pulse Width  
1.5  
0
-
1.5  
0
-
1.5  
0
-
1.5  
0
-
1.5  
0
-
ns  
tLZOE  
tHZOE  
tHZC  
tCH  
-
-
-
-
-
ns  
ns  
-
2.6  
-
2.8  
-
3.0  
-
3.0  
-
3.5  
1.5  
1.7  
1.7  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
0.3  
0.3  
0.3  
0.3  
0.3  
0.3  
2
2.6  
-
1.5  
1.8  
1.8  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
2
2.8  
-
1.5  
2.0  
2.0  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
2
3.0  
-
1.5  
2.1  
2.1  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
2
3.0  
-
1.5  
2.5  
2.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
2
3.5  
-
ns  
ns  
Clock Low Pulse Width  
tCL  
-
-
-
-
-
ns  
Address Setup to Clock High  
Address Status Setup to Clock High  
Data Setup to Clock High  
tAS  
-
-
-
-
-
ns  
tSS  
-
-
-
-
-
ns  
tDS  
-
-
-
-
-
ns  
Write Setup to Clock High (GW, BW, WEX)  
Address Advance Setup to Clock High  
Chip Select Setup to Clock High  
Address Hold from Clock High  
Address Status Hold from Clock High  
Data Hold from Clock High  
tWS  
-
-
-
-
-
ns  
tADVS  
tCSS  
tAH  
-
-
-
-
-
ns  
-
-
-
-
-
ns  
-
-
-
-
-
ns  
tSH  
-
-
-
-
-
ns  
tDH  
-
-
-
-
-
ns  
Write Hold from Clock High (GW, BW, WEX)  
Address Advance Hold from Clock High  
Chip Select Hold from Clock High  
ZZ High to Power Down  
tWH  
tADVH  
tCSH  
tPDS  
tPUS  
-
-
-
-
-
ns  
-
-
-
-
-
ns  
-
-
-
-
-
ns  
-
-
-
-
-
cycle  
cycle  
ZZ Low to Power Up  
2
-
2
-
2
-
2
-
2
-
Notes : 1. The above parameters are also guaranteed at industrial temperature range.  
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS  
is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.  
3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.  
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.  
- 14 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG  
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan  
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not  
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-  
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,  
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without  
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an  
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be  
tied to VDD through a resistor. TDO should be left unconnected.  
JTAG Block Diagram  
JTAG Instruction Coding  
IR2 IR1 IR0 Instruction  
TDO Output  
Notes  
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST  
IDCODE  
SAMPLE-Z  
BYPASS  
SAMPLE  
Boundary Scan Register  
Identification Register  
Boundary Scan Register  
Bypass Register  
1
3
2
4
5
6
4
4
0
0
0
1
Boundary Scan Register  
1
RESERVED Do Not Use  
SRAM  
CORE  
1
1
BYPASS  
BYPASS  
Bypass Register  
Bypass Register  
NOTE :  
1. Places DQs in Hi-Z in order to sample all input data regardless of other  
SRAM inputs. This instruction is not IEEE 1149.1 compliant.  
TDI  
BYPASS Reg.  
2. Places DQs in Hi-Z in order to sample all input data regardless of other  
SRAM inputs.  
TDO  
Identification Reg.  
Instruction Reg.  
3. TDI is sampled as an input to the first ID register to allow for the serial shift  
of the external TDI data.  
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The  
Bypass Register also holds serially loaded TDI when exiting the Shift DR  
states.  
Control Signals  
TAP Controller  
TMS  
TCK  
5. SAMPLE instruction dose not places DQs in Hi-Z.  
6. This instruction is reserved for future use.  
TAP Controller State Diagram  
1
0
Test Logic Reset  
0
1
1
1
0
Run Test Idle  
Select DR  
0
Select IR  
0
1
1
1
1
Capture DR  
0
Capture IR  
0
0
Shift DR  
1
Shift IR  
1
Exit1 DR  
0
Exit1 IR  
0
0
0
0
0
Pause DR  
1
Pause IR  
1
Exit2 DR  
1
Exit2 IR  
1
1
0
Update DR  
0
Update IR  
1
- 15 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
SCAN REGISTER DEFINITION  
Part  
Instruction Register  
Bypass Register  
1 bits  
ID Register  
32 bits  
Boundary Scan  
75 bits  
512Kx36  
1Mx18  
3 bits  
3 bits  
1 bits  
32 bits  
75 bits  
ID REGISTER DEFINITION  
Revision Number Part Configuration Vendor Definition Samsung JEDEC Code  
Part  
Start Bit(0)  
(31:28)  
(27:18)  
(17:12)  
XXXXXX  
XXXXXX  
(11: 1)  
512Kx36  
1Mx18  
0000  
00111 00100  
01000 00011  
00001001110  
00001001110  
1
1
0000  
119BGA BOUNDARY SCAN EXIT ORDER(x36)  
119BGA BOUNDARY SCAN EXIT ORDER(x18)  
1
2T  
1R  
4T  
4H  
5R  
5T  
5L  
NC  
NC  
CLK  
ADV  
ADSC  
ADSP  
BW  
WEc  
A
4K  
4G  
4B  
4A  
4M  
3G  
3B  
3A  
2B  
4E  
3C  
2C  
2A  
2D  
1E  
2F  
1G  
2H  
1D  
2E  
2G  
1H  
2K  
1L  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
1
2T  
1R  
6T  
4H  
5R  
5T  
5L  
A
NC  
A
CLK  
ADV  
ADSC  
ADSP  
BW  
WEb  
A
4K  
4G  
4B  
4A  
4M  
3G  
3B  
3A  
2B  
4E  
3C  
2C  
2A  
2D  
1E  
2F  
1G  
2H  
1D  
2E  
2G  
1H  
2K  
1L  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
2
2
3
A
3
4
GW  
NC  
4
GW  
NC  
A
5
5
6
A
6
7
WEa  
NC  
7
WEa  
NC  
A
8
7R  
6R  
7T  
6P  
7N  
6M  
7L  
A
8
7R  
6R  
7T  
6P  
7N  
6M  
7L  
A
9
A
A
9
A
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
ZZ  
CS1  
A
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
ZZ  
CS1  
A
DQPa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
NC  
NC  
NC  
NC  
NC  
NC  
DQa  
DQa  
DQa  
DQa  
NC  
DQa  
DQa  
DQa  
DQa  
DQPa  
NC  
NC  
NC  
NC  
NC  
A
A
A
A
A
DQPc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQPd  
WEd  
LBO  
A
NC  
6K  
7P  
6N  
6L  
6K  
7P  
6N  
6L  
NC  
NC  
NC  
NC  
7K  
5J  
7K  
5J  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQPb  
NC  
6H  
7G  
6F  
7E  
7D  
7H  
6G  
6E  
6D  
7B  
6C  
5C  
6A  
5B  
5A  
4F  
5G  
6B  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQPb  
NC  
6H  
7G  
6F  
7E  
6D  
7H  
6G  
6E  
7D  
7B  
6C  
5C  
6A  
5B  
5A  
4F  
5G  
6B  
2M  
1N  
1P  
1K  
2L  
2M  
1N  
2P  
1K  
2L  
NC  
2N  
2P  
3L  
NC  
2N  
1P  
3L  
A
NC  
A
A
NC  
A
3R  
2R  
3T  
4N  
4P  
A
LBO  
A
3R  
2R  
3T  
4N  
4P  
A
A
A
A
A
A
OE  
A1  
OE  
NC  
A
A1  
WEb  
A
A0  
A0  
NOTE, NC ; Don¢t Care  
- 16 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
165FBGA BOUNDARY SCAN EXIT ORDER(x36)  
165FBGA BOUNDARY SCAN EXIT ORDER(x18)  
1
1R  
6N  
LBO  
A
CLK  
NC  
6B  
11B  
1A  
6A  
5B  
5A  
4A  
4B  
3B  
3A  
2A  
2B  
1B  
1C  
1D  
1E  
1F  
1G  
2D  
2E  
2F  
2G  
1J  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
1
1R  
6N  
LBO  
A
CLK  
NC  
NC  
CS2  
WEa  
NC  
WEb  
NC  
CS2  
CS1  
A
6B  
11B  
1A  
6A  
5B  
5A  
4A  
4B  
3B  
3A  
2A  
2B  
1B  
1C  
1D  
1E  
1F  
1G  
2D  
2E  
2F  
2G  
1J  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
2
2
3
11P  
8P  
A
NC  
3
11P  
8P  
A
4
A
CS2  
WEa  
WEb  
WEc  
WEd  
CS2  
CS1  
A
4
A
5
8R  
A
5
8R  
A
6
9R  
A
6
9R  
A
7
9P  
A
7
9P  
A
8
10P  
10R  
11R  
11H  
11N  
11M  
11L  
11K  
11J  
10M  
10L  
10K  
10J  
11G  
11F  
11E  
11D  
10G  
10F  
10E  
10D  
11C  
11A  
10A  
10B  
9A  
A
8
10P  
10R  
11R  
11H  
11N  
11M  
11L  
11K  
11J  
10M  
10L  
10K  
10J  
11G  
11F  
11E  
11D  
11C  
10F  
10E  
10D  
10G  
11A  
10A  
10B  
9A  
A
9
A
9
A
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
A
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
A
ZZ  
ZZ  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
NC  
A
NC  
NC  
NC  
NC  
NC  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
NC  
NC  
NC  
NC  
A
A
NC  
NC  
NC  
NC  
NC  
NC  
NC  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
NC  
NC  
NC  
NC  
A
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
A
1K  
1L  
1K  
1L  
1M  
2J  
1M  
1N  
2K  
2L  
2K  
2L  
2M  
1N  
3P  
3R  
4R  
4P  
6P  
6R  
2M  
2J  
A
A
A
A
3P  
3R  
4R  
4P  
6P  
6R  
ADV  
ADSP  
ADSC  
OE  
A
ADV  
ADSP  
ADSC  
OE  
BW  
GW  
A
9B  
A
9B  
A
8A  
A
8A  
A
8B  
A1  
8B  
A1  
7A  
BW  
GW  
A0  
7A  
A0  
7B  
7B  
NOTE, NC ; Don¢t Care  
- 17 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
JTAG DC OPERATING CONDITIONS  
Parameter  
Power Supply Voltage  
Symbol  
Min  
3.135  
2.0 / 1.7  
-0.3  
Typ  
Max  
3.465  
VDD+0.3  
0.8 / 0.7  
-
Unit  
V
Note  
VDD  
VIH  
3.3  
Input High Level ( 3.3V I/O / 2.5V I/O )  
Input Low Level ( 3.3V I/O / 2.5V I/O )  
Output High Voltage( 3.3V I/O / 2.5V I/O )  
Output Low Voltage( 3.3V I/O / 2.5V I/O )  
-
-
-
-
V
1
VIL  
V
VOH  
VOL  
2.4 / 2.0  
-
V
0.4 / 0.4  
V
NOTE : The input level of SRAM pin is to follow the SRAM DC specification.  
1. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V.  
JTAG AC TEST CONDITIONS  
Parameter  
Symbol  
VIH/VIL  
TR/TF  
Min  
Unit  
V
Note  
Input High/Low Level( 3.3V I/O , 2.5V I/O )  
Input Rise/Fall Time( 3.3V I/O , 2.5V I/O )  
Input and Output Timing Reference Level  
3.0/0 , 2.5/0  
1.0/1.0 , 1.0/1.0  
VDDQ/2  
ns  
V
JTAG AC Characteristics  
Parameter  
TCK Cycle Time  
Symbol  
Min  
50  
20  
20  
5
Max  
Unit  
Note  
tCHCH  
tCHCL  
tCLCH  
tMVCH  
tCHMX  
tDVCH  
tCHDX  
tSVCH  
tCHSX  
tCLQV  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TCK High Pulse Width  
TCK Low Pulse Width  
TMS Input Setup Time  
TMS Input Hold Time  
TDI Input Setup Time  
TDI Input Hold Time  
-
-
-
5
-
5
-
5
-
SRAM Input Setup Time  
SRAM Input Hold Time  
Clock Low to Output Valid  
5
-
5
-
0
10  
JTAG TIMING DIAGRAM  
TCK  
tCHCH  
tCHCL  
tCLCH  
tMVCH  
tCHMX  
tCHDX  
TMS  
TDI  
tDVCH  
tSVCH  
tCHSX  
PI  
(SRAM)  
tCLQV  
TDO  
- 18 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
- 19 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
- 20 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
- 21 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
- 22 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
- 23 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
APPLICATION INFORMATION  
DEPTH EXPANSION  
The Samsung 512Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.  
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.  
I/O[0:71]  
Data  
Address  
A
[0:19]  
A
[19]  
A
[0:18]  
A
[19]  
A[0:18]  
Address Data  
Address Data  
CLK  
CS  
CS  
2
CS2  
CS2  
2
CLK  
ADSC  
WEx  
OE  
512Kx36  
SPB  
SRAM  
CLK  
ADSC  
WEx  
OE  
512Kx36  
SPB  
SRAM  
Microprocessor  
Address  
CLK  
(Bank 1)  
(Bank 0)  
Cache  
Controller  
CS  
1
CS1  
ADV ADSP  
ADV ADSP  
ADS  
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)  
(ADSP CONTROLLED , ADSC=HIGH)  
Clock  
tSS  
tSH  
ADSP  
tAS  
tAH  
A1  
A2  
ADDRESS  
[0:n]  
tWS  
tWH  
WRITE  
CS1  
tCSS  
tCSH  
Bank 0 is selected by CS2, and Bank 1 deselected by CS2  
An+1  
ADV  
OE  
Bank 0 is deselected by CS2, and Bank 1 selected by CS2  
tADVS  
tADVH  
tOE  
tHZC  
tLZOE  
Data Out  
(Bank 0)  
Q1-1  
Q1-2  
Q1-3  
Q1-4  
tCD  
tLZC  
Data Out  
(Bank 1)  
Q2-1  
Q2-2  
Q2-3  
Q2-4  
*Notes : n = 14 32K depth ,  
15 64K depth  
16 128K depth , 17 256K depth  
18 512K depth , 19 1M depth  
Don¢t Care  
Undefined  
- 24 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
APPLICATION INFORMATION  
DEPTH EXPANSION  
The Samsung 1Mx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.  
This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic.  
I/O[0:71]  
Data  
Address  
A
[20]  
A[20]  
A[0:20]  
A[0:19]  
A[0:19]  
Address Data  
Address Data  
CS  
CS  
CLK  
CS  
CS  
2
2
2
2
Microprocessor  
1Mx18  
SPB  
SRAM  
CLK  
ADSC  
WEx  
OE  
1Mx18  
SPB  
SRAM  
CLK  
ADSC  
WEx  
OE  
Address  
CLK  
(Bank 1)  
(Bank 0)  
Cache  
Controller  
CS1  
CS  
1
ADV ADSP  
ADV ADSP  
ADS  
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)  
(ADSP CONTROLLED , ADSC=HIGH)  
Clock  
tSS  
tSH  
ADSP  
tAS  
tAH  
A1  
A2  
ADDRESS  
[0:n]  
tWS  
tWH  
WRITE  
CS1  
tCSH  
tCSS  
Bank 0 is selected by CS2, and Bank 1 deselected by CS2  
An+1  
ADV  
OE  
Bank 0 is deselected by CS2, and Bank 1 selected by CS2  
tADVS  
tADVH  
tOE  
tLZOE  
tHZC  
Data Out  
(Bank 0)  
Q1-1  
Q1-2  
Q1-3  
Q1-4  
tCD  
tLZC  
Data Out  
(Bank 1)  
Q2-1  
Q2-2  
Q2-3  
Q2-4  
*Notes : n = 14 32K depth ,  
15 64K depth  
16 128K depth , 17 256K depth  
18 512K depth , 19 1M depth  
20 2M depth  
Undefined  
Don¢t Care  
- 25 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
PACKAGE DIMENSIONS  
Units ; millimeters/Inches  
100-TQFP-1420A  
22.00 ±0.30  
20.00 ±0.20  
0~8°  
+ 0.10  
- 0.05  
0.127  
16.00 ±0.30  
0.10 MAX  
14.00 ±0.20  
(0.83)  
0.50 ±0.10  
#1  
0.65  
(0.58)  
0.30 ±0.10  
0.10 MAX  
1.40 ±0.10  
1.60 MAX  
0.05 MIN  
0.50 ±0.10  
- 26 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
119 BGA PACKAGE DIMENSIONS  
1.27  
1.27  
14.00±0.10  
22.00±0.10  
Indicator of  
Ball(1A) Location  
20.50±0.10  
C0.70  
C1.00  
0.750±0.15  
1.50REF  
0.60±0.10  
0.60±0.10  
NOTE :  
1. All Dimensions are in Millimeters.  
2. Solder Ball to PCB Offset : 0.10 MAX.  
3. PCB to Cavity Offset : 0.10 MAX.  
12.50±0.10  
- 27 -  
May 2002  
Rev 2.0  
K7A163600A  
K7A163200A  
K7A161800A  
512Kx36/x32 & 1Mx18 Synchronous SRAM  
165 FBGA PACKAGE DIMENSIONS  
13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array  
A
B
Top View  
C
Side View  
D
A
F
E
B
Bottom View  
G
Æ H  
E
Symbol  
Value  
15 ± 0.1  
Units  
mm  
Note  
Symbol  
Value  
1.0  
Units  
mm  
Note  
A
B
C
D
E
F
13 ± 0.1  
1.3 ± 0.1  
0.35 ± 0.05  
mm  
14.0  
10.0  
mm  
mm  
G
H
mm  
mm  
0.45 ± 0.05  
mm  
- 28 -  
May 2002  
Rev 2.0  

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