K7A161800M-HC14 [SAMSUNG]
Cache SRAM, 1MX18, 4ns, CMOS, PBGA119, BGA-119;
| 型号： | K7A161800M-HC14 |
| 厂家： | 
SAMSUNG |
| 描述： | Cache SRAM, 1MX18, 4ns, CMOS, PBGA119, BGA-119 静态存储器 |
| 文件： | 总20页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
Document Title
512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev.No.
History
Draft Date
Remark
0.0
0.1
0.2
Initial draft
Dec. 29. 1998
Preliminary
1. Update ICC & ISB values.
May. 27. 1999 Preliminary
1. Change ISB value from 150mA to 110mA at -67.
2. Change ISB value from 130mA to 90mA at -72 .
3. Change ISB value from 120mA to 80mA at -10 .
Sep. 04. 1999
Nov. 19. 1999
Preliminary
Preliminary
0.3
1. Add tCYC 167MHz and 183MHz.
2. Changed DC condition at Icc and parameters
Icc ; from 420mA to 400mA at -67,
from 400mA to 380mA at -72,
from 350mA to 320mA at -10,
1.0
2.0
1. Final Spec Release.
Dec. 08. 1999
Feb. 23. 2001
Final
Final
1. Remove tCYC 183MHz & 100MHz .
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
The K7A163600M and K7A161800M are 18,874,368-bit
Synchronous Static Random Access Memory designed for
high performance second level cache of Pentium and
Power PC based System.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V +0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
It is organized as 512K(1M) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS1 high, ADSP is blocked to control sig-
nals.
• Three Chip Enables for simple depth expansion with No Data Con-
tention only for TQFP ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache control-
ler(ADSC) inputs. Subsequent burst addresses are gener-
ated internally in the system¢s burst sequence and are
controlled by the burst address advance(ADV) input.
LBO pin is DC operated and determines burst
sequence(linear or interleaved).
• 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package)
FAST ACCESS TIMES
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
PARAMETER
Cycle Time
Symbol -16
-15
6.7
3.8
3.8
-14
7.2
4.0
4.0
Unit
ns
The K7A163600M and K7A161800M are fabricated using
SAMSUNG¢s high performance CMOS technology and is
available in a 100pin TQFP and 119BGA package. Multiple
power and ground pins are utilized to minimize ground
bounce.
tCYC
tCD
6.0
3.5
3.5
Clock Access Time
ns
Output Enable Access Time
tOE
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
512Kx36 , 1Mx18
BURST CONTROL
LOGIC
BURST
MEMORY
ADDRESS
COUNTER
ADV
ADSC
A¢0~A¢1
ARRAY
A0~A1
A2~A18
or A2~A19
A
0
~A18
ADDRESS
REGISTER
or A0~A19
ADSP
DATA-IN
REGISTER
CS
CS
CS
1
2
2
GW
BW
OUTPUT
REGISTER
CONTROL
LOGIC
BUFFER
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
DQPa ~ DQPd
or DQa0 ~ DQb7
DQPa,DQPb
- 2 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
(TOP VIEW)
PIN CONFIGURATION
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
VDD
N.C.
VSS
N.C.
VDD
ZZ
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
K7A163600M(512Kx36)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A18
Address Inputs
32,33,34,35,36,37,42 VDD
43,44,45,46,47,48,49 VSS
50,81,82,99,100
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
ADV
ADSP
ADSC
CLK
CS1
CS2
Burst Address Advance
Address Status Processor 84
Address Status Controller 85
83
No Connect
Data Inputs/Outputs
14,16,38,39,66
N.C.
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
Clock
89
98
97
92
Chip Select
Chip Select
Chip Select
CS2
WEx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
GW
BW
ZZ
Output Enable
86
88
87
64
31
Output Power Supply 4,11,20,27,54,61,70,77
(3.3V or 2.5V)
VDDQ
VSSQ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
Output Ground
5,10,21,26,55,60,71,76
LBO
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 3 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
(TOP VIEW)
PIN CONFIGURATION
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
1
2
3
4
5
6
7
8
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7A161800M(1Mx18)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A19
Address Inputs
32,33,34,35,36,37,42 VDD
43,44,45,46,47,48,49 VSS
50 80,81,82,99,100
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
ADV
ADSP
ADSC
CLK
CS1
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
83
84
85
89
98
97
92
No Connect
1,2,3,6,7,14,16,25,28,29
30,38,39,51,52,53,56,57
66,75,78,79,95,96
N.C.
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
DQa0 ~ a7
DQb0 ~ b7
DQPa, Pb
CS2
CS2
Chip Select
WEx(x=a,b) Byte Write Inputs
93,94
86
OE
Output Enable
Output Power Supply 4,11,20,27,54,61,70,77
(3.3V or 2.5V)
VDDQ
VSSQ
GW
BW
ZZ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
88
87
64
31
Output Ground
5,10,21,26,55,60,71,76
LBO
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 4 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
(TOP VIEW)
119BGA PACKAGE PIN CONFIGURATIONS
K7A163600M(512Kx36)
1
2
A
3
A
4
ADSP
ADSC
VDD
NC
5
6
A
7
A
B
C
D
E
F
VDDQ
NC
A
VDDQ
NC
A
A
A
A
NC
A
A
A
A
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
VSS
VSS
VSS
WEc
VSS
NC
VSS
WEd
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
WEb
VSS
NC
VSS
WEa
VSS
VSS
VSS
NC
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
CS1
OE
G
H
J
ADV
GW
VDD
CLK
NC
K
L
M
N
P
R
T
BW
A1*
A0*
VDD
A
NC
NC
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
Power Supply(+3.3V)
A
Address Inputs
VDD
VSS
A0, A1
Burst Count Address
Ground
ADV
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Byte Write Inputs
N.C.
No Connect
ADSP
ADSC
CLK
CS1
WEx
DQa
DQb
DQc
DQd
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
(x=a,b,c,d)
DQPa~Pd
OE
GW
BW
ZZ
Output Enable
VDDQ
Output Power Supply
(2.5V or 3.3V)
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
LBO
- 5 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
(TOP VIEW)
119BGA PACKAGE PIN CONFIGURATIONS
K7A161800M(1Mx18)
1
2
A
3
A
4
ADSP
ADSC
VDD
NC
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
VDDQ
NC
A
A
A
A
NC
A
A
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
VSS
VSS
VSS
WEb
VSS
NC
VSS
VSS
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
WEa
VSS
VSS
VSS
NC
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NC
CS1
OE
DQa
VDDQ
DQa
NC
VDDQ
NC
G
H
J
ADV
GW
VDD
CLK
NC
DQb
VDDQ
NC
VDDQ
DQa
NC
K
L
DQb
VDDQ
DQb
NC
M
N
P
R
T
BW
VDDQ
NC
A1*
A0*
DQa
NC
NC
VDD
NC
NC
A
A
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
Power Supply(+3.3V)
A
A0,A1
Address Inputs
VDD
VSS
Burst Count Address
Ground
ADV
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
N.C.
No Connect
ADSP
ADSC
CLK
DQa
DQb
DQPa~Pb
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
CS1
Chip Select
WEx
Byte Write Inputs
(x=a,b)
VDDQ
Output Power Supply
(2.5V or 3.3V)
OE
Output Enable
GW
BW
ZZ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
LBO
- 6 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
FUNCTION DESCRIPTION
The K7A163600M and K7A161800M are synchronous SRAM designed to support the burst address accessing sequence of the
Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and
duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb,WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
(Interleaved Burst)
BURST SEQUENCE TABLE
Case 1
Case 2
Case 3
Case 4
LBO PIN
HIGH
First Address
A 1
0
A 0
0
A 1
0
A 0
1
A 1
1
A 0
0
A 1
1
A 0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
Fourth Address
1
1
1
0
0
1
0
0
(Linear Burst)
BQ TABLE
Case 1
Case 2
Case 3
Case 4
A 0
LBO PIN
LOW
A 1
A 0
A 1
A 0
A 1
A 0
A 1
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ
H
L
OE
I/O STATUS
High-Z
Notes
1. X means "Don¢t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
Sleep Mode
X
L
DQ
Read
L
H
High-Z
Write
L
X
Din, High-Z
High-Z
5. Deselected means power down state of which stand-by current
depends on cycle time.
Deselected
L
X
- 7 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
L
CS2
X
CS2 ADSP ADSC ADV WRITE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
X
X
H
X
H
L
X
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
L
X
X
L
N/A
Not Selected
L
X
L
N/A
Not Selected
L
L
X
X
L
N/A
Not Selected
L
X
L
N/A
Not Selected
L
H
H
H
X
X
L
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
X
L
X
L
X
L
L
X
H
H
H
H
H
H
L
X
X
X
L
Notes : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by • .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE(x36)
GW
H
BW
H
L
WEa
X
WEb
WEc
X
WEd
OPERATION
READ
X
H
H
L
X
H
H
H
L
H
H
H
READ
H
L
L
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
H
H
L
H
H
L
L
H
L
L
L
L
L
X
X
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
WRITE TRUTH TABLE(x18)
GW
H
BW
H
L
WEa
X
WEb
OPERATION
X
H
H
L
READ
H
H
READ
H
L
L
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
H
L
L
L
L
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
- 8 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
PASS-THROUGH TRUTH TABLE
PREVIOUS CYCLE
PRESENT CYCLE
NEXT CYCLE
OPERATION
WRITE
OPERATION
CS1
WRITE OE
Initiate Read Cycle
Address=An
Data=Qn-1 for all bytes
Write Cycle, All bytes
Address=An-1, Data=Dn-1
Read Cycle
Data=Qn
All L
L
H
L
Write Cycle, All bytes
Address=An-1, Data=Dn-1
No new cycle
Data=Qn-1 for all bytes
No carryover from
previous cycle
All L
All L
H
H
H
H
L
Write Cycle, All bytes
Address=An-1, Data=Dn-1
No new cycle
Data=High-Z
No carryover from
previous cycle
H
Initiate Read Cycle
One L Address=An
Data=Qn-1 for one byte
Write Cycle, One byte
Address=An-1, Data=Dn-1
Read Cycle
Data=Qn
L
H
H
L
L
Write Cycle, One byte
Address=An-1, Data=Dn-1
No new cycle
Data=Qn-1 for one byte
No carryover from
previous cycle
One L
H
Note : 1. This operation makes written data immediately available at output during a read cycle preceded by a write cycle.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Voltage on I/O Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 4.6
VDD
UNIT
V
VDDQ
VIN
V
-0.3 to 4.6
-0.3 to VDDQ+0.5
1.6
V
VIO
V
PD
W
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
(0°C £ TA £ 70°C)
OPERATING CONDITIONS at 3.3V I/O
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
3.135
3.135
0
Typ.
3.3
3.3
0
MAX
3.465
3.465
0
UNIT
VDD
V
V
V
VDDQ
VSS
(0°C £ TA £ 70°C)
OPERATING CONDITIONS at 2.5V I/O
PARAMETER
SYMBOL
MIN
3.135
2.375
0
Typ.
3.3
2.5
0
MAX
3.465
2.9
UNIT
VDD
V
V
V
Supply Voltage
VDDQ
VSS
Ground
0
(TA=25°C, f=1MHz)
CAPACITANCE*
PARAMETER
SYMBOL
CIN
TEST CONDITION
VIN=0V
MIN
MAX
UNIT
pF
Input Capacitance
Output Capacitance
-
-
7
9
COUT
VOUT=0V
pF
*Note : Sampled not 100% tested.
- 9 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
DC ELECTRICAL CHARACTERISTICS
MIN
MAX
+2
PARAMETER
SYMBOL
TEST CONDITIONS
UNIT NOTES
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
VDD = Max ; VIN=VSS to VDD
-2
-2
-
mA
mA
IOL
Output Disabled, VOUT=VSS to VDDQ
+2
-16
-15
-14
-16
-15
-14
420
400
380
120
110
90
Device Selected, IOUT=0mA,
ZZ£ VIL , Cycle Time ³ tCYC Min
Operating Current
ICC
ISB
-
mA
mA
1,2
-
-
Device deselected, IOUT=0mA,
ZZ£VIL, f=Max,
-
All Inputs£0.2V or ³ VDD-0.2V
-
Standby Current
Device deselected, IOUT=0mA, ZZ£0.2V,
f = 0, All Inputs=fixed (VDD-0.2V or 0.2V)
ISB1
ISB2
-
-
30
30
mA
mA
Device deselected, IOUT=0mA, ZZ³ VDD-
0.2V, f=Max, All Inputs£VIL or ³ VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
nput High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL=8.0mA
IOH=-4.0mA
IOL=1.0mA
IOH=-1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
-
2.0
-0.3*
2.0
-0.3*
1.7
0.8
VIH
VDD+0.5**
0.7
3
3
VIL
VIH
VDD+0.5**
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.
2. Data states are all zero.
3. In Case of I/O Pins, the Max. VIH=VDDQ +0.3V.
VIH
VSS
VSS-1.0V
20% tCYC(MIN)
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C)
PARAMETER
VALUE
0 to 3.0V
0 to 2.5V
1.0V/ns
1.0V/ns
1.5V
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
VDDQ/2
See Fig. 1
- 10 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
Output Load(A)
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50W
Dout
VL=1.5V for 3.3V I/O
319W / 1667W
VDDQ/2 for 2.5V I/O
30pF*
Dout
Zo=50W
353W / 1538W
5pF*
* Including Scope and Jig Capacitance
Fig. 1
(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
AC TIMING CHARACTERISTICS
-16
-15
-14
Parameter
Symbol
Unit
Min
6.0
-
Max
Min
6.7
-
Max
Min
7.2
-
Max
Cycle Time
tCYC
tCD
-
-
-
ns
ns
Clock Access Time
3.5
3.8
4.0
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
tOE
-
3.5
-
3.8
-
4.0
ns
tLZC
tOH
0
-
0
-
0
-
ns
1.5
0
-
1.5
0
-
1.5
0
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
-
ns
ns
Output Enable High to Output High-Z
Clock High to Output High-Z
-
3.0
-
3.0
-
3.5
1.5
2.1
2.1
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
3.0
-
1.5
2.3
2.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
3.0
-
1.5
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
3.5
-
ns
Clock High Pulse Width
ns
Clock Low Pulse Width
tCL
-
-
-
ns
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
tAS
-
-
-
ns
tSS
-
-
-
ns
tDS
-
-
-
ns
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
tWS
tADVS
tCSS
tAH
-
-
-
ns
-
-
-
ns
-
-
-
ns
-
-
-
ns
tSH
-
-
-
ns
tDH
-
-
-
ns
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
tADVH
tCSH
tPDS
tPUS
-
-
-
ns
-
-
-
ns
-
-
-
ns
-
-
-
cycle
cycle
ZZ Low to Power Up
2
-
2
-
2
-
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
- 11 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
- 12 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
- 13 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
- 14 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
- 15 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
- 16 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 512Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.
I/O[0:71]
Data
Address
A[0:19]
A[19]
A[0:18]
A[19]
A[0:18]
Address Data
Address Data
CS
CS
CLK
2
CS
CS
2
2
2
512Kx36
SPB
SRAM
CLK
ADSC
WEx
OE
512Kx36
SPB
SRAM
CLK
ADSC
WEx
OE
Microprocessor
Address
CLK
(Bank 0)
(Bank 1)
Cache
Controller
CS1
CS
1
ADV ADSP
ADV ADSP
ADS
(Refer to non-interleave write timing for interleave write timing)
INTERLEAVE READ TIMING
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
tAH
A1
A2
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS
2
, and Bank 1 selected by CS
2
tADVS
tADVH
tOE
tHZC
tLZOE
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes : n = 14 32K depth ,
15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
Don¢t Care
Undefined
- 17 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 1Mx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic.
I/O[0:71]
Data
Address
A[20]
A[20]
A[0:20]
A[0:19]
A[0:19]
Address Data
CS
CS
Address Data
CS
CS
CLK
2
2
2
2
Microprocessor
CLK
ADSC
WEx
OE
1Mx18
SPB
SRAM
CLK
ADSC
WEx
OE
1Mx18
SPB
SRAM
Address
CLK
(Bank 0)
(Bank 1)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
(Refer to non-interleave write timing for interleave write timing)
INTERLEAVE READ TIMING
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
tAH
A1
A2
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS
2
, and Bank 1 selected by CS
2
tADVS
tADVH
tOE
tLZOE
tHZC
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes : n = 14 32K depth ,
15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
20 2M depth
Undefined
Don¢t Care
- 18 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
PACKAGE DIMENSIONS
100-TQFP-1420A
Units ; millimeters/Inches
22.00 ±0.30
20.00 ±0.20
0~8°
0.10
0.05
0.127+-
16.00 ± 0.30
0.10 MAX
14.00 ±0.20
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
- 19 -
February 2001
Rev 2.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
119 BGA PACKAGE DIMENSIONS
1.27
1.27
14.00±0.10
22.00±0.10
Indicator of
Ball(1A) Location
20.50±0.10
C0.70
C1.00
0.750±0.15
1.50REF
0.60±0.10
0.60±0.10
NOTE :
1. All Dimensions are in Millimeters.
2. Solder Ball to PCB Offset : 0.10 MAX.
3. PCB to Cavity Offset : 0.10 MAX.
12.50±0.10
- 20 -
February 2001
Rev 2.0
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