K7A803609B-QC25 [SAMSUNG]

256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM; 256Kx36和512Kx18位同步流水线突发SRAM


型号：	K7A803609B-QC25
厂家：	SAMSUNG
描述：	256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM 256Kx36和512Kx18位同步流水线突发SRAM 存储内存集成电路静态存储器时钟
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中文：	中文翻译
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K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

Document Title

256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM

Revision History

Rev. No.

History

Draft Date

Remark

0.0

0.1

0.2

0.3

1.0

Initial draft

May. 18 . 2001

Preliminary

1. Delete pass- through

June. 26. 2001 Preliminary

1. Add x32 org part and industrial temperature part

1. change scan order(1) form 4T to 6T at 119BGA(x18)

Aug. 11. 2001

Aug. 28. 2001

Nov. 16. 2001

Preliminary

Final

1. Final spec release

2. Change ISB2 form 50mA to 60mA

2.0

2.1

3.0

Remove tCYC 225MHz(-22)

1. Delete 119BGA package

April. 01. 2002 Final

April. 04. 2003 Final

1. Remove x32 organization

2. Remove -20 speed bin

Nov. 17. 2003

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 1 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

8Mb SB/SPB Synchronous SRAM Ordering Information

Speed

Org.

Part Number

Mode

VDD

FT ; Access Time(ns)

PKG

Temp

Pipelined ; Cycle Time(MHz)

K7B801825B-QC(I)65/75

K7A801800B-QC(I)16/14

K7A801809B-QC(I)25

K7B803625B-QC(I)65/75

K7A803600B-QC(I)16/14

K7A803609B-QC(I)25

3.3

6.5/7.5 ns

167/138 MHz

250 MHz

Commercial

Temperature

Range

512Kx18

SPB(2E1D)

100TQFP

6.5/7.5 ns

Industrial

Temperature

Range

256Kx36

SPB(2E1D)

167/138 MHz

250 MHz

- 2 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

256Kx36 & 512Kx18-bit Synchronous Pipelined Burst SRAM

FEATURES

GENERAL DESCRIPTION

• Synchronous Operation.

The K7A803609B and K7A801809B are 9,437,184-bit Syn-

chronous Static Random Access Memory designed for high

performance second level cache of Pentium and Power PC

based System.

• 2 Stage Pipelined operation with 4 Burst.

• On-Chip Address Counter.

• Self-Timed Write Cycle.

• On-Chip Address and Control Registers.

• 3.3V+0.165V/-0.165V Power Supply.

• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O

or 2.5V+0.4V/-0.125V for 2.5V I/O

It is organized as 256K(512K) words of 36(18) bits and inte-

grates address and control registers, a 2-bit burst address

counter and added some new functions for high perfor-

mance cache RAM applications; GW, BW, LBO, ZZ. Write

cycles are internally self-timed and synchronous.

Full bus-width write is done by GW, and each byte write is

performed by the combination of WEx and BW when GW is

high. And with CS1 high, ADSP is blocked to control signals.

Burst cycle can be initiated with either the address status

processor(ADSP) or address status cache controller(ADSC)

inputs. Subsequent burst addresses are generated inter-

nally in the system′s burst sequence and are controlled by

the burst address advance(ADV) input.

LBO pin is DC operated and determines burst sequence(lin-

ear or interleaved).

ZZ pin controls Power Down State and reduces Stand-by

current regardless of CLK.

The K7A803609B and K7A801809B are fabricated using

SAMSUNG′s high performance CMOS technology and is

available in a 100pin TQFP and Multiple power and ground

pins are utilized to minimize ground bounce.

• 5V Tolerant Inputs Except I/O Pins.

• Byte Writable Function.

• Global Write Enable Controls a full bus-width write.

• Power Down State via ZZ Signal.

• LBO Pin allows a choice of either a interleaved burst or a linear

burst.

• Three Chip Enables for simple depth expansion with No Data

Contention only for TQFP ; 2cycle Enable, 1cycle Disable.

• Asynchronous Output Enable Control.

• ADSP, ADSC, ADV Burst Control Pins.

• TTL-Level Three-State Output.

• 100-TQFP-1420A

• Operating in commeical and industrial temperature range.

FAST ACCESS TIMES

PARAMETER

Cycle Time

Symbol

tCYC

tCD

-25

4.0

2.6

Unit

Clock Access Time

Output Enable Access Time

tOE

LOGIC BLOCK DIAGRAM

CLK

LBO

256Kx36 , 512Kx18

BURST CONTROL

LOGIC

BURST

MEMORY

ADDRESS

ADV

A′0

~A′1

ARRAY

ADSC

COUNTER

or A²

~A¹1⁷8

ADDRESS

or A⁰

~A1¹8⁷

ADSP

DATA-IN

OUTPUT

CONTROL

LOGIC

BUFFER

WEx

(x=a,b,c,d or a,b)

DQa0 ~ DQd7 or DQa0 ~ DQb7

DQPa,DQPb

DQPa ~ DQPd

- 3 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

PIN CONFIGURATION(TOP VIEW)

DQPb

DQPc

DQb7

DQc0

DQb6

DQc1

VDDQ

VSSQ

DQb5

DQc2

DQb4

DQc3

DQb3

DQc4

DQb2

DQc5

VSSQ

VDDQ

DQb1

DQc6

100 Pin TQFP

DQb0

VSS

DQc7

N.C.

(20mm x 14mm)

N.C.

VDD

N.C.

VSS

DQa7

DQa6

VDDQ

VSSQ

DQa5

DQa4

DQa3

DQa2

VSSQ

VDDQ

DQa1

DQa0

DQPa

DQd0

DQd1

VDDQ

VSSQ

DQd2

DQd3

DQd4

DQd5

VSSQ

VDDQ

DQd6

DQd7

DQPd

K7A803609B(256Kx36)

PIN NAME

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A17

Address Inputs

32,33,34,35,36,37,43 VDD

44,45,46,47,48,49,50 VSS

Power Supply(+3.3V)

Ground

15,41,65,91

17,40,67,90

81,82,99,100

N.C.

No Connect

14,16,38,39,42,66

ADV

ADSP

ADSC

CLK

CS1

Burst Address Advance

Address Status Processor 84

Address Status Controller 85

DQa0~a7

DQb0~b7

DQc0~c7

DQd0~d7

DQPa~Pd

Data Inputs/Outputs

52,53,56,57,58,59,62,63

68,69,72,73,74,75,78,79

2,3,6,7,8,9,12,13

18,19,22,23,24,25,28,29

51,80,1,30

Clock

Chip Select

CS2

WEx(x=a,b,c,d) Byte Write Inputs

93,94,95,96

VDDQ

VSSQ

Output Power Supply

(2.5V or 3.3V)

Output Ground

4,11,20,27,54,61,70,77

5,10,21,26,55,60,71,76

Output Enable

Global Write Enable

Byte Write Enable

Power Down Input

Burst Mode Control

LBO

Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

2. The pin 42 is reserved for address bit for the 16Mb .

- 4 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

PIN CONFIGURATION(TOP VIEW)

A10

N.C.

VDDQ

VSSQ

N.C.

DQPa

DQa7

DQa6

VSSQ

VDDQ

DQa5

DQa4

VSS

N.C.

VDDQ

VSSQ

N.C.

DQb0

DQb1

VSSQ

VDDQ

DQb2

DQb3

N.C.

100 Pin TQFP

(20mm x 14mm)

N.C.

VDD

N.C.

VSS

DQb4

DQb5

VDDQ

VSSQ

DQb6

DQb7

DQPb

N.C.

DQa3

DQa2

VDDQ

VSSQ

DQa1

DQa0

N.C.

VSSQ

VDDQ

N.C.

K7A801809B(512Kx18)

VSSQ

VDDQ

N.C.

PIN NAME

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A18

Address Inputs

32,33,34,35,36,37,43 VDD

44,45,46,47,48,49,50 VSS

Power Supply(+3.3V) 15,41,65,91

Ground

17,40,67,90

80,81,82,99,100

N.C.

No Connect

1,2,3,6,7,14,16,25,28,29,

30,38,39,42,51,52,53,56,

57,66,75,78,79,95,96

ADV

ADSP

ADSC

CLK

CS1

CS2

WEx

Burst Address Advance

Address Status Processor 84

Address Status Controller

Clock

DQa0 ~ a7

DQb0 ~ b7

DQPa, Pb

VDDQ

Data Inputs/Outputs

58,59,62,63,68,69,72,73

8,9,12,13,18,19,22,23

74,24

Chip Select

Output Power Supply 4,11,20,27,54,61,70,77

(2.5V or 3.3V)

Output Ground

Byte Write Inputs

Output Enable

93,94

VSSQ

5,10,21,26,55,60,71,76

Global Write Enable

Byte Write Enable

Power Down Input

Burst Mode Control

LBO

Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

2. The pin 42 is reserved for address bit for the 16Mb .

- 5 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

FUNCTION DESCRIPTION

The K7A803609B and K7A801809B are synchronous SRAM designed to support the burst address accessing sequence of the

Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and

duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.

The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.

When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ

returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.

Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address

register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-

ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-

ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output

pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address

increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to

control signals by disabling CS1.

All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx

when GW is high.

Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-

ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled

Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the

next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte

write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7

and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-

ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;

ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).

Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external

address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state

of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is

selected.

BURST SEQUENCE TABLE

(Interleaved Burst)

Case 4

Case 1

Case 2

Case 3

LBO PIN

HIGH

First Address

Fourth Address

TABLE

(Linear Burst)

Case 4

LBO PIN

LOW

First Address

Fourth Address

Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

ASYNCHRONOUS TRUTH TABLE

OPERATION

I/O STATUS

High-Z

Notes

1. X means "Don′t Care".

2. ZZ pin is pulled down internally

Sleep Mode

3. For write cycles that following read cycles, the output buffers must be

disabled with OE, otherwise data bus contention will occur.

4. Sleep Mode means power down state of which stand-by current does

not depend on cycle time.

Read

High-Z

Write

Din, High-Z

High-Z

5. Deselected means power down state of which stand-by current

depends on cycle time.

Deselected

- 6 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

CS1

CS2

CS2 ADSP ADSC ADV WRITE CLK

ADDRESS ACCESSED

N/A

OPERATION

Not Selected

↑

N/A

Not Selected

N/A

Not Selected

N/A

Not Selected

N/A

Not Selected

External Address

Next Address

Current Address

Begin Burst Read Cycle

Begin Burst Write Cycle

Begin Burst Read Cycle

Continue Burst Read Cycle

Continue Burst Write Cycle

Suspend Burst Read Cycle

Suspend Burst Write Cycle

NOTE : 1. X means "Don′t Care".

2. The rising edge of clock is symbolized by ↑.

3. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

4. Operation finally depends on status of asynchronous input pins(ZZ and OE).

WRITE TRUTH TABLE(x36)

WEa

WEb

WEc

WEd

OPERATION

READ

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c and d

WRITE ALL BYTEs

Notes : 1. X means "Don′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).

WRITE TRUTH TABLE(x18)

WEa

WEb

OPERATION

READ

WRITE BYTE a

WRITE BYTE b

WRITE ALL BYTEs

Notes : 1. X means "Don′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).

- 7 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Voltage on VDD Supply Relative to VSS

Voltage on VDDQ Supply Relative to VSS

Voltage on Input Pin Relative to VSS

Voltage on I/O Pin Relative to VSS

Power Dissipation

SYMBOL

VDD

RATING

-0.3 to 4.6

VDD

UNIT

VDDQ

VIN

-0.3 to VDD+0.3

-0.3 to VDDQ+0.3

1.6

VIO

Storage Temperature

TSTG

TOPR

TBIAS

-65 to 150

0 to 70

°C

Commercial

Industrial

Operating Temperature

-40 to 85

-10 to 85

Storage Temperature Range Under Bias

*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING CONDITIONS at 3.3V I/O(0°C ≤ TA ≤ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

VDD

MIN

3.135

Typ.

3.3

MAX

3.465

UNIT

VDDQ

VSS

* The above parameters are also guaranteed at industrial temperature range.

OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

VDD

MIN

3.135

2.375

Typ.

3.3

2.5

MAX

3.465

2.9

UNIT

VDDQ

VSS

* The above parameters are also guaranteed at industrial temperature range.

CAPACITANCE*(TA=25°C, f=1MHz)

PARAMETER

SYMBOL

CIN

TEST CONDITION

VIN=0V

MIN

MAX

UNIT

Input Capacitance

Output Capacitance

COUT

VOUT=0V

*Note : Sampled not 100% tested.

- 8 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)

PARAMETER

SYMBOL

TEST CONDITIONS

VDD = Max ; VIN=VSS to VDD

MIN

-2

MAX

UNIT NOTES

µA

Input Leakage Current(except ZZ)

Output Leakage Current

IIL

IOL

Output Disabled, VOUT=VSS to VDDQ

-2

Device Selected, IOUT=0mA,

Operating Current

Standby Current

ICC

-25

470

1,2

ZZ≤VIL , Cycle Time ≥ tCYC Min

Device deselected, IOUT=0mA,

ZZ≤VIL, f=Max,

All Inputs≤0.2V or ≥ VDD-0.2V

ISB

170

Device deselected, IOUT=0mA, ZZ≤0.2V,

f = 0, All Inputs=fixed (VDD-0.2V or 0.2V)

ISB1

ISB2

100

Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,

f=Max, All Inputs≤VIL or ≥VIH

Output Low Voltage(3.3V I/O)

Output High Voltage(3.3V I/O)

Output Low Voltage(2.5V I/O)

Output High Voltage(2.5V I/O)

Input Low Voltage(3.3V I/O)

Input High Voltage(3.3V I/O)

Input Low Voltage(2.5V I/O)

Input High Voltage(2.5V I/O)

VOL

VOH

VOL

VOH

VIL

IOL=8.0mA

IOH=-4.0mA

IOL=1.0mA

IOH=-1.0mA

0.4

2.4

0.4

2.0

-0.3*

2.0

-0.3*

1.7

0.8

VDD+0.3

0.7

VIH

VIL

VIH

VDD+0.3

Notes : The above parameters are also guaranteed at industrial temperature range.

1. Reference AC Operating Conditions and Characteristics for input and timing.

2. Data states are all zero.

3. In Case of I/O Pins, the Max. V^IH=VDDQ+0.3V.

VIH

VSS

VSS-1.0V

20% tCYC(MIN)

TEST CONDITIONS

(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, T

=0to70 C)

Parameter

Value

0 to 3.0V

0 to 2.5V

1.0V/ns

1.5V

Input Pulse Level(for 3.3V I/O)

Input Pulse Level(for 2.5V I/O)

Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)

Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)

Input and Output Timing Reference Levels for 3.3V I/O

Input and Output Timing Reference Levels for 2.5V I/O

Output Load

VDDQ/2

See Fig. 1

* The above parameters are also guaranteed at industrial temperature range.

- 9 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

Output Load(A)

Output Load(B),

(for tLZC, tLZOE, tHZOE & tHZC)

+3.3V for 3.3V I/O

RL=50Ω

Dout

/+2.5V for 2.5V I/O

VL=1.5V for 3.3V I/O

319Ω / 1667Ω

VDDQ/2 for 2.5V I/O

30pF*

Dout

Zo=50Ω

353Ω / 1538Ω

5pF*

* Including Scope and Jig Capacitance

Fig. 1

AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)

-25

PARAMETER

Symbol

UNIT

MIN

4.0

MAX

Cycle Time

tCYC

tCD

Clock Access Time

2.6

Output Enable to Data Valid

Clock High to Output Low-Z

Output Hold from Clock High

tOE

2.6

tLZC

tOH

0.8

Output Enable Low to Output Low-Z

Output Enable High to Output High-Z

Clock High to Output High-Z

tLZOE

tHZOE

tHZC

tCH

2.6

0.8

1.7

1.2

0.3

2.6

Clock High Pulse Width

Clock Low Pulse Width

tCL

Address Setup to Clock High

tAS

Address Status Setup to Clock High

Data Setup to Clock High

tSS

tDS

Write Setup to Clock High (GW, BW, WEX)

Address Advance Setup to Clock High

Chip Select Setup to Clock High

Address Hold from Clock High

Address Status Hold from Clock High

Data Hold from Clock High

tWS

tADVS

tCSS

tAH

tSH

tDH

Write Hold from Clock High (GW, BW, WEX)

Address Advance Hold from Clock High

Chip Select Hold from Clock High

ZZ High to Power Down

tWH

tADVH

tCSH

tPDS

tPUS

cycle

ZZ Low to Power Up

Notes : 1.The above parameters are also guaranteed at industrial temperature range.

2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS

is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.

4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.

- 10 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

- 11 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

- 12 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

- 13 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

- 14 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

- 15 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

APPLICATION INFORMATION

DEPTH EXPANSION

The Samsung 256Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.

This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.

I/O[0:71]

Data

Address

A[0:18]

A[18]

A[0:17]

A[18]

A[0:17]

Address Data

CLK

CS2

256Kx36

SPB

CLK

ADSC

WEx

256Kx36

SPB

CLK

ADSC

WEx

Microprocessor

Address

CLK

SRAM

(Bank 0)

(Bank 1)

Cache

Controller

CS1

ADV ADSP

ADS

INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)

(ADSP CONTROLLED , ADSC=HIGH)

Clock

tSS

tSH

ADSP

tAS

tAH

ADDRESS

[0:n]

tWS

tWH

WRITE

tCSS

tCSH

CS1

Bank 0 is selected by CS2, and Bank 1 deselected by CS2

An+1

ADV

Bank 0 is deselected by CS², and Bank 1 selected by CS2

tADVS

tADVH

tOE

tHZC

tLZOE

Data Out

(Bank 0)

Q1-1

Q1-2

Q1-3

Q1-4

tCD

tLZC

Data Out

(Bank 1)

Q2-1

Q2-2

Q2-3

Q2-4

*Notes : n = 14 32K depth ,

15 64K depth

Don′t Care

Undefined

16 128K depth , 17 256K depth

18 512K depth

- 16 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

APPLICATION INFORMATION

DEPTH EXPANSION

The Samsung 512Kx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.

This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.

I/O[0:71]

Data

Address

A[0:18]

A[19]

A[0:19]

A[0:18]

A[19]

Address Data

CLK

CS2

Microprocessor

512Kx18

SPB

CLK

ADSC

WEx

512Kx18

SPB

CLK

ADSC

WEx

Address

CLK

SRAM

(Bank 0)

(Bank 1)

Cache

Controller

CS1

ADV ADSP

ADS

INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)

(ADSP CONTROLLED , ADSC=HIGH)

Clock

tSS

tSH

ADSP

tAS

tAH

ADDRESS

[0:n]

tWS

tWH

WRITE

tCSS

tCSH

CS1

Bank 0 is selected by CS2, and Bank 1 deselected by CS2

An+1

ADV

Bank 0 is deselected by CS², and Bank 1 selected by CS2

tADVS

tADVH

tOE

tHZC

tLZOE

Data Out

(Bank 0)

Q1-1

Q1-2

Q1-3

Q1-4

tCD

tLZC

Data Out

(Bank 1)

Q2-1

Q2-2

Q2-3

Q2-4

*Notes : n = 14 32K depth ,

15 64K depth

Undefined

Don′t Care

16 128K depth , 17 256K depth

18 512K depth , 19 1M depth

- 17 -

Nov. 2003

Rev 3.0

K7A803609B

K7A801809B

256Kx36 & 512Kx18 Synchronous SRAM

PACKAGE DIMENSIONS

Units ; millimeters/Inches

100-TQFP-1420A

22.00

20.00

0.30

0.20

0~8°

+ 0.10

- 0.05

0.127

16.00

14.00

0.30

0.10 MAX

0.20

(0.83)

0.50 ±0.10

0.65

(0.58)

0.30

±0.10

0.10 MAX

1.40

±0.10

1.60 MAX

0.05 MIN

0.50 ±0.10

- 18 -

Nov. 2003

Rev 3.0

K7A803609B-QC25 [SAMSUNG]

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