K7D323674A-GC370 [SAMSUNG]
DDR SRAM, 1MX36, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, BGA-153;
| 型号： | K7D323674A-GC370 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR SRAM, 1MX36, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, BGA-153 双倍数据速率 静态存储器 内存集成电路 |
| 文件： | 总18页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
32Mb C-die DDR SRAM Specification
153BGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev 0.0
Nov. 2005
- 1 -
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
Document Title
32M DDR SYNCHRONOUS SRAM
Revision History
RevNo.
History
DraftData
Remark
Rev. 0.0
Initial document.
Nov. 2005
Advance
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
Rev 0.0
Nov. 2005
- 2 -
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
FEATURES
• Registered Outputs.
• 1Mx36 or 2Mx18 Organizations.
• 1.8~2.5V VDD/1.5V ~1.8VDDQ.
• HSTL Input and Outputs.
• Double and Single Data Rate Burst Read and Write.
• Burst Count Controllable With Max Burst Length of 4
• Interleaved and Linear Burst mode support
• Bypass Operation Support
• Single Differential HSTL Clock.
• Synchronous Pipeline Mode of Operation with Self-Timed
Late Write.
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1)
• 153(9x17) Ball Grid Array Package(14mmx22mm)
• No Output enable support.
• Free Running Active High and Active Low Echo Clock Output
Pin.
• Registered Addresses, Burst Control and Data Inputs.
GENERAL DESCRIPTION
The K7D323674C and K7D321874C are 37,748,736 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
1,048,576 words by 36 bits for K7D323674C and 2,097,152 words by 18 bits for K7D321874C, fabricated using Samsung's
advanced CMOS technology.
Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At
the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after
write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and
falling edge of K clock for a double data rate (DDR) write operations.
Data outputs are updated from output registers off the rising edges of K clock for SDR read operations and off the rising and falling
edges of K clock for DDR read operations. Free running echo clocks are supported which are representative of data output access
time for all SDR and DDR operations.
The chip is operated with 1.8~2.5V power supply and is compatible with HSTL input and output. The package is 9x17(153) Ball Grid
Array balls on a 1.27mm pitch.
ORDERING INFORMATION
Organization
Maximum Frequency
Part Number
400MHz
375MHz
333MHz
400MHz
375MHz
333MHz
K7D323674C-H(G)C40
K7D323674C-H(G)C37
K7D323674C-H(G)C33
K7D321874C-H(G)C40
K7D321874C-H(G)C37
K7D321874C-H(G)C33
1Mx36
2Mx18
* G : Lead free package
Rev 0.0
Nov. 2005
- 3 -
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
FUNCTIONAL BLOCK DIAGRAM
SA[0:20]( or SA[0:21])
Address
Memory Array
1Mx36
20(or 21)
Register
18(or 19)
2:1
Dec.
MUX
or
(Burst Address)
CE
(2Mx18)
Clock
Data Out
36(or 18)x2
K,K
Data In
Buffer
Burst
36(or18)x2
Counter
Comparator
S/A Array
W/D
Advance
Array
(Burst Write
Address)
B
1
3
Control
SD/DD
Write
Address
Register
B
36(or 18)x2
36(or18)x2
Write Buffer
20(or 21)
18(or 19)
(2 stage)
CE
2 : 1 MUX
Synchronous
Select
CE
Strobe_out
&
B2
Echo Clock
Output
Output
Buffer
Data In
Register
(2 stage)
R/W
R/W control
Data Output Strobe
Data Output Enable
State Machine
LD
Internal
Clock
36(or 18)
DQ
Generator
XDIN
CQ,CQ
PIN DESCRIPTION
Pin Name
Pin Description
Pin Name
TCK
TMS
TDI
Pin Description
K, K
SA
Differential Clocks
JTAG Test Clock
Synchronous Address Input
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
HSTL Input Reference Voltage
Power Supply
SA0, SA1
DQ
Synchronous Burst Address Input (SA0 = LSB)
Synchronous Data I/O
TDO
VREF
VDD
CQ, CQ
B1
Differential Output Echo Clocks
Load External Address
B2
Burst R/W Enable
VDDQ
VSS
Output Power Supply
GND
B3
Single/Double Data Selection
Linear Burst Order
LBO
ZQ
NC
No Connection
Output Driver Impedance Control Input
Rev 0.0
Nov. 2005
- 4 -
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7D323674C(1Mx36)
1
2
3
SA
4
SA
5
ZQ
6
SA
7
SA
8
9
A
B
C
D
E
F
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
VDDQ
DQ
VDDQ
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
SA
VSS
SA
B1
VSS
SA
VDDQ
DQ
SA
SA
SA
SA
VDDQ
DQ
SA
Vss(5)
VDD
VDD
VSS
VDD
VDD
VSS
LBO
VDD
VDD
VSS
SA
VDD
VREF
VDD
K
Vss(6)
VDD
VDD
VSS
SA
VDDQ
CQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
NC*
VDD(4)
SA
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
SA
VDDQ
CQ
G
H
J
VDDQ
DQ
VDDQ
DQ
K
VDD
VDD
VSS
VDDQ
DQ
VDD
B2
VDDQ
DQ
K
L
VDDQ
CQ
B3
MODE(7)
VDD
VDD
VSS
VDDQ
CQ
M
N
P
R
T
VDD
VREF
VDD(2)
SA1
SA0
TCK
VDDQ
DQ
VDDQ
DQ
VDDQ
DQ
SA
VDD(3)
SA
VDDQ
DQ
VSS
TDI
VSS
U
VDDQ
TMS
TDO
NC
VDDQ
K7D321874C(2Mx18)
1
2
3
SA
4
SA
5
ZQ
6
SA
7
SA
8
9
A
B
C
D
E
F
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
VDDQ
DQ
VDDQ
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
SA
VSS
SA
B1
VSS
SA
VDDQ
NC
SA
SA
SA
SA
VDDQ
DQ
SA
Vss(5)
VDD
VDD
VSS
VDD
VDD
VSS
LBO
VDD
VDD
VSS
SA
VDD
VREF
VDD
K
Vss(6)
VDD
VDD
VSS
SA
VDDQ
CQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
SA
VDDQ
NC
G
H
J
VDDQ
NC
VSS
DQ
VSS
NC
VDDQ
DQ
K
VDD
VDD
VSS
VDDQ
DQ
VDD
B2
VDDQ
NC
K
L
VDDQ
NC
VSS
DQ
VSS
SA
B3
MODE(7)
VDD
VDD
VSS
VDDQ
CQ
M
N
P
R
T
VDD
VREF
VDD(2)
SA1
SA0
TCK
VDDQ
DQ
VDDQ
NC
VDDQ
NC
VDD(4)
SA
SA
VDD(3)
SA
VDDQ
DQ
VSS
TDI
VSS
U
VDDQ
TMS
TDO
NC
VDDQ
(1) Variable address see "Variable address assignment table"
(2) Variable address see "Variable address assignment table"
(3) Variable address see "Variable address assignment table"
(4) Variable address see "Variable address assignment table"
(5) Variable address see "Variable address assignment table"
(6) Variable address see "Variable address assignment table"
(7) Internally NC
Rev 0.0
Nov. 2005
- 5 -
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
VARIABLE ADDRESS ASSIGNMENT TABLE
Ball 5C
Ball 5P
Ball 7R
Ball 3R
(4)
Ball 4D
(5)
Ball 6D
(6)
Density
(1)
(2)
(3)
32 Mb
64 Mb
SA
SA
NC
SA
NC
SA
VDD
SA
SA
SA
SA
SA
VDD
VDD
SA
VDD
VDD
SA
Vss
Vss
Vss
Vss
SA
SA
Vss
Vss
Vss
Vss
SA
SA
144 Mb
288 Mb
576 Mb
1152 Mb
SA
SA
SA
SA
SA
SA
NOTE : - SRAM density definition beyond 144Mb will include the parity bits.
Rev 0.0
Nov. 2005
- 6 -
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
Read Operation(Single and Double)
During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is
read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of
K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal
array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by
burst order off the second rising and falling edge of K clock.
Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.
To avoid data contention,at least two NOP operations are required between the last read and the first write operation.
Write Operation(Late Write)
During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered
at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of
K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are
stored in the data in registers until the next write operation, and only at the next write operation are data inputs fully written into
SRAM array.
Echo clock operation
Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation
only when K clock is in the stop mode.
Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture
data outputs.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array.
Programmable Impedance Output Driver
The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and
are equal to RQ/5. For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by
test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Output driver imped-
ance is updated every 64 clock cycles of Non-Read operation (Write or NOP) but since the echo clock drivers are in operation even
during Non-Read operation, the impedance is update only the drivers are not in operation. Therefore impedance updates for "0s" or
pull down drivers occur whenever the echo clock driver is driving "1s" or vice versa. Furthermore, to guarantee optimum output driver
impedance after power up, the SRAM need 2048 deselect (or write) cycles.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
Rev 0.0
Nov. 2005
- 7 -
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
TRUTH TABLE
K
↑
↑
↑
↑
↑
↑
B1
H
L
B2
L
B3
X
H
L
DQ
Hi-Z
DOUT
DOUT
DIN
Operation
No Operation, Pipeline High-Z
Load Address, Single Read
Load Address, Double Read
Load Address, Single Write
Load Address, Double Write
Increment Address, Continue
H
H
L
L
L
H
L
L
L
DIN
H
H
X
B
NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".
- K & K are complementary.
OUTPUT TRISTATE TRUTH TABLE
K
↑
↑
Operation
DQ (n)
DQ (n+1)
High-Z
Write (B2=L)
X
X
Deselect (NOP) (B1=H, B2=L)
High-Z
BURST SEQUENCE TABLE
4 Burst Operation for Interleaved Burst (LBO = VDDQ)
Interleaved Burst
Case 1
Case 2
Case 3
Case 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
NOTE : - For Interleave Burst LBO = VDDQ is recommended. If LBO = VDD, it must not exceed 2.63V.
4 Burst Operation for Linear Burst (LBO = VSS)
Case 1
Case 2
Case 3
Case 4
Linear Burst Mode
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Rev 0.0
Nov. 2005
- 8 -
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
BUS CYCLE STATE DIAGRAM
LOAD
NEW ADDRESS
READ
SDR
WRITE
SDR
READ
DDR
WRITE
DDR
INCREMENT
ADDRESS
INCREMENT
ADDRESS
INCREMENT
ADDRESS
INCREMENT
ADDRESS
POWER
UP
NO OP
NOTE :
1. State transitions ; B1 =(Load Address), B1=(Increment Address, Continue)
B2 =(Read), B2 =(Write)
B3 =(Single Data Rate), B3 =(Double Data Rate)
Rev 0.0
Nov. 2005
- 9 -
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Core Supply Voltage Relative to VSS
Output Supply Voltage Relative to VSS
Voltage on any pin Relative to VSS
Output Short-Circuit Current(per I/O)
Storage Temperature
Symbol
VDD
VDDQ
VIN
Value
Unit
V
-0.5 to 3.13
-0.5 to 2.3
V
-0.5 to VDDQ+0.5 (2.3V MAX)
V
IOUT
TSTR
TJ
25
-55 to 125
110
mA
°C
°C
W
Maximum Junction Temperature
Maximum Power Dissipation
PD
3.0
NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level Voltage
Input Low Level Voltage
Input Reference Voltage
Symbol
VDD
Min
1.7
Typ
2.5
1.5
-
Max
2.6
Unit
V
Note
VDDQ
VIH
1.4
1.9
V
VREF+0.1
-0.3
VDDQ+0.3
VREF-0.1
1.0
V
1, 2
1, 3
VIL
-
V
VREF
0.68
0.75
V
NOTE :1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=2.6V (2.1V for DQs) (pulse width ≤ 20% of cycle time).
3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.0V (-0.5V for DQs) (pulse width ≤ 20% of cycle time).
DC CHARACTERISTICS
Min
Max
Parameter
Symbol
Unit
Note
IDD40
IDD37
IDD33
Average Power Supply Operating Current(x36)
(Cycle time = tKHKH min)
-
TBD
mA
1,2
IDD40
IDD37
IDD33
Average Power Supply Operating Current(x18)
(Cycle time = tKHKH min)
-
TBD
mA
1,2
1
Stop Clock Standby Current
(VIN=VDD-0.2V or 0.2V fixed, K=Low, K=High)
Input Leakage Current
(VIN=VSS or VDDQ)
Output Leakage Current
(VOUT=VSS or VDDQ)
ISB1
ILI
-
TBD
mA
µA
µA
-3
-5
3
5
ILO
Output High Voltage(Programmable Impedance Mode)
Output Low Voltage(Programmable Impedance Mode)
Output High Voltage(IOH=-0.1mA)
VOH1
VOL1
VOH2
VOL2
VDDQ/2
VSS
VDDQ-0.2
VSS
VDDQ
VDDQ/2
VDDQ
0.2
V
V
V
V
3
4
Output Low Voltage(IOL=0.1mA)
NOTE :1. Minimum cycle. IOUT=0mA.
2. 50% read cycles.
3. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175Ω ≤ RQ ≤ 300Ω.
4. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175Ω ≤ RQ ≤ 300Ω.
Rev 0.0
Nov. 2005
- 10
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
PIN CAPACITANCE
Parameter
Input Capacitance
Symbol
CIN
COUT
Test Condition
VIN=0V
TYP
-
-
Max
TBD
TBD
Unit
pF
pF
Data Output Capacitance
VOUT=0V
NOTE : Periodically sampled and not 100% tested.(TA=25°C, f=500MHz)
AC INPUT CHARACTERISTICS
Parameter
AC Input Logic High
AC Input Logic Low
Clock Input Differential Voltage
VREF Peak-to-Peak AC Voltage
Symbol
VIH (AC)
VIL (AC)
VDIF (AC)
VREF (AC)
Min
VREF + 0.4
Max
Unit
Note
V
V
V
V
-
-
-
-
VREF - 0.4
0.8
5% VREF (DC)
AC INPUT DEFINITION
CK
V
(AC)
DIF
CK
VIH(AC)
VREF
Setup
Time
Hold
Time
VIL(AC)
AC TEST CONDITIONS(TA=0 to 70°C, VDD=2.37 -2.63V, VDDQ=1.5V)
Parameter
Input High/Low Level
Input Reference Level
Input Rise/Fall Time
Symbol
VIH/VIL
VREF
Value
1.25/0.25
0.75
0.5/0.5
0.75
Unit
V
V
ns
V
V
Note
-
-
-
-
-
-
TR/TF
Output Timing Reference Level
Clock Input Timing Reference Level
Output Load
Cross Point
See Below
Rev 0.0
Nov. 2005
- 11
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
AC TEST OUTPUT LOAD
50Ω
0.75V
0.75V
50Ω
50Ω
5pF
0.75V
25Ω
DQ
50Ω
5pF
AC TIMING CHARACTERISTICS
-40
-37
-33
PARAMETER
SYMBOL
UNITS NOTES
MIN
MAX
MIN
MAX
MIN
MAX
Clock
1
Clock Cycle Time
tKHKH
tKHKL
tKLKH
2.50
1.15
1.15
5.00
2.67
1.25
1.25
6.00
3.00
1.40
1.40
6.00
ns
ns
ns
Clock High Pulse Width
Clock Low Pulse Width
Setup Times
Address Setup Time
tAVKH
tBVKH
tDVKX
0.30
0.30
0.20
0.33
0.33
0.25
0.35
0.35
0.30
ns
ns
ns
Control(B1,B2,B3) Setup Time
Data Setup Time
2
2
Hold Times
Address Hold Time
tKHAX
tKHBX
tKXDX
0.30
0.30
0.20
0.33
0.33
0.25
0.35
0.35
0.30
ns
ns
ns
Control(B1,B2,B3) Hold Time
Data Hold Time
Output Times
tKHKL-0.1
tKLKH-0.1
1.0
tKHKL+0.1
tKLKH+0.1
2.5
tKHKL-0.1
tKLKH-0.1
1.0
tKHKL+0.1
tKLKH+0.1
2.5
tKHKL-0.1
tKLKH-0.1
1.0
tKHKL+0.1
tKLKH+0.1
2.5
2
2
3
3
Echo Clock High Pulse Width
Echo Clock Low Pulse Width
Clock Crossing to Echo Clock
Clock Crossing to Echo Clock
Echo Clock High to Output Valid
Echo Clock Low to Output Valid
Echo Clock High to Output Hold
Echo Clock Low to Output Hold
Echo Clock High to Output High-Z
Echo Clock High to Output Low-Z
tCHCL
tCLCH
tCXCH
tCXCL
tCHQV
tCLQV
tCHQX
tCLQX
tCHQZ
tCHLZ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.0
2.5
1.0
2.5
1.0
2.5
0.20
0.20
0.20
0.20
0.20
0.20
-0.20
-0.20
-0.20
-0.20
-0.20
-0.20
0.20
0.20
0.20
-0.20
-0.20
-0.20
Notes: 1. The maximum cycle time must be limited to guarantee AC timing specification.
2. This parameter is guaranteed by design, and may not be tested at values shown in the table.
3. This parameter refers to CQ and CQ rising and falling edges.
4. This parameter is only for 32Mb density
5. K and K Clocks must be used differentially to meet AC timing specifications.
Rev 0.0
Nov. 2005
- 12
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES
(Burst Length=4, 2)
READ
READ
CONTINUE READ
(burst of 2)
WRITE
READ
NOP
READ
CONTINUE READ
CONTINUE
CONTINUE
NOP
NOP
WRITE
READ
(burst of 4)
(burst of 4)
(burst of 4)
(burst of 4)
9
5
1
2
4
7
6
8
10
12
11
3
K
K
tKHKH
B1
B2
tBVKH
tKHBX
B3
A2
A5
A1
A3
A0
SA
tAVKH
t
KHAX
t
KHDX
DVKH
t
DQ
Q01
Q02
Q03
Q04
Q51
Q52
Q53
Q54
Q11
Q12
D
21
D22
D23
D24
Q31
QX2
t
CHQV
tCHQX
tCLQV
tKXCH
tKXCL
CLQX
t
tCHCL tCLCH
tCHQZ
tCHLZ
CQ
CQ
DON’T CARE
UNDEFINED
NOTE
1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
Rev 0.0
Nov. 2005
- 13
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES
(Burst Length=4, 2, 1)
READ
READ
READ
WRITE
READ
NOP
READ
CONTINUE CONTINUE CONTINUE READ
CONTINUE
CONTINUE
NOP
NOP
WRITE
READ
(burst of 4)
(burst of 1)
(burst of 2)
(burst of 2)
1
2
3
4
5
6
7
8
9
10
11
12
K
tKHKL
tKLKH
tKHKH
K
B1
B2
B3
tBVKH
tKHBX
A2
A1
A3
A0
SA
tDVKH
tAVKH
tKHAX
tKHDX
DQ
Q01
Q02
Q03
Q04
Q11
QX1
D21
D22
Q31
tKXCH
tCHQV
tKXCL
tCHQX
tCHCLtCLCH
tCHLZ
tCHQZ
CQ
CQ
DON’T CARE
UNDEFINED
NOTE :
1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation. Any further
Continue assertions constitute invalid operations.
4. This device will have an address wraparound if further Continues are applied.
Rev 0.0
Nov. 2005
- 14
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing
between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform-
ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control-
ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use
this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must
be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the
application of a logic 1, and therefore can be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left
unconnected.
JTAG Block Diagram
JTAG Instruction Coding
Notes
1
IR2 IR1 IR0 Instruction
TDO Output
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
IDCODE
Boundary Scan Register
Identification Register
0
2
0
SAMPLE-Z Boundary Scan Register
PRIVATE3 Bypass Register
1
0
3,5
4
1
SAMPLE
Boundary Scan Register
SRAM
1
PRIVATE2 Bypass Register
PRIVATE1 Bypass Register
3,5
3,5
3
CORE
1
SA
SA
1
BYPASS
Bypass Register
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. Input terminators are switched off.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
TDI
BYPASS Reg.
Identification Reg.
Instruction Reg.
TDO
3. Bypass register is initiated to VSS when BYPASS instruction is
invoked.
The Bypass Register also holds serially loaded TDI when exiting the
Shift DR states.
Control Signals
TAP Controller
4. SAMPLE instruction dose not places DQs in Hi-Z.
TMS
TCK
5. PRIVATE1 and PRIVATE2 are reserved for the exclusive use of SAM-
SUNG. This instruction should not be used.
TAP Controller State Diagram
Test Logic Reset
0
Run Test Idle
1
0
1
1
0
1
Select DR
0
Select IR
0
1
1
1
1
Capture IR
Capture DR
0
0
0
Shift IR
Shift DR
1
1
Exit1 IR
Exit1 DR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update IR
1
1
0
Update DR
0
Rev 0.0
Nov. 2005
- 15
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
BOUNDARY SCAN EXIT ORDER(x36)
BOUNDARY SCAN EXIT ORDER(x18)
1
5P
5R
5T
6R
7T
7R
7P
8T
9T
8P
7M
9P
8M
9M
7K
8K
9K
6L
VDD(2)
SA1
SA0
SA
SA
VDD(2)
SA
DQ1
DQ2
DQ10
DQ0
DQ12
CQ(3)
DQ3
DQ9
DQ11
DQ13
MODE
K
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
5C
4A
4C
4D
3A
3B
3C
3D
2B
1B
2D
3F
1D
2F
1F
3H
2H
1H
5A
5B
5K
5L
SA
SA
SA
VSS(2
SA
SA
1
2
3
4
5
6
7
8
5P
5R
5T
6R
7T
7R
7P
8T
VDD(2)
SA1
SA0
SA
SA
VDD(2)
SA
28
29
30
31
32
33
34
35
36
5C
4A
4C
4D
3A
3B
3C
3D
2B
SA
SA
SA
VSS(2)
SA
SA
SA
SA
DQ10
2
3
4
5
6
7
8
9
SA
SA
DQ1
DQ19
DQ20
DQ28
DQ18
DQ30
CQ(3)
DQ21
DQ27
DQ29
DQ31
ZQ(1)
B1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
9
9P
DQ2
10
8M
CQ(3)
37
38
1D
2F
DQ11
CQ(3)
11
7K
DQ0
39
3H
DQ9
12
13
14
15
9K
6L
5H
5G
DQ3
MODE
K
40
41
42
43
44
45
1H
5A
5B
5K
5L
4L
DQ12
ZQ(1)
B1
B2
B3
5H
5G
9H
8H
7H
9F
8F
9D
7F
8D
9B
8B
7D
7C
7B
7A
6D
6C
6A
K
K
DQ4
DQ6
DQ8
DQ14
CQ(3)
DQ5
DQ17
DQ7
DQ15
DQ16
SA
SA
SA
SA
VSS(2)
SA
B2
B3
16
17
8H
9F
DQ6
DQ4
4L
LBO
DQ22
DQ24
DQ26
DQ32
CQ(3)
DQ23
DQ35
DQ25
DQ33
DQ34
VDD(2)
SA
LBO
1K
2K
3K
1M
2M
1P
3M
2P
1T
2T
3R
3T
4R
7U
46
47
2K
DQ15
DQ13
18
19
20
7F
8D
9B
DQ8
DQ7
DQ5
1M
48
49
50
51
52
53
54
55
3M
2P
1T
3P
3R
3T
4R
7U
DQ17
DQ16
DQ14
SA
VDD(2)
SA
21
22
23
24
25
26
27
7D
7C
7B
7A
6D
6C
6A
SA
SA
SA
SA
VSS(2)
SA
SA
NC
SA
NC
SA
SA
* Reserved for Mode Pin
* Reserved for Mode Pin
NOTE :
1. If pin is connected as they should, TDO will be low. If pin is open, TDO will be high
2. This pin is place holder for higher density. TDO will be low for VSS and high for VDD
3. CQ and CQ are outputs during boundary scan. CQ reflects the input to K and CQ outputs the inverted value of K. It is prohibited to force CQ and CQ.
And TDO is ’X’.(Don’t Care)
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
1 bits
ID Register
32 bits
Boundary Scan
74 bits
1M x 36
2M x 18
3 bits
3 bits
1 bits
32 bits
55 bits
Rev 0.0
Nov. 2005
- 16
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
ID REGISTER DEFINITION
Revision Number
Part Configuration
(27:18)
Vendor Definition
(17:12)
Samsung JEDEC Code
(11: 1)
Start Bit
(0)
Part
(31:28)
1M x 36
2M x 18
0000
0000
01000 00100
01001 00011
XXXXXX
XXXXXX
00011001110
00011001110
1
1
JTAG DC OPERATING CONDITIONS
Parameter
Symbol
Min
1.7
Typ
Max
2.6
Unit
V
Note
Power Supply Voltage
VDD
VIH
2.5
Input High Level
0.65*VDD
-0.3
-
-
-
-
VDD+0.3
0.35*VDD
VDD
V
Input Low Level
VIL
V
Output High Voltage(IOH=-2mA)
Output Low Voltage(IOL=2mA)
VOH
VOL
0.75*VDD
VSS
V
0.25*VDD
V
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Symbol
VIH/VIL
TR/TF
Min
Unit
V
Note
Input High/Low Level
VDD/0.0
1.0/1.0
VDD/2
Input Rise/Fall Time
ns
V
Input and Output Timing Reference Level
NOTE : 1. See SRAM AC test output load on page 5.
1
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
Note
TCK Cycle Time
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tCLQV
-
-
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
-
-
5
-
5
-
5
-
Clock Low to Output Valid
0
10
JTAG TIMING DIAGRAM
TCK
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tCHDX
TMS
TDI
tDVCH
tCLQV
TDO
Rev 0.0
Nov. 2005
- 17
Preliminary
K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
153 BGA PACKAGE DIMENSIONS
1.27
0.60 ±0.10
0.050
0.024 ±0.004
9 8 7 6 5 4 3 2 1
0.56 ±0.04
0.022 ±0.002
12.50 ±0.10
0.492 ±0.004
14.00 ±0.10
0.551 ±0.004
0.75 ±0.15
0.90 ±0.10
153-∅
∅0.3/0.012MAX
0.030 ±0.006
0.035 ±0.004
2.21
MAX
0.087
0.15
MAX
0.006
BOTTOM VIEW
TOP VIEW
NOTE :
1. All Dimensions are in Millimeters.
2. Solder Ball to PCS Offset : 0.10 MAX.
3. PCB to Cavity Offset : 0.10 MAX.
153 BGA PACKAGE THERMAL CHARACTERISTICS
Parameter
Junction to Ambient(at still air)
Junction to Case
Symbol
Theta_JA
Theta_JC
Theta_JB
Thermal Resistance
Unit
°C/W
°C/W
°C/W
Note
TBD
TBD
TBD
Junction to Board
NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x Theta_JA.
Rev 0.0
Nov. 2005
- 18
相关型号：
©2020 ICPDF网 联系我们和版权申明