K7I321884C-FI25 [SAMSUNG]
Standard SRAM, 2MX18, 0.45ns, CMOS, PBGA165;
| 型号： | K7I321884C-FI25 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 2MX18, 0.45ns, CMOS, PBGA165 静态存储器 |
| 文件： | 总18页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
36Mb DDRII SRAM Specification
165 FBGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 August 2006
- 1 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
Document Title
1Mx36-bit, 2Mx18-bit DDRII CIO b4 SRAM
Revision History
Rev. No.
History
Draft Date
Remark
Advance
Preliminary
0.0
1. Initial document.
Jan. 17, 2006
Apr. 26, 2006
0.1
1. Put the data in the table of DC Characteristics, Pin Capacitance
and Thermal Resistance.
0.2
1. Add 333MHz Bin
2. Change AC Characteristics.
Preliminary
May. 08, 2006
0.3
1.0
1. Change Samsung JEDEC Code in ID REGISTER DEFINITION
Preliminary
Final
Jun. 05, 2006
Jul, 10, 2006
1. Final
2. Change Vss/SA to NC/SA in Pin Configuration
1.1
1. Correct typo
Final
Aug. 23, 2006
Rev. 1.1 August 2006
- 2 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
1Mx36-bit, 2Mx18-bit DDRII CIO b4 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
Cycle Access
Time Time
RoHS
Avail.
Org.
Part Number
Unit
• DLL circuitry for wide output data valid window and future fre-
quency scaling.
K7I323684C-E(F)C(I)33
K7I323684C-E(F)C(I)30
K7I323684C-E(F)C(I)25
K7I321884C-E(F)C(I)33
K7I321884C-E(F)C(I)30
K7I321884C-E(F)C(I)25
3.0
3.3
4.0
3.0
3.3
4.0
0.45
0.45
0.45
0.45
0.45
0.45
ns
ns
ns
ns
ns
ns
√
√
√
√
√
√
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O.
X36
X18
• Pipelined, double-data rate operation.
• Common data input/output bus.
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR (Double Data Rate) Interface on read and write ports.
• Fixed 4-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks (K and K) for accurate DDR timing at clock
rising edges only.
* -E(F)C(I)
E(F) [Package type]: E-Pb Free, F-Pb
C(I) [Operating Temperature]: C-Commercial, I-Industrial
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Single address bus.
• Byte write (x18, x36) function.
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball array FBGA) with body size of 15x17mm
& Lead Free
FUNCTIONAL BLOCK DIAGRAM
36 (or 18)
DATA
REG
36 (or 18)
WRITE DRIVER
18
ADD REG
&
18 (or 19)
4(or 2)
(or 19)
ADDRESS
A0,A1
BURST
LOGIC
72
72
(or 36)
1Mx36
(2Mx18)
MEMORY
ARRAY
36 (or 18)
DQ
(or 36)
LD
R/W
BWX
CTRL
LOGIC
CQ, CQ
(Echo Clock out)
K
K
CLK
GEN
C
C
SELECT OUTPUT CONTROL
Notes: 1. Numbers in ( ) are for x18 device
DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
Rev. 1.1 August 2006
- 3 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7I323684C(1Mx36)
1
2
NC/SA*
DQ27
NC
DQ29
NC
DQ30
DQ31
VREF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
4
5
6
K
K
7
8
LD
SA
9
SA
10
NC/SA*
NC
11
CQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
SA
R/W
SA
VSS
BW2
BW3
SA
BW1
BW0
SA1
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
SA0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
VSS
DQ17
NC
DQ15
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
VREF
DQ13
DQ12
NC
DQ11
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
VSS
VSS
SA
SA
SA
SA
SA
SA
DQ9
TMS
SA
SA
C
Notes: 1. * Checked No Connect (NC) pins are reserved for higher density address, i.e. 10A for 72Mb, 2A for 144Mb.
2. BW0 controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35.
PIN NAME
SYMBOL
PIN NUMBERS
DESCRIPTION
Input Clock
NOTE
K, K
C, C
CQ, CQ
Doff
SA0,SA1
SA
6B, 6A
6P, 6R
11A, 1A
1H
6C,7C
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Burst Count Address Inputs
Address Inputs
1
3A,9A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3M,10M,11M,2N,3N,11N,3P,10P,11P
DQ0-35
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
R/W
LD
4A
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW1,BW2, BW3
7B,7A,5A,5B
2H,10H
11H
Block Write Control Pin, active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply (1.8 V)
VREF
ZQ
VDD
2
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
VDDQ
Output Power Supply (1.5V or 1.8V)
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
4M-8M,4N,8N
VSS
Ground
TMS
TDI
TCK
TDO
10R
11R
2R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
1R
JTAG Test Data Output
2A,10A,1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
NC
No Connect
3
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected
3. Not connected to chip pad internally.
.
Rev. 1.1 August 2006
- 4 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7I321884C(2Mx18)
1
2
NC/SA*
DQ9
NC
3
4
5
6
7
NC
8
LD
SA
VSS
9
SA
10
SA
NC
DQ7
NC
NC
NC
NC
VREF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
A
B
C
D
E
F
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
SA
NC
NC
R/W
SA
VSS
BW1
NC
SA
K
K
BW0
SA1
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
SA0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
NC
NC
DQ12
NC
VREF
NC
NC
DQ15
NC
NC
NC
DQ10
DQ11
NC
DQ13
VDDQ
NC
DQ14
NC
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
G
H
J
K
L
M
N
P
R
DQ16
DQ17
SA
VSS
SA
SA
VSS
SA
SA
SA
SA
SA
SA
TCK
C
Notes: 1. * Checked No Connect (NC) pins are reserved for higher density address, i.e. 2A for 72Mb.
2. BW0 controls write to DQ0:DQ8 and BW1 controls write to DQ9:DQ17.
PIN NAME
SYMBOL
K, K
PIN NUMBERS
DESCRIPTION
Input Clock
NOTE
6B, 6A
C, C
CQ, CQ
Doff
SA0,SA1
SA
6P, 6R
11A, 1A
1H
6C,7C
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Burst Count Address Inputs
Address Inputs
1
3A,9A,10A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L
10M,3N,3P,11P
DQ0-17
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
R/W
4A
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
LD
BW0, BW1
VREF
7B, 5A
2H,10H
11H
Block Write Control Pin, active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply (1.8 V)
ZQ
VDD
2
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
VDDQ
VSS
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply (1.5V or 1.8V)
Ground
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
TMS
TDI
TCK
TDO
10R
11R
2R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
1R
JTAG Test Data Output
2A,7A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,11D
1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G
NC
No Connect
3
1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L
1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected
3. Not connected to chip pad internally.
.
Rev. 1.1 August 2006
- 5 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
GENERAL DESCRIPTION
The K7I323684C and K7I321884C are 37,748,736-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized
as 1,048,576 words by 36bits for K7I323684C and 2,097,152 words by 18 bits for K7I321884C.
Address, data inputs, and all control signals are synchronized to the input clock (K or K). Normally data outputs are synchronized to
output clocks (C and C), but when C and C are tied high, the data outputs are synchronized to the input clocks (K and K). Read data
are referenced to echo clock (CQ or CQ) outputs. Read address and write address are registered on rising edges of the input K
clocks.
Common address bus is used to access address both for read and write operations. The internal burst counter is fixed to 4-bit
sequential for both read and write operations. Synchronous pipeline read and late write enable high speed operations. Simple depth
expansion is accomplished by using LD for port selection. Byte write operation is supported with BW0 and BW1 (BW2 and BW3) pins
for x18 (x36) device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.
The K7I323684C and K7I321884C are implemented with SAMSUNG's high performance 6T CMOS technology and is available in
165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K. Address is presented and stored in
the read address register synchronized with K clock. For 4-bit burst DDR operation, it will access four 36-bit or 18-bit data words with
each read command.
The first pipelined data is transferred out of the device triggered by C clock following next K clock rising edge. Next burst data is trig-
gered by the rising edge of following C clock rising edge. Continuous read operations are initiated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks. In case C and C tied to high, output data
are triggered by K and K instead of C and C.
When the LD is disabled after a read operation, the K7I323684C and K7I321884C will first complete burst read operation before
entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high impedance state.
Write Operations
Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K. Address is presented and stored in
the write address register synchronized with next K clock. For 4-bit burst DDR operation, it will write two 36-bit or 18-bit data words
with each write command.
The first “late write” data is transferred and registered in to the device synchronous with next K clock rising edge. Next burst data is
transferred and registered synchronous with following K clock rising edge. Continuous write operations are initiated with K rising
edge.
And “late write” data is presented to the device on every rising edge of both K and K clocks.
When the LD is disabled, the K7I323684C and K7I321884C will enter into deselect mode. The device disregards input data pre-
sented on the same cycle W disabled.
The K7I323684C and K7I321884C support byte write operations. With activating BW0 or BW1 (BW2 or BW3) in write cycle, only one
byte of input data is presented. In K7I321884C, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.
And in K7I323684C BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.
Rev. 1.1 August 2006
- 6 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
Single Clock Mode
K7I323684C and K7I321884C can be operated with the single clock pair K and K, instead of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high during oper-
ation. After power up, this device can′t change to or from single clock mode. System flight time and clock skew could not be compen-
sated in this mode.
Depth Expansion
Each port can be selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal for
each bank. Before chip deselected, all read and write pending operations are completed.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor (RQ).
The value of RQ (within 15%) is five times the output impedance desired. For example, 250Ω resistor will give an output impedance
of 50Ω.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates
are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the
SRAM needs 1024 non-read cycles.
Echo clock operation
To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are syn-
chronized with internal data output. Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transferred to external through same structures as output driver.
Clock Consideration
K7I323684C and K7I321884C utilize internal DLL (Delay-Locked Loops) for maximum output data valid window. It can be placed into
a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
Rev. 1.1 August 2006
- 7 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
Detail Specification of Power-Up Sequence in DDRII SRAM
DDRII SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
• Power-Up Sequence
1. Apply power and keep Doff at low state (All other inputs may be undefined)
- Apply VDD before VDDQ
- Apply VDDQ before VREF or the same time with VREF
2. Just after the stable power and clock (K, K, C, C), take Doff to be high.
3. The additional 1024cycles of clock input is required to lock the DLL after enabling DLL
* Notes: If you want to tie up the Doff pin to High with unstable clock, then you must stop the clock for a few seconds
(Min. 30ns) to reset the DLL after it become a stable clock status.
• DLL Constraints
1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as TKC var.
2. The lower end of the frequency at which the DLL can operate is 8.4ns.
3. If the incoming clock is unstable and the DLL is enabled, then the DLL may lock onto a wrong frequency
and this may cause the failure in the initial stage.
Power up & Initialization Sequence (Doff pin controlled)
K,K
1024 cycle
Unstable
Any
Power-Up
DLL Locking Range
Inputs Clock
Status
CLKstage
Command
must be stable
V
DD
V
DDQ
V
REF
Doff
Power up & Initialization Sequence (Doff pin Fixed high, Clock controlled)
K,K
Min 30ns
1024 cycle
Unstable
Any
Stop Clock
Power-Up
DLL Locking Range
Inputs Clock
Status
CLKstage
Command
must be stable
V
DD
V
DDQ
V
REF
* Notes: When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 1024 cycles of clock input is needed to lock the DLL.
Rev. 1.1 August 2006
- 8 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
LINEAR BURST SEQUENCE TABLE
Case 1
Case 2
Case 3
Case 4
BURST SEQUENCE
SA1
SA0
SA1
SA0
SA1
SA0
SA1
SA0
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
Q
K
LD
R/W
OPERATION
Q(A0)
Q(A1)
Q(A2)
Q(A3)
Previous
state
Previous
state
Previous
state
Previous
state
Stopped
X
H
L
X
X
H
L
Clock Stop
No Operation
Read
↑
↑
↑
High-Z
High-Z
High-Z
High-Z
QOUT at
C(t+1)
QOUT at
C(t+2)
QOUT at
C(t+2)
QOUT at
C(t+3)
L
Din at K(t+1) Din at K(t+1) Din at K(t+2) Din at K(t+2)
Write
Notes: 1. X means “Don′t Care”.
2. The rising edge of clock is symbolized by (↑).
3. Before enter into clock stop status, all pending read and write operations will be completed.
WRITE TRUTH TABLE(x18)
K
K
↑
↑
↑
↑
BW0
L
BW1
L
OPERATION
↑
WRITE ALL BYTEs ( K↑)
WRITE ALL BYTEs ( K↑)
WRITE BYTE 0 ( K↑)
WRITE BYTE 0 ( K↑)
WRITE BYTE 1 ( K↑)
WRITE BYTE 1 ( K↑ )
WRITE NOTHING ( K↑)
WRITE NOTHING ( K↑)
L
L
↑
L
H
L
H
↑
H
L
H
L
↑
H
H
H
H
Notes: 1. X means “Don′t Care”.
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (↑).
3. Assumes a WRITE cycle was initiated.
4. This table illustrates operation for x18 devices.
WRITE TRUTH TABLE(x36)
K
K
↑
↑
↑
↑
↑
BW0
L
BW1
L
BW2
L
BW3
L
OPERATION
WRITE ALL BYTEs ( K↑)
WRITE ALL BYTEs ( K↑)
WRITE BYTE 0 ( K↑)
↑
L
L
L
L
↑
↑
↑
↑
L
H
H
L
H
H
H
H
L
H
H
H
H
L
L
WRITE BYTE 0 ( K↑)
H
H
H
H
H
H
WRITE BYTE 1 ( K↑)
L
WRITE BYTE 1 ( K↑)
H
H
H
H
WRITE BYTE 2 and BYTE 3 ( K↑)
WRITE BYTE 2 and BYTE 3 ( K↑)
WRITE NOTHING ( K↑)
WRITE NOTHING ( K↑)
L
L
H
H
H
H
Notes: 1. X means "Don′t Care”.
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (↑).
3. Assumes a WRITE cycle was initiated.
Rev. 1.1 August 2006
- 9 -
K7I323684C
K7I321884C
ABSOLUTE MAXIMUM RATINGS*
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Storage Temperature
SYMBOL
VDD
RATING
-0.5 to 2.9
UNIT
V
VDDQ
VIN
-0.5 to VDD
V
-0.5 to VDD+0.3
-65 to 150
V
TSTG
TOPR
TBIAS
°C
°C
°C
Operating Temperature
Commercial / Industrial
0 to 70 / -40 to 85
-10 to 85
Storage Temperature Range Under Bias
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
OPERATING CONDITIONS
PARAMETER
SYMBOL
VDD
Min
1.7
MAX
1.9
UNIT
V
V
V
Supply Voltage
Reference Voltage
VDDQ
1.4
1.9
VREF
0.68
0.95
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
VDD=Max; VIN=VSS to VDDQ
MIN
-2
MAX
+2
UNIT NOTES
Input Leakage Current
Output Leakage Current
IIL
µA
µA
IOL
Output Disabled,
-2
+2
-33
-30
-25
-33
-30
-25
-33
-30
-25
750
700
650
700
650
600
300
280
250
VDD=Max, IOUT=0mA
Cycle Time ≥ tKHKH Min
Operating Current (x36)
Operating Current (x18)
Standby Current (NOP)
ICC
ICC
-
-
mA
mA
mA
1,5
1,5
1,6
VDD=Max, IOUT=0mA
Cycle Time ≥ tKHKH Min
-
-
Device deselected, IOUT=0mA, f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V
ISB1
-
-
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Input Low Voltage
Input High Voltage
VOH1
VOL1
VOH2
VOL2
VIL
VDDQ/2-0.12 VDDQ/2+0.12
VDDQ/2-0.12 VDDQ/2+0.12
V
V
V
V
V
V
2,7
3,7
4
IOH=-1.0mA
IOL=1.0mA
VDDQ-0.2
VSS
VDDQ
0.2
4
-0.3
VREF-0.1
VDDQ+0.3
8,9
8,10
VIH
VREF+0.1
Notes: 1. Minimum cycle. IOUT=0mA.
2. |IOH|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.
3. |IOL|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.
4. Minimum Impedance Mode when ZQ pin is connected to VDD.
5. Operating current is calculated with 50% read cycles and 50% write cycles.
6. Standby Current is only after all pending read and write burst operations are completed.
7. Programmable Impedance Mode.
8. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.
9. VIL (Min.) DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).
10. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).
Rev. 1.1 August 2006
- 10 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
MIN
MAX
-
UNIT
V
NOTES
1,2
VIH (AC)
VIL (AC)
VREF + 0.2
-
VREF - 0.2
V
1,2
Notes: 1. This condition is for AC function test only, not for AC parameter test.
2. To maintain a valid level, the transition edge of the input must:
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
AC TIMING CHARACTERISTICS
-33
-30
-25
PARAMETER
SYMBOL
UNIT
NOTE
MIN
MAX
MIN
MAX
MIN
MAX
Clock
Clock Cycle Time (K, K, C, C)
Clock Phase Jitter (K, K, C, C)
Clock High Time (K, K, C, C)
Clock Low Time (K, K, C, C)
Clock to Clock (K↑ → K↑, C↑ → C↑)
Clock to data clock (K↑ → C↑, K↑→ C↑)
DLL Lock Time (K, C)
tKHKH
tKC var
tKHKL
3.00
8.40
0.20
3.30
8.40
0.20
4.00
8.40
0.20
ns
ns
5
1.2
1.2
1.32
1.32
1.49
0.00
1024
30
1.60
1.60
1.80
0.00
1024
30
ns
tKLKH
ns
tKHKH
tKHCH
tKC lock
tKC reset
1.35
0.00
1024
30
ns
1.30
1.45
1.80
ns
cycle
ns
6
K Static to DLL reset
Output Times
C, C High to Output Valid
C, C High to Output Hold
C, C High to Echo Clock Valid
C, C High to Echo Clock Hold
CQ, CQ High to Output Valid
CQ, CQ High to Output Hold
C, High to Output High-Z
C, High to Output Low-Z
Setup Times
tCHQV
tCHQX
0.45
0.45
0.25
0.45
0.45
0.45
0.27
0.45
0.45
0.45
0.30
0.45
ns
ns
ns
ns
ns
ns
ns
ns
3
3
-0.45
-0.45
-0.25
-0.45
-0.45
-0.45
-0.27
-0.45
-0.45
-0.45
-0.30
-0.45
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHQZ
7
7
3
3
tCHQX1
Address valid to K rising edge
Control inputs valid to K rising edge
Data-in valid to K, K rising edge
Hold Times
tAVKH
tIVKH
0.40
0.40
0.28
0.40
0.40
0.30
0.50
0.50
0.35
ns
ns
ns
2
tDVKH
K rising edge to address hold
K rising edge to control inputs hold
K, K rising edge to data-in hold
tKHAX
tKHIX
0.40
0.40
0.28
0.40
0.40
0.30
0.50
0.50
0.35
ns
ns
ns
tKHDX
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,BW0,BW1 and (BW2, BW3, also for x36)
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ± 0.1 ns variation from echo clock to data.
The data sheet parameters reflect tester guardbands and test setup variations.
Rev. 1.1 August 2006
- 11 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
THERMAL RESISTANCE
PRMETER
Junction to Ambient
Junction to Case
SYMBOL
θJA
TYP
20.8
2.3
Unit
°C/W
°C/W
°C/W
NOTES
θJC
Junction to Pins
θJB
4.3
Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. TJ=TA + PD x θJA
PIN CAPACITANCE
PRMETER
Address Control Input Capacitance
Input and Output Capacitance
Clock Capacitance
SYMBOL
CIN
TESTCONDITION
TYP
MAX
Unit
pF
NOTES
VIN=0V
VOUT=0V
-
4
6
5
5
7
6
COUT
pF
CCLK
pF
Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V.
2. Periodically sampled and not 100% tested.
AC TEST CONDITIONS
AC TEST OUTPUT LOAD
Parameter
Symbol
VDD
Value
1.7~1.9
1.4~1.9
1.25/0.25
0.75
Unit
V
0.75V
Core Power Supply Voltage
Output Power Supply Voltage
Input High/Low Level
VREF
VDDQ/2
VDDQ
VIH/VIL
VREF
V
50Ω
V
SRAM
Zo=50Ω
Input Reference Level
V
250Ω
Input Rise/Fall Time
TR/TF
0.3/0.3
VDDQ/2
ns
V
ZQ
Output Timing Reference Level
Note: Parameters are tested with RQ=250Ω
Overershoot Timing
Undershoot Timing
20% tKHKH
VDDQ+0.5V
VIH
VDDQ+0.25V
VDDQ
VSS
VSS-0.25V
VSS-0.5V
20% tKHKH(MIN)
VIL
Note: For power-up, VIH ≤ VDDQ+0.3V and VDD ≤ 1.7V and VDDQ ≤ 1.4V t ≤ 200ms
Rev. 1.1 August 2006
- 12 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
APPLICATION INRORMATION
R=250Ω
R=250Ω
ZQ
CQ
CQ
DQ
ZQ
CQ
CQ
DQ
SRAM#1
SRAM#4
Vt
SA
SA
R
R/W LD0BW0 BW1C C K K
R/WLD3BW0BW1 C C K K
R
DQ
Vt
Address
R/W
LD
BW
MEMORY
CONTROLLER
Return CLK
Source CLK
Return CLK
Source CLK
R=50Ω Vt=VREF
SRAM1 Input CQ
SRAM1 Input CQ
SRAM4 Input CQ
SRAM4 Input CQ
Rev. 1.1 August 2006
- 13 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
TIMING WAVE FORMS OF READ, WRITE AND NOP
NOP
READ
READ
NOP
NOP
WRITE
READ
(burst of 4)
(burst of 4)
(burst of 4)
(burst of 4)
(Note3)
9
5
1
2
4
7
6
8
10
12
11
3
K
K
t
KHKL
t
KHKH
tKHKH
tKLKH
tIVKH
tKHIX
LD
R/W
A2
A1
A3
A0
SA
t
KHDX
DVKH
tAVKH
tKHAX
t
DQ
Q01
Q02
Q03
Q04
Q11
Q12
Q13
Q14
D
21
D22
D23
D24
Q31
Q32
Q33
tCHQX
tCQHQX
t
CHQZ
t
CHQV
t
CQHQV
tKHCH
t
CHQX1
tKHKH
tKHKH
tKHKL
tKLKH
C
C
tCQHQZ
tCHCQX
tCHCQV
CQ
CQ
t
CHCQV
CHCQX
t
DON′T CARE
UNDEFINED
NOTE
1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled (High-Z) one clock cycle after a NOP.
3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent
bus contention.
Rev. 1.1 August 2006
- 14 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 Instruction
TDO Output
Notes
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
IDCODE
SAMPLE-Z
Boundary Scan Register
Identification Register
Boundary Scan Register
1
3
2
6
5
6
6
4
0
0
0
RESERVED Do Not Use
1
SAMPLE
Boundary Scan Register
1
RESERVED Do Not Use
RESERVED Do Not Use
SRAM
CORE
1
1
BYPASS
Bypass Register
NOTE:
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
TDI
BYPASS Reg.
Identification Reg.
Instruction Reg.
TDO
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
Control Signals
TAP Controller
TMS
TCK
TAP Controller State Diagram
1
0
Test Logic Reset
0
1
1
0
1
Run Test Idle
Select DR
0
Capture DR
0
Shift DR
1
Exit1 DR
0
Select IR
0
1
1
1
1
Capture IR
0
0
Shift IR
1
Exit1 IR
0
0
0
0
0
Pause DR
1
Pause IR
1
Exit2 IR
1
Exit2 DR
1
1
0
Update DR
0
Update IR
1
Rev. 1.1 August 2006
- 15 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
ID Register
32 bits
32 bits
Boundary Scan
109 bits
1Mx36
2Mx18
3 bits
3 bits
1 bit
1 bit
109 bits
ID REGISTER DEFINITION
Revision Number
Part Configuration
(28:12)
00def0wx0t0q0b0s0
Samsung JEDEC Code
(11: 1)
Part
Start Bit(0)
(31:29)
000
1Mx36
2Mx18
00011001110
00011001110
1
1
000
00def0wx0t0q0b0s0
Note: Part Configuration
/def=010 for 36Mb, /wx=11 for x36, 10 for x18
/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O
BOUNDARY SCAN EXIT ORDER
ORDER
PIN ID
ORDER
PIN ID
10D
9E
ORDER
73
PIN ID
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1H
1J
2J
3K
3J
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
Internal
1
2
6R
6P
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
3
4
6N
7P
10C
11D
9C
9D
11B
11C
9B
10B
11A
10A
9A
5
6
7N
7R
7
8
8R
8P
9
9R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10M
11N
9M
9N
11L
11M
9L
10L
11K
10K
9J
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
9K
98
99
10J
11J
11H
10G
9G
11F
11G
9F
100
101
102
103
104
105
106
107
108
109
10F
11E
10E
3D
3C
1D
Note: 1. NC pins are read as "X" (i.e. don′t care.)
Rev. 1.1 August 2006
- 16 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Symbol
Min
1.7
Typ
Max
1.9
Unit
V
Note
Power Supply Voltage
VDD
VIH
1.8
Input High Level
1.3
-
-
-
-
VDD+0.3
0.5
V
Input Low Level
VIL
-0.3
1.4
V
Output High Voltage (IOH=-2mA)
Output Low Voltage(IOL=2mA)
VOH
VOL
VDD
V
VSS
0.4
V
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Symbol
VIH/VIL
TR/TF
Min
1.8/0.0
1.0/1.0
0.9
Unit
V
Note
Input High/Low Level
Input Rise/Fall Time
ns
V
Input and Output Timing Reference Level
Note: 1. See SRAM AC test output load on page 11.
1
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
Note
TCK Cycle Time
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
-
-
5
-
5
-
5
-
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
5
-
5
-
0
10
JTAG TIMING DIAGRAM
TCK
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
TMS
TDI
tDVCH
tSVCH
tCHDX
tCHSX
PI
(SRAM)
tCLQV
TDO
Rev. 1.1 August 2006
- 17 -
K7I323684C
K7I321884C
1Mx36 & 2Mx18 DDRII CIO b4 SRAM
165 FBGA PACKAGE DIMENSIONS (Lead & Lead Free)
15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
B
Top View
A
C
Side View
D
A
G
E
B
F
Bottom View
H ∅
E
Symbol
Value
15 ± 0.1
Units
Note
Symbol
Value
1.0
Units
mm
mm
mm
mm
Note
A
B
C
D
mm
mm
mm
mm
E
F
17 ± 0.1
1.3 ± 0.1
0.35 ± 0.05
14.0
G
H
10.0
0.5 ± 0.05
Rev. 1.1 August 2006
- 18 -
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