K7N161831B-QI160 [SAMSUNG]
ZBT SRAM, 1MX18, 3.5ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100;
| 型号： | K7N161831B-QI160 |
| 厂家： | 
SAMSUNG |
| 描述： | ZBT SRAM, 1MX18, 3.5ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总25页 (文件大小：559K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
TM
18Mb NtRAM Specification
100TQFP/165FBGA with Pb/Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 3.0 April 2006
- 1 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
Document Title
512Kx36 & 1Mx18-Bit Pipelined NtRAMTM
Revision History
Draft Date
Mar. 23, 2004
May. 13. 2004
Sep. 21. 2004
Rev. No.
History
Remark
Advance
0.0
0.1
0.2
1. Initial document.
Preliminary
Preliminary
1. Update the current spec(Icc, ISB)
1. Change the ISB,ISB1,ISB2
- ISB ; from 120mA to 170mA
- ISB1 ; from 80mA to 150mA
- ISB2 ; from 80mA to 130mA
Oct. 18. 2004
Jan. 04. 2005
July 18. 2005
Feb. 16. 2006
Apr. 04. 2006
Preliminary
Preliminary
Final
0.3
0.4
1.0
2.0
3.0
1. Remove the 1.8V Vdd voltage level
1. Remove the -20 and -13 speed bin
1. Finalize the datasheet
Final
1. Add the overshoot timing
Final
1. Change ordering information
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. 3.0 April 2006
- 2 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
18Mb NtRAM (Pipelined) Ordering Information
Org.
VDD (V)
Speed (ns)
Access Time (ns)
Part Number
RoHS Avail.
K7N161831B-P(Q,E,F)1C(I)225
K7N161831B-P(Q,E,F)1C(I)216
K7N163631B-P(Q,E,F)1C(I)225
K7N163631B-P(Q,E,F)1C(I)216
3.3/2.5
3.3/2.5
3.3/2.5
3.3/2.5
4.0
6.0
4.0
6.0
2.6
3.5
2.6
3.5
√
√
√
√
1Mx18
512Kx36
Note 1. P(Q,E,F) [Package type] : 100TQFP ; P-Pb Free, Q-Pb, 165FBGA ; E-Pb Free, F-Pb
2. C(I) [Operating Temperature] : C-Commercial, I-Industrial
Rev. 3.0 April 2006
- 3 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
512Kx36 & 1Mx18-Bit Pipelined NtRAMTM
FEATURES
GENERAL DESCRIPTION
• VDD= 2.5 or 3.3V +/- 5% Power Supply.
• Byte Writable Function.
The K7N163631B and K7N161831B are 18,874,368-bits Syn-
chronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N163631B and K7N161803B are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP and 165FBGA packages. Multiple power
and ground pins minimize ground bounce.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data-
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• 100-TQFP-1420A (Lead and Lead free package)
• 165FBGA(11x15 ball aray) with body size of 13mmx15mm.
(Lead and Lead free package)
• Operating in commeical and industrial temperature range.
FAST ACCESS TIMES
PARAMETER
Symbol
tCYC
tCD
-25
4.0
2.6
2.6
-16
6.0
3.5
3.5
Unit
ns
Cycle Time
Clock Access Time
ns
Output Enable Access Time
tOE
ns
LOGIC BLOCK DIAGRAM
LBO
A0~A1
BURST
A
′
0
~A′1
A [0:18]or
ADDRESS
COUNTER
512Kx36, 1Mx18
MEMORY
A [0:19]
ADDRESS
REGISTER
A2~A18 or A2~A19
ARRAY
WRITE
WRITE
ADDRESS
REGISTER
DATA-IN
ADDRESS
CLK
CKE
K
K
REGISTER
K
REGISTER
DATA-IN
REGISTER
CS
CS
CS
1
2
2
ADV
WE
CONTROL
LOGIC
OUTPUT
K
BW
x
REGISTER
BUFFER
(x=a,b,c,d or a,b)
OE
ZZ
36 or 18
DQa ~ DQd7 or DQa0 ~ DQb8
DQP0a ~ DQPd
TM
NtRAM
and No Turnaround Random Access MRemeorvy a.re3t.ra0deAmaprkrsiolf S2a0m0su6ng.
- 4 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
PIN CONFIGURATION(TOP VIEW)
NC/DQPc
1
DQPb/NC
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc0
2
DQc1
3
VDDQ
4
VSSQ
5
DQc2
6
DQc3
7
DQc4
8
DQc5
9
VSSQ
10
VDDQ
11
DQc6
12
100 Pin TQFP
(20mm x 14mm)
DQc7
13
VDD
14
VDD
15
VDD
VDD
16
VDD
VSS
17
ZZ
DQd0
18
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa/NC
DQd1
19
K7N163631B(512Kx36)
VDDQ
20
VSSQ
21
DQd2
22
DQd3
23
DQd4
24
DQd5
25
VSSQ
26
VDDQ
27
DQd6
28
DQd7
29
NC/DQPd
30
PIN NAME
SYMBOL
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A18
32,33,34,35,36,37,44 VDD
45,46,47,48,49,50,81 VSS
82,83,84,99,100
Power Supply(+3.3V) 14,15,16,41,65,66,91
Ground
17,40,67,90
ADV
WE
CLK
CKE
CS1
CS2
CS2
Address Advance/Load
85
No Connect
38,39,42,43
N.C.
Read/Write Control Input 88
Clock
89
Data Inputs/Outputs 52,53,56,57,58,59,62,63
Data Inputs/Outputs 68,69,72,73,74,75,78,79
Data Inputs/Outputs 2,3,6,7,8,9,12,13
Data Inputs/Outputs 18,19,22,23,24,25,28,29
Data Inputs/Outputs 51,80,1,30
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
or NC
Clock Enable
Chip Select
Chip Select
Chip Select
87
98
97
92
BWx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
86
64
31
Output Power Supply 4,11,20,27,54,61,70,77
(3.3V or 2.5V)
Output Ground
VDDQ
VSSQ
5,10,21,26,55,60,71,76
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
Rev. 3.0 April 2006
- 5 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
1
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQa0
DQa1
DQa2
VSSQ
VDDQ
DQa3
DQa4
VSS
2
N.C.
3
VDDQ
VSSQ
N.C.
4
5
6
N.C.
7
DQb8
DQb7
VSSQ
VDDQ
DQb6
DQb5
VDD
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
VDD
VDD
VDD
VDD
VSS
ZZ
DQb4
DQb3
VDDQ
VSSQ
DQb2
DQb1
DQb0
N.C.
DQa5
DQa6
VDDQ
VSSQ
DQa7
DQa8
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7N161831B(1Mx18)
VSSQ
VDDQ
N.C.
N.C.
N.C.
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A19
Address Inputs
32,33,34,35,36,37,44 VDD
45,46,47,48,49,50,80 VSS
81,82,83,84,99,100
Power Supply(+3.3V) 14,15,16,41,65,66,91
Ground
17,40,67,90
ADV
WE
CLK
CKE
CS1
CS2
CS2
Address Advance/Load
85
No Connect
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,95,96
N.C.
Read/Write Control Input 88
Clock
89
Clock Enable
Chip Select
Chip Select
Chip Select
87
98
Data Inputs/Outputs 58,59,62,63,68,69,72,73,74
Data Inputs/Outputs 8,9,12,13,18,19,22,23,24
DQa0~a8
DQb0~b8
97
92
BWx(x=a,b) Byte Write Inputs
93,94
86
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
Output Power Supply 4,11,20,27,54,61,70,77
(3.3V or 2.5V)
VDDQ
VSSQ
64
31
Output Ground
5,10,21,26,55,60,71,76
NOTE : A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
Rev. 3.0 April 2006
- 6 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)
K7N163631B(512Kx36)
1
2
3
4
5
6
7
8
9
10
A
11
NC
CS2
A
B
C
D
E
F
NC
A
CS1
BWc
BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CKE
WE
ADV
OE
A
NC
A
CS2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A
A
NC
DQPc
DQc
DQc
DQc
DQc
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
DQPb
DQb
DQb
DQb
DQb
ZZ
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
NC
G
H
J
DQd
DQd
DQd
DQd
DQPd
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
DQa
DQa
DQa
DQa
DQPa
NC
K
L
M
N
P
R
NC
TDI
A1*
TDO
TCK
LBO
NC
A
A
TMS
A0*
A
A
A
A
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
Address Inputs
VDD
VSS
Power Supply
Ground
A0,A1
ADV
WE
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
N.C.
No Connect
CLK
DQa
DQb
DQc
DQd
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
CKE
CS1
Clock Enable
Chip Select
CS2
Chip Select
CS2
Chip Select
DQPa~Pd
BWx
(x=a,b,c,d)
Byte Write Inputs
VDDQ
Output Power Supply
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
TCK
TMS
TDI
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
TDO
Rev. 3.0 April 2006
- 7 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)
K7N161831B(1Mx18)
1
NC
2
3
4
5
6
7
8
9
10
A
11
A
CS2
A
B
C
D
E
F
A
CS1
BWb
NC
NC
CKE
WE
ADV
OE
A
NC
A
CS2
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A
A
NC
NC
NC
DQb
DQb
DQb
DQb
VDD
NC
NC
NC
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
G
H
J
NC
DQb
DQb
DQb
DQb
DQPb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
NC
NC
K
L
NC
NC
M
N
P
R
NC
TDI
TMS
A1*
TDO
TCK
NC
LBO
A
A
A0*
A
A
A
A
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
Address Inputs
VDD
VSS
Power Supply
Ground
A0,A1
ADV
WE
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
No Connect
N.C.
CLK
CKE
CS1
CS2
CS2
Clock Enable
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
DQa
DQb
DQPa, Pb
Chip Select
Chip Select
Chip Select
BWx
(x=a,b)
Byte Write Inputs
Output Power Supply
VDDQ
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
TCK
TMS
TDI
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
TDO
Rev. 3.0 April 2006
- 8 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
FUNCTION DESCRIPTION
The K7N163631B and K7N161831B are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-
lined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO=High)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
BQ TABLE
(Linear Burst, LBO=Low)
Case 4
Case 1
Case 2
Case 3
LBO PIN
LOW
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
Rev. 3.0 April 2006
- 9 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
STATE DIAGRAM FOR NtRAMTM
WRITE
READ
BEGIN
READ
BEGIN
WRITE
WRITE
READ
DESELECT
BURST
READ
BURST
WRITE
BURST
BURST
COMMAND
ACTION
DS
DESELECT
READ
WRITE
BEGIN READ
BEGIN WRITE
BEGIN READ
BURST
BEGIN WRITE
CONTINUE DESELECT
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
Rev. 3.0 April 2006
- 10 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 CS2 CS2 ADV WE BWx OE
CKE CLK
ADDRESS ACCESSED
N/A
Operation
Not Selected
H
X
X
X
L
X
L
X
X
H
X
L
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
N/A
Not Selected
X
X
H
X
H
X
H
X
H
X
X
L
N/A
Not Selected
H
L
N/A
Not Selected Continue
Begin Burst Read Cycle
Continue Burst Read Cycle
NOP/Dummy Read
Dummy Read
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
X
L
X
L
H
L
L
H
H
X
X
X
X
X
X
L
X
L
H
L
Begin Burst Write Cycle
Continue Burst Write Cycle
NOP/Write Abort
Write Abort
X
L
X
L
H
L
X
L
L
H
H
X
X
X
X
X
H
X
X
X
Next Address
Current Address
Ignore Clock
Notes : 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by (↑).
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE(x36)
WE
H
L
BWa
X
BWb
X
BWc
X
BWd
X
OPERATION
READ
L
H
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
H
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
WRITE TRUTH TABLE(x18)
WE
BWa
X
BWb
OPERATION
H
X
H
L
READ
L
L
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ABORT/NOP
L
H
L
L
L
L
H
H
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
Rev. 3.0 April 2006
- 11 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
ASYNCHRONOUS TRUTH TABLE
Notes
OPERATION
ZZ
H
L
OE
I/O STATUS
High-Z
1. X means "Don′t Care".
Sleep Mode
X
2. Sleep Mode means power Sleep Mode of which stand-by current does
not depend on cycle time.
L
DQ
3. Deselected means power Sleep Mode of which stand-by current
depends on cycle time.
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
Deselected
L
X
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on Any Other Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 4.6
-0.3 to VDD+0.3
1.6
UNIT
V
VIN
V
PD
W
Storage Temperature
TSTG
TOPR
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
°C
Commercial
Industrial
Operating Temperature
-40 to 85
-10 to 85
Storage Temperature Range Under Bias
*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C)
PARAMETER
SYMBOL
VDD1
MIN
2.375
2.375
3.135
3.135
0
Typ.
2.5
2.5
3.3
3.3
0
MAX
2.625
2.625
3.465
3.465
0
UNIT
V
V
V
V
V
VDDQ1
VDD2
Supply Voltage
VDDQ2
VSS
Ground
Notes: 1. The above parameters are also guaranteed at industrial temperature range.
2. It should be VDDQ ≤ VDD
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
SYMBOL
CIN
TEST CONDITION
VIN=0V
MIN
-
-
MAX
5
6
UNIT
pF
Output Capacitance
COUT
VOUT=0V
pF
*Note : Sampled not 100% tested.
Overshoot Timing
Undershoot Timing
20% tCYC(MIN)
VIH
VDDQ+1.0V
VDDQ+0.5V
VDDQ
VSS
VSS-0.5V
VSS-1.0V
20% tCYC(MIN)
VIL
Rev. 3.0 April 2006
- 12 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
VDD=Max ; VIN=VSS to VDD
MIN
-2
-2
-
MAX
+2
UNIT NOTES
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
µA
µA
IOL
Output Disabled, Vout=VSS to VDDQ
+2
-25
-16
360
300
Device Selected, IOUT=0mA,
ZZ≤VIL , Cycle Time ≥ tCYC Min
Operating Current
Standby Current
ICC
ISB
mA
mA
mA
mA
1,2
-
Device deselected, IOUT=0mA, ZZ≤VIL,
f=Max, All Inputs≤0.2V or ≥ VDD-0.2V
-
-
-
170
150
130
Device deselected, IOUT=0mA, ZZ≤0.2V,
f=0, All Inputs=fixed (VDD-0.2V or 0.2V)
ISB1
ISB2
Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,
f=Max, All Inputs≤VIL or ≥VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL=8.0mA
IOH=-4.0mA
IOL=1.0mA
IOH=-1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
-
2.0
-0.3*
2.0
-0.3*
1.7
0.8
VIH
VIL
VDD+0.3**
0.7
3
3
VIH
VDD+0.3**
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. Data states are all zero.
4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
TEST CONDITIONS
PARAMETER
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 3.3/2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
VALUE
0 to 3.0V
0 to 2.5V
1.0V/ns
1.5V
VDDQ/2
See Fig. 1
* The above parameters are also guaranteed at industrial temperature range.
Rev. 3.0 April 2006
- 13 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
Output Load(A)
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50Ω
Dout
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
Dout
319Ω / 1667Ω
Zo=50Ω
353Ω / 1538Ω
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS
-25
-16
PARAMETER
SYMBOL
UNIT
MIN
4.0
-
MAX
MIN
6.0
-
MAX
Cycle Time
tCYC
tCD
-
-
ns
ns
Clock Access Time
2.6
3.5
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tOE
-
2.6
-
3.5
ns
tLZC
tOH
1.5
1.5
0
-
1.5
1.5
0
-
ns
-
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
ns
-
2.6
-
3.0
ns
-
2.6
-
-
3.0
-
ns
1.7
1.7
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
2
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
ns
Clock Low Pulse Width
tCL
-
-
ns
Address Setup to Clock High
CKE Setup to Clock High
tAS
-
-
ns
tCES
tDS
-
-
ns
Data Setup to Clock High
-
-
ns
Write Setup to Clock High (WE, BWX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
CKE Hold from Clock High
tWS
-
-
ns
tADVS
tCSS
tAH
-
-
ns
-
-
ns
-
-
ns
tCEH
tDH
-
-
ns
Data Hold from Clock High
-
-
ns
Write Hold from Clock High (WE, BWX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
-
-
ns
tADVH
tCSH
tPDS
tPUS
-
-
ns
-
-
ns
-
-
cycle
cycle
ZZ Low to Power Up
2
-
2
-
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
5. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.
The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,3.465V) than tHZC, which is a Max. parameter(worst case at 70°C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
Rev. 3.0 April 2006
- 14 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
ISB2
MIN
MAX
UNITS
mA
Current during SLEEP MODE
ZZ ≥ VIH
130
ZZ active to input ignored
tPDS
2
2
cycle
cycle
cycle
tPUS
ZZ inactive to input sampled
ZZ active to SLEEP current
tZZI
2
ZZ inactive to exit SLEEP current
tRZZI
0
SLEEP MODE WAVEFORM
K
tPDS
tPUS
ZZ setup cycle
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
DON′T CARE
Rev. 3.0 April 2006
- 15 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 Instruction
TDO Output
Notes
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
IDCODE
SAMPLE-Z
BYPASS
SAMPLE
Boundary Scan Register
Identification Register
Boundary Scan Register
Bypass Register
1
3
2
4
5
6
4
4
0
0
0
1
Boundary Scan Register
1
RESERVED Do Not Use
SRAM
CORE
1
1
BYPASS
BYPASS
Bypass Register
Bypass Register
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
TDI
BYPASS Reg.
Identification Reg.
Instruction Reg.
TDO
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
Control Signals
TAP Controller
TMS
TCK
TAP Controller State Diagram
1
0
Test Logic Reset
0
1
1
0
1
Run Test Idle
Select DR
0
Capture DR
0
Shift DR
1
Exit1 DR
0
Select IR
0
1
1
1
1
Capture IR
0
0
Shift IR
1
Exit1 IR
0
0
0
0
0
Pause DR
1
Pause IR
1
Exit2 IR
1
Exit2 DR
1
1
0
Update DR
0
Update IR
1
Rev. 3.0 April 2006
- 16 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
1 bits
ID Register
32 bits
32 bits
Boundary Scan
75 bits
512Kx36
1Mx18
3 bits
3 bits
1 bits
75 bits
ID REGISTER DEFINITION
Revision Number Part Configuration Vendor Definition Samsung JEDEC Code
Part
Start Bit(0)
(31:28)
0000
(27:18)
(17:12)
XXXXXX
XXXXXX
(11: 1)
512Kx36
1Mx18
00111 00100
00001001110
1
1
0000
01000 00011
00001001110
165FBGA BOUNDARY SCAN EXIT ORDER(x36)
165FBGA BOUNDARY SCAN EXIT ORDER(x18)
1
2
3
4
5
6
7
8
1R
6N
11P
8P
8R
9R
LBO
NC
NC
A
A
A
A
A
A
A
CLK
NC
NC
6B
11B
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
1K
1L
1M
2J
2K
2L
2M
1N
3P
3R
4R
4P
6P
6R
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
1
2
3
4
5
6
7
8
1R
6N
11P
8P
8R
9R
LBO
NC
NC
A
A
A
A
A
A
A
CLK
NC
NC
CS2
BWa
NC
BWb
NC
CS2
CS1
A
6B
11B
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
CS2
BWa
BWb
BWc
BWd
CS2
CS1
A
9P
9P
10P
10R
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
10G
10F
10E
10D
11C
11A
10A
10B
9A
10P
10R
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
11C
10F
10E
10D
10G
11A
10A
10B
9A
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
ZZ
ZZ
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
NC
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
NC
NC
NC
NC
A
A
A
A
A
ADV
OE
CKE
WE
A
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
NC
NC
NC
NC
A
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
A
1K
1L
1M
1N
2K
2L
2M
2J
A
A
A
ADV
OE
CKE
WE
3P
3R
4R
4P
6P
6R
A
A
A
A1
A
A
A
A1
9B
8A
8B
7A
9B
8A
8B
7A
A0
A0
7B
7B
NOTE, NC ; Don′t Care
Rev. 3.0 April 2006
- 17 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
JTAG DC OPERATING CONDITIONS
Parameter
Power Supply Voltage
Input High Level
Symbol
VDD
VIH
Min
3.135/2.375
2.0/1.7
-0.3
Typ
Max
3.465/2.625
VDD+0.3
0.8/0.7
-
Unit
V
Note
3.3/2.5
-
-
-
-
V
Input Low Level
VIL
V
Output High Voltage
Output Low Voltage
VOH
VOL
2.4/2.0
-
V
0.4/0.4
V
NOTE : The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Symbol
VIH/VIL
TR/TF
Min
3.0/0 , 2.5/0
Unit
V
Note
Input High/Low Level
Input Rise/Fall Time
1.0/1.0 , 1.0/1.0
VDDQ/2
ns
V
Input and Output Timing Reference Level
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
Note
TCK Cycle Time
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
-
-
5
-
5
-
5
-
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
5
-
5
-
0
10
JTAG TIMING DIAGRAM
TCK
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tCHDX
TMS
TDI
tDVCH
tSVCH
tCHSX
PI
(SRAM)
tCLQV
TDO
Rev. 3.0 April 2006
- 18 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
Rev. 3.0 April 2006
- 19 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
Rev. 3.0 April 2006
- 20 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
Rev. 3.0 April 2006
- 21 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
Rev. 3.0 April 2006
- 22 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
Rev. 3.0 April 2006
- 23 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
PACKAGE DIMENSIONS
Units ; millimeters/Inches
100-TQFP-1420A (Lead and Lead free package)
22.00
20.00
±
±
0.30
0.20
0~8
°
+ 0.10
- 0.05
0.127
16.00
14.00
±
0.30
0.10 MAX
±
0.20
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30
±0.10
0.10 MAX
1.40
±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
Rev. 3.0 April 2006
- 24 -
K7N163631B
K7N161831B
512Kx36 & 1Mx18 Pipelined NtRAMTM
165 FBGA PACKAGE DIMENSIONS (Lead and Lead free package)
13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
A
B
Top View
C
Side View
D
A
F
E
B
Bottom View
G
∅ H
E
Symbol
Value
15 ± 0.1
Units
mm
mm
mm
mm
Note
Symbol
Value
1.0
Units
mm
mm
mm
mm
Note
A
B
C
D
E
F
13 ± 0.1
14.0
10.0
1.3 ± 0.1
0.35 ± 0.05
G
H
0.5 ± 0.05
Rev. 3.0 April 2006
- 25 -
相关型号：
©2020 ICPDF网 联系我们和版权申明