K7N801801B-QC16/13_技术文档

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

Document Title

256Kx36 & 512Kx18-Bit Flow Through NtRAM^TM

Revision History

Rev. No.

History

Draft Date

Remark

0.0

0.1

0.2

1.0

1. Initial document.

May. 18. 2001

Aug. 11. 2001

Aug. 28. 2001

Nov. 16. 2001

Preliminary

Final

1. Add x32 org part and industrial temperature part

1. change scan order(1) form 4T to 6T at 119BGA(x18)

1. Final spec release

2. Change ISB2 form 50mA to 60mA

2.0

2.1

3.0

Change ordering information( remove 225MHz at Nt-Pipelined)

1. Delete 119BGA package

April. 01. 2002

April. 04. 2003

Nov. 17. 2003

Final

1. Remove x32 organization

2. Remove -85 speed bin

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 1 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

8Mb NtRAM(Flow Through / Pipelined) Ordering Information

Speed

Org.

Part Number

Mode

VDD

FT ; Access Time(ns)

PKG

Temp

Pipelined ; Cycle Time(MHz)

K7M801825B-QC(I)65/75

K7N801801B-QC(I)16/13

K7N801809B-QC(I)25

K7N801845B-QC(I)16/13

K7N801849B-QC(I)25

K7M803625B-QC(I)65/75

K7N803601B-QC(I)16/13

K7N803609B-QC(I)25

K7N803645B-QC(I)16/13

K7N803649B-QC(I)25

FlowThrough

Pipelined

FlowThrough

Pipelined

3.3

2.5

3.3

2.5

6.5/7.5 ns

167/133 MHz

250 MHz

C:

512Kx18

Commercial

Temperature

Range

167/133 MHz

250MHz

Q:

I:

100TQFP

6.5/7.5 ns

Industrial

Temperature

Range

167/133 MHz

250 MHz

256Kx36

167/133 MHz

250 MHz

- 2 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

256Kx36 & 512Kx18-Bit Flow Through NtRAM^TM

FEATURES

GENERAL DESCRIPTION

• 3.3V+0.165V/-0.165V Power Supply.

• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O

or 2.5V+0.4V/-0.125V for 2.5V I/O

• Byte Writable Function.

The K7M803625B and K7M801825B are

9,437,184-bit Synchronous Static SRAMs.

The NtRAM^TM, or No Turnaround Random Access Memory uti-

lizes all bandwidth in any combination of operating cycles.

Address, data inputs, and all control signals except output

enable and linear burst order are synchronized to input clock.

Burst order control must be tied "High or Low".

• Εnable clock and suspend operation.

• Single READ/WRITE control pin.

• Self-Timed Write Cycle.

• Three Chip Enable for simple depth expansion with no data

contention .

Asynchronous inputs include the sleep mode enable(ZZ).

Output Enable controls the outputs at any given time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-chip

write pulse generation

and provides increased timing flexibility for incoming signals.

For read cycles, Flow-Through SRAM allows output data to

simply flow freely from the memory array.

The K7M803625B and K7M801825B are implemented with

SAMSUNG′s high performance CMOS technology and is avail-

able in 100pin TQFP and Multiple power and ground pins mini-

mize ground bounce.

• A interleaved burst or a linear burst mode.

• Asynchronous output enable control.

• Power Down mode.

• TTL-Level Three-State Outputs.

• 100-TQFP-1420A

• Operating in commeical and industrial temperature range.

FAST ACCESS TIMES

Parameter

Cycle Time

Symbol -65 -75 Unit

tCYC

tCD

7.5 8.5 ns

6.5 7.5 ns

3.5 3.5 ns

Clock Access Time

Output Enable Access Time

tOE

LOGIC BLOCK DIAGRAM

LBO

~A

BURST

A′

0

~A′1

A [0:17]or

ADDRESS

COUNTER

A

0

1

256Kx36 , 512Kx18

MEMORY

A [0:18]

ADDRESS

REGISTER

A2

~A17 or A ~A18

2

ARRAY

WRITE

ADDRESS

CLK

CKE

K

REGISTER

DATA-IN

K

REGISTER

CS

1

2

ADV

WE

CONTROL

LOGIC

BW

x

(x=a,b,c,d or a,b)

BUFFER

OE

ZZ

36 or 18

DQa ~ DQd

7

or DQa

0

~ DQb

8

DQP⁰a ~ DQPd

TM

NtRAM and No Turnaround Random Access Memory are trademarks of Samsung,

and its architecture and functionalities are supported by NEC and Toshiba.

- 3 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

PIN CONFIGURATION(TOP VIEW)

DQPb

80

DQPc

1

DQb7

79

DQc0

2

DQb6

78

DQc1

3

VDDQ

77

VDDQ

4

VSSQ

76

VSSQ

5

DQb5

75

DQc2

6

DQb4

74

DQc3

7

DQb3

73

DQc4

8

DQb2

72

DQc5

9

VSSQ

71

VSSQ

10

VDDQ

70

VDDQ

11

DQb1

DQc6

12

69

100 Pin TQFP

DQb0

68

DQc7

13

VSS

67

Vss

14

VSS

66

VDD

15

(20mm x 14mm)

VDD

65

VDD

16

ZZ

64

VSS

DQd0

DQd1

VDDQ

VSSQ

DQd2

DQd3

DQd4

DQd5

VSSQ

VDDQ

DQd6

DQd7

DQPd

17

18

19

20

21

22

23

24

25

26

27

28

29

30

DQa7

DQa6

VDDQ

VSSQ

DQa5

DQa4

DQa3

DQa2

VSSQ

VDDQ

DQa1

DQa0

DQPa

63

62

61

60

59

58

57

56

55

54

53

52

51

K7M803625B(256Kx36)

PIN NAME

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A17

Address Inputs

32,33,34,35,36,37,44 VDD

45,46,47,48,49,50,81 VSS

Power Supply(+3.3V) 15,16,41,65,91

Ground

14,17,40,66,67,90

38,39,42,43,84

82,83,99,100

85

N.C.

No Connect

ADV

WE

CLK

CKE

CS1

CS2

Address Advance/Load

Read/Write Control Input 88

DQa0~a7

DQb0~b7

DQc0~c7

DQd0~d7

DQPa~Pd

Data Inputs/Outputs 52,53,56,57,58,59,62,63

68,69,72,73,74,75,78,79

2,3,6,7,8,9,12,13

Clock

89

Clock Enable

Chip Select

87

98

18,19,22,23,24,25,28,29

51,80,1,30

97

92

BWx(x=a,b,c,d) Byte Write Inputs

93,94,95,96

Output Power Supply 4,11,20,27,54,61,70,77

(2.5V or 3.3V)

VDDQ

VSSQ

OE

ZZ

LBO

Output Enable

Power Sleep Mode

Burst Mode Control

86

64

31

Output Ground

5,10,21,26,55,60,71,76

Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.

2. A⁰and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

- 4 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

PIN CONFIGURATION(TOP VIEW)

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A10

N.C.

VDDQ

VSSQ

N.C.

DQb8

DQb7

VSSQ

VDDQ

DQb6

DQb5

VSS

1

N.C.

VDDQ

VSSQ

N.C.

DQa0

DQa1

DQa2

VSSQ

VDDQ

DQa3

DQa4

VSS

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

VSS

VDD

(20mm x 14mm)

VDD

VSS

ZZ

DQb4

DQb3

VDDQ

VSSQ

DQb2

DQb1

DQb0

N.C.

VSSQ

VDDQ

N.C.

DQa5

DQa6

VDDQ

VSSQ

DQa7

DQa8

N.C.

VSSQ

VDDQ

N.C.

K7M801825B(512Kx18)

PIN NAME

SYMBOL

A0 - A18

PIN NAME

Address Inputs

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

32,33,34,35,36,37,44 VDD

45,46,47,48,49,50,80 VSS

81,82,83,99,100

85

Power Supply(+3.3V) 15,16,41,65,91

Ground

No Connect

14,17,40,66,67,90

N.C.

1,2,3,6,7,25,28,29,30,

38,39,42,43,51,52,53,

56,57,75,78,79,84,95,96

ADV

WE

CLK

CKE

CS1

CS2

Address Advance/Load

Read/Write Control Input 88

Clock

89

Clock Enable

Chip Select

87

DQa0~a8

DQb0~b8

Data Inputs/Outputs

58,59,62,63,68,69,72,73,74

8,9,12,13,18,19,22,23,24

98

97

92

BWx(x=a,b) Byte Write Inputs

93,94

86

VDDQ

VSSQ

Output Power Supply 4,11,20,27,54,61,70,77

(2.5V or 3.3V)

Output Ground

OE

ZZ

LBO

Output Enable

Power Sleep Mode

Burst Mode Control

64

31

5,10,21,26,55,60,71,76

Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.

2. A⁰and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

- 5 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

FUNCTION DESCRIPTION

The K7M803625B and K7M801825B are NtRAM^TMdesigned to sustain 100% bus bandwidth by eliminating turnaround cycle when

there is transition from Read to Write, or vice versa.

All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.

All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the

burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next

operation.

Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous

inputs are ignored and the internal device registers will hold their previous values.

NtRAM^TMlatches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)

are active .

Output Enable(OE) can be used to disable the output at any given time.

Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the

address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven

high, and ADV driven low. Data appears at the outputs within the same clock cycle as the address for the data. Also during read

operation OE must be driven low for the device to drive out the requested data.

Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The Flow

Through NtRAM^TMuses a late write cycle to utilize 100% of the bandwidth.

At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required one cycle

later.

Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is

provided by the external address. The burst address counter wraps around to its initial state upon completion.

The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.

And when this pin is high, Interleaved burst sequence is selected.

During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles.

At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up

time.

BURST SEQUENCE TABLE

(Interleaved Burst, LBO=High)

Case 4

Case 1

Case 2

Case 3

LBO PIN

HIGH

A1

A0

A1

A0

A1

A0

A1

A0

First Address

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

BQ TABLE

(Linear Burst, LBO=Low)

Case 4

Case 2

Case 3

LBO PIN

LOW

A1

A0

A1

A0

A1

A0

A1

A0

First Address

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

- 6 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

STATE DIAGRAM FOR NtRAM^TM

WRITE

READ

BEGIN

READ

BEGIN

WRITE

READ

DESELECT

BURST

READ

BURST

WRITE

BURST

COMMAND

ACTION

DS

DESELECT

READ

WRITE

BEGIN READ

BEGIN WRITE

BEGIN READ

BURST

BEGIN WRITE

CONTINUE DESELECT

Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does

not change the state of the device.

2. States change on the rising edge of the clock(CLK)

- 7 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

CS1

H

X

L

CS2 CS2 ADV WE BWx OE

CKE CLK

ADDRESS ACCESSED

N/A

OPERATION

Not Selected

X

L

X

H

X

L

X

H

X

H

X

L

X

L

X

L

H

↑

N/A

Not Selected

X

H

X

H

X

H

X

H

X

L

N/A

Not Selected

H

L

N/A

Not Selected Continue

Begin Burst Read Cycle

Continue Burst Read Cycle

NOP/Dummy Read

Dummy Read

External Address

Next Address

External Address

Next Address

External Address

Next Address

N/A

X

L

X

L

H

L

H

X

L

X

L

H

L

Begin Burst Write Cycle

Continue Burst Write Cycle

NOP/Write Abort

Write Abort

X

L

X

L

H

L

X

L

H

X

H

X

Next Address

Current Address

Ignore Clock

Notes : 1. X means "Don′t Care".

2. The rising edge of clock is symbolized by (↑).

3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.

4. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

5. Operation finally depends on status of asynchronous input pins(ZZ and OE).

WRITE TRUTH TABLE( x36)

WE

H

L

BWa

X

BWb

X

BWc

X

BWd

X

Operation

READ

L

H

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c

WRITE BYTE d

WRITE ALL BYTEs

WRITE ABORT/NOP

L

H

L

H

L

H

L

H

L

H

L

H

Notes : 1. X means "Don′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).

WRITE TRUTH TABLE(x18)

WE

H

BWa

X

BWb

OPERATION

X

H

L

READ

L

WRITE BYTE a

WRITE BYTE b

WRITE ALL BYTEs

WRITE ABORT/NOP

L

H

L

H

Notes : 1. X means "Don′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).

- 8 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

ASYNCHRONOUS TRUTH TABLE

Notes

I/O STATUS

Operation

ZZ

H

L

OE

1. X means "Don′t Care".

Sleep Mode

X

High-Z

DQ

2. Sleep Mode means power Sleep Mode of which stand-by current does

not depend on cycle time.

L

3. Deselected means power Sleep Mode of which stand-by current

depends on cycle time.

Read

L

H

X

High-Z

Write

L

Din, High-Z

High-Z

Deselected

L

X

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Voltage on VDD Supply Relative to VSS

Voltage on Any Other Pin Relative to VSS

Power Dissipation

SYMBOL

VDD

RATING

-0.3 to 4.6

-0.3 to VDD+0.3

1.4

UNIT

V

VIN

V

PD

W

Storage Temperature

TSTG

TOPR

TBIAS

-65 to 150

0 to 70

°C

Commercial

Industrial

Operating Temperature

-40 to 85

-10 to 85

Storage Temperature Range Under Bias

*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING CONDITIONS at 3.3V I/O(0°C ≤ TA ≤ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

VDD

MIN

3.135

0

Typ.

3.3

0

MAX

3.465

0

UNIT

V

VDDQ

VSS

* The above parameters are also guaranteed at industrial temperature range.

OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

VDD

MIN

3.135

2.375

0

Typ.

3.3

2.5

0

MAX

3.465

2.9

UNIT

V

VDDQ

VSS

0

* The above parameters are also guaranteed at industrial temperature range.

CAPACITANCE*(TA=25°C, f=1MHz)

PARAMETER

SYMBOL

CIN

TEST CONDITION

VIN=0V

MIN

-

MAX

5

7

UNIT

pF

Input Capacitance

Output Capacitance

COUT

VOUT=0V

*Note : Sampled not 100% tested.

- 9 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)

PARAMETER

SYMBOL

TEST CONDITIONS

VDD=Max ; VIN=VSS to VDD

MIN

MAX

+2

UNIT NOTES

µA

Input Leakage Current(except ZZ)

Output Leakage Current

IIL

-2

-

IOL

Output Disabled,

+2

-65

-75

-65

300

280

140

Device Selected , IOUT=0mA,

ZZ≤VIL , Cycle Time ≥ tCYC Min

Operating Current

Standby Current

ICC

mA

1,2

-

Device deselected, IOUT=0mA,

ZZ≤VIL, f=Max,

All Inputs≤0.2V or ≥ VDD-0.2V

-

ISB

mA

-75

-

130

100

60

Device deselected, IOUT=0mA, ZZ≤0.2V, f=0,

All Inputs=fixed (VDD-0.2V or 0.2V)

ISB1

ISB2

mA

Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,

f=Max, All Inputs≤VIL or ≥VIH

Output Low Voltage(3.3V I/O)

Output High Voltage(3.3V I/O)

Output Low Voltage(2.5V I/O)

Output High Voltage(2.5V I/O)

Input Low Voltage(3.3V I/O)

Input High Voltage(3.3V I/O)

Input Low Voltage(2.5V I/O)

Input High Voltage(2.5V I/O)

VOL

VOH

VOL

VOH

VIL

IOL=8.0mA

IOH=-4.0mA

IOL=1.0mA

IOH=-1.0mA

-

0.4

V

2.4

-

0.4

-

2.0

-0.3*

2.0

-0.3*

1.7

0.8

VDD+0.3**

0.7

3

VIH

VIL

VIH

VDD+0.3**

Notes : 1. The above parameters are also guaranteed at industrial temperature range.

2. Reference AC Operating Conditions and Characteristics for input and timing.

3. Data states are all zero.

4. In Case of I/O Pins, the Max. V^IH=VDDQ+0.3V.

VIH

VSS

VSS-1.0V

20% tCYC(MIN)

T_(VEST CONDITIONS

DD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, T

A

=0to70 C)

°

Parameter

Value

0 to 3.0V

0 to 2.5V

1.0V/ns

1.5V

Input Pulse Level(for 3.3V I/O)

Input Pulse Level(for 2.5V I/O)

Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)

Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)

Input and Output Timing Reference Levels for 3.3V I/O

Input and Output Timing Reference Levels for 2.5V I/O

Output Load

VDDQ/2

See Fig. 1

* The above parameters are also guaranteed at industrial temperature range.

- 10 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

Output Load(A)

Output Load(B),

(for tLZC, tLZOE, tHZOE & tHZC)

+3.3V for 3.3V I/O

RL=50Ω

30pF*

Dout

/+2.5V for 2.5V I/O

VL=1.5V for 3.3V I/O

VDDQ/2 for 2.5V I/O

319Ω / 1667Ω

Dout

Zo=50Ω

353Ω / 1538Ω

5pF*

* Including Scope and Jig Capacitance

Fig. 1

AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)

-65

-75

PARAMETER

SYMBOL

UNIT

MAX

MIN

7.5

-

MAX

-

MIN

8.5

-

Cycle Time

tCYC

tCD

-

ns

Clock Access Time

6.5

7.5

Output Enable to Data Valid

Clock High to Output Low-Z

Output Hold from Clock High

Output Enable Low to Output Low-Z

Output Enable High to Output High-Z

Clock High to Output High-Z

Clock High Pulse Width

tOE

-

3.5

-

3.5

ns

tLZC

tOH

2.5

0

-

2.5

0

-

ns

-

ns

tLZOE

tHZOE

tHZC

tCH

-

ns

-

3.5

-

3.5

ns

-

3.8

-

4.0

-

ns

2.5

1.5

0.5

2

2.8

2.0

0.5

2

ns

Clock Low Pulse Width

tCL

-

ns

Address Setup to Clock High

CKE Setup to Clock High

tAS

-

ns

tCES

tDS

-

ns

Data Setup to Clock High

-

ns

Write Setup to Clock High (WE, BWX)

Address Advance Setup to Clock High

Chip Select Setup to Clock High

Address Hold from Clock High

CKE Hold from Clock High

tWS

-

ns

tADVS

tCSS

tAH

-

ns

-

ns

-

ns

tCEH

tDH

-

ns

Data Hold from Clock High

-

ns

Write Hold from Clock High (WE, BWX)

Address Advance Hold from Clock High

Chip Select Hold from Clock High

ZZ High to Power Down

tWH

-

ns

tADVH

tCSH

tPDS

tPUS

-

ns

-

ns

-

cycle

ZZ Low to Power Up

2

-

2

-

Notes : 1. The above parameters are also guaranteed at industrial temperature range.

2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled

low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.

4. A write cycle is defined by WE low having been registerd into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,

Both cases must meet setup and hold times.

5. To avoid bus contention, At a given vlotage and temperature t^LZCis more than tHZC.

The soecs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions

(0°C,3.465V) than t^HZC, which is a Max. parameter(worst case at 70°C,3.135V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperatue.

- 11 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

SLEEP MODE

SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

SLEEP MODE is dictated by the length of time the ZZ is in a High state.

After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z

The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.

When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP

MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-

ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given

while the SRAM is transitioning out of SLEEP MODE.

SLEEP MODE ELECTRICAL CHARACTERISTICS

DESCRIPTION

Current during SLEEP MODE

CONDITIONS

SYMBOL

ISB2

MIN

MAX

60

UNITS

mA

ZZ ≥ VIH

ZZ active to input ignored

tPDS

2

cycle

tPUS

ZZ inactive to input sampled

ZZ active to SLEEP current

tZZI

2

ZZ inactive to exit SLEEP current

tRZZI

0

SLEEP MODE WAVEFORM

K

tPDS

tPUS

ZZ setup cycle

ZZ recovery cycle

ZZ

tZZI

Isupply

ISB2

tRZZI

All inputs

Deselect or Read Only

(except ZZ)

Normal

operation

cycle

Outputs

(Q)

High-Z

DON′T CARE

- 12 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

- 13 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

- 14 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

- 15 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

- 16 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

- 17 -

Nov. 2003

Rev 3.0

K7M803625B

K7M801825B

256Kx36 & 512Kx18 Flow-Through NtRAM^TM

PACKAGE DIMENSIONS

Units ; millimeters/Inches

100-TQFP-1420A

22.00

20.00

±

0.30

0.20

0~8°

+ 0.10

- 0.05

±

0.127

16.00

14.00

±

0.30

0.10 MAX

±

0.20

(0.83)

0.50 ±0.10

#1

0.65

(0.58)

0.30

±0.10

0.10 MAX

1.40

±0.10

1.60 MAX

0.05 MIN

0.50 ±0.10

- 18 -

Nov. 2003

Rev 3.0


型号：	K7N801801B-QC16/13
厂家：	SAMSUNG
描述：	256Kx36 & 512Kx18-Bit Flow Through NtRAM 256Kx36和512Kx18位流经NtRAM
文件：	总18页 (文件大小：376K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K7N801801B-QC16/13 [SAMSUNG]

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