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K7P163611M-HC33 [SAMSUNG]

Standard SRAM, 512KX36, 1.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FLIP CHIP, BGA-119;
K7P163611M-HC33
型号： K7P163611M-HC33
厂家： SAMSUNG    SAMSUNG
描述：

Standard SRAM, 512KX36, 1.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FLIP CHIP, BGA-119

静态存储器
文件： 总13页 (文件大小：249K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
Document Title  
512Kx36 & 1Mx18 Synchronous Pipelined SRAM  
Revision History  
Draft Date  
Remark  
Rev. No.  
History  
Aug. 2000  
Advance  
Rev. 0.0  
- Initial Document  
Dec. 2001  
Final  
Rev. 1.0  
- Final specification release  
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the  
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters  
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.  
Rev 1.0  
Dec. 2001  
- 1 -  
K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
512Kx36 & 1Mx18 Synchronous Pipelined SRAM  
FEATURES  
• 512Kx36 or 1Mx18 Organizations.  
• 3.3V VDD/1.5V VDDQ (1.9V max VDDQ).  
• HSTL Input and Output Levels.  
Maximum Access  
Part Number  
Organization  
Frequency  
Time  
• Differential, HSTL Clock Inputs K, K.  
• Synchronous Read and Write Operation  
• Registered Input and Registered Output  
• Internal Pipeline Latches to Support Late Write.  
• Byte Write Capability(four byte write selects, one for each 9bits)  
• Synchronous or Asynchronous Output Enable.  
• Power Down Mode via ZZ Signal.  
• Programmable Impedance Output Drivers.  
• JTAG Boundary Scan (subset of IEEE std. 1149.1).  
• 119(7x17) Flip Chip Ball Grid Array Package(14mmx22mm).  
K7P163611M-HC33  
K7P163611M-HC30  
K7P163611M-HC25  
K7P161811M-HC33  
K7P161811M-HC30  
K7P161811M-HC25  
333MHz  
300MHz  
250MHz  
333MHz  
300MHz  
250MHz  
1.5  
1.6  
2.0  
1.5  
1.6  
2.0  
512Kx36  
1Mx18  
FUNCTIONAL BLOCK DIAGRAM  
19 or 20  
SA[0:18]  
Read  
or [0:19]  
2:1  
MUX  
Memory Array  
512Kx36  
1Mx18  
Address  
Dec.  
Register  
Clock  
Buffer  
K,K  
Data Out  
36 or 18  
Data In  
36 or 18  
19 or 20  
Write  
Address  
Register  
W/D  
Array  
S/A Array  
36 or 18  
MUX0  
36 or 18  
36 or 18  
36 or 18  
WAY  
Data In  
Register  
(2 stage)  
Data Out  
Register  
SS  
Control  
Register  
Control  
Logic  
E
SW  
ZZ  
36 or 18  
OE  
G
36 or 18  
36 or 18  
XDIN  
Internal  
Clock  
Generator  
DQ  
PIN DESCRIPTION  
Pin Name  
Pin Description  
Pin Name  
Pin Description  
Asynchronous Power Down  
K, K  
SAn  
DQn  
SS  
Differential Clocks  
ZZ  
ZQ  
Synchronous Address Input  
Output Driver Impedance Control  
JTAG Test Clock  
Bi-directional Data Bus  
TCK  
TMS  
TDI  
Synchronous Select  
JTAG Test Mode Select  
JTAG Test Data Input  
JTAG Test Data Output  
HSTL Input Reference Voltage  
Power Supply  
SW  
Synchronous Global Write Enable  
Synchronous Byte a Write Enable  
Synchronous Byte b Write Enable  
Synchronous Byte c Write Enable  
Synchronous Byte d Write Enable  
Read Protocol Mode Pins (M1=VSS, M2=VDDQ)  
Asynchronous Output Enable  
SWa  
SWb  
SWc  
SWd  
M1, M2  
G
TDO  
VREF  
VDD  
VDDQ  
VSS  
Output Power Supply  
GND  
NC  
No Connection  
Rev 1.0  
Dec. 2001  
- 2 -  
K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
PACKAGE PIN CONFIGURATIONS(TOP VIEW)  
K7P163611M(512Kx36)  
1
2
3
4
NC  
NC  
VDD  
ZQ  
SS  
G
5
6
7
A
B
C
D
E
F
VDDQ  
NC  
SA  
SA  
SA  
SA  
VDDQ  
NC  
SA  
SA  
SA  
SA  
NC  
SA  
SA  
SA  
SA  
NC  
DQc  
DQc  
VDDQ  
DQc  
DQc  
VDDQ  
DQd  
DQd  
VDDQ  
DQd  
DQd  
NC  
DQc  
DQc  
DQc  
DQc  
DQc  
VDD  
DQd  
DQd  
DQd  
DQd  
DQd  
SA  
VSS  
VSS  
VSS  
SWc  
VSS  
VREF  
VSS  
SWd  
VSS  
VSS  
VSS  
M1  
VSS  
VSS  
VSS  
SWb  
VSS  
VREF  
VSS  
SWa  
VSS  
VSS  
VSS  
M2  
DQb  
DQb  
DQb  
DQb  
DQb  
VDD  
DQa  
DQa  
DQa  
DQa  
DQa  
SA  
DQb  
DQb  
VDDQ  
DQb  
DQb  
VDDQ  
DQa  
DQa  
VDDQ  
DQa  
DQa  
NC  
G
H
J
NC  
NC  
VDD  
K
K
L
K
M
N
P
R
T
SW  
SA  
SA  
VDD  
SA  
TCK  
NC  
NC  
SA  
SA  
NC  
ZZ  
U
VDDQ  
TMS  
TDI  
TDO  
NC  
VDDQ  
K7P161811M(1Mx18)  
1
2
3
4
NC  
NC  
VDD  
ZQ  
SS  
G
5
6
7
A
B
C
D
E
F
VDDQ  
NC  
SA  
SA  
SA  
SA  
VDDQ  
NC  
SA  
SA  
SA  
SA  
NC  
SA  
SA  
SA  
SA  
NC  
DQb  
NC  
NC  
VSS  
VSS  
VSS  
SWb  
VSS  
VREF  
VSS  
NC  
VSS  
VSS  
VSS  
M1  
VSS  
VSS  
VSS  
NC  
DQa  
NC  
NC  
DQb  
NC  
DQa  
VDDQ  
DQa  
NC  
VDDQ  
NC  
DQa  
NC  
G
H
J
DQb  
NC  
NC  
NC  
VDD  
K
DQb  
VDDQ  
NC  
VSS  
VREF  
VSS  
SWa  
VSS  
VSS  
VSS  
M2  
DQa  
VDD  
NC  
VDD  
DQb  
NC  
VDDQ  
DQa  
NC  
K
L
DQb  
VDDQ  
DQb  
NC  
K
DQa  
NC  
M
N
P
R
T
DQb  
NC  
SW  
SA  
SA  
VDD  
NC  
TCK  
VDDQ  
NC  
DQa  
NC  
DQb  
SA  
DQa  
NC  
NC  
SA  
NC  
SA  
SA  
SA  
SA  
ZZ  
U
VDDQ  
TMS  
TDI  
TDO  
NC  
VDDQ  
Rev 1.0  
Dec. 2001  
- 3 -  
K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
FUNCTION DESCRIPTION  
The K7P163611M and K7P161811M are 18,874,368 bit Synchronous Pipeline Mode SRAM. It is organized as 524,288 words of 36  
bits(or 1,048,576 words of 18 bits)and is implemented in SAMSUNG¢s advanced CMOS technology.  
Single differential HSTL level K clocks are used to initiate read/write operation and all internal operations are self-timed. At the rising  
edge of K clock, all Addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are updated  
from output registers at the next rising edge of K clock. An internal write data buffer allows write data to follow one cycle after  
addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.  
Read Operation  
During read operations, addresses and controls are registered during the first rising edge of K clock and then the internal array is  
read between first rising and falling edges of K clock. Data outputs are updated from output registers off the falling edge of K clock.  
During consecutive read operations where the address is the same, the data output must be held constant without any glitches. This  
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-  
ple SRAM cycles to perform a single read operation.  
Write Operation(Late Write)  
During write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered at the  
following rising edge of K clock. Write addresses and data inputs are stored in the data in registers until the next write operation, and  
only at the next write opeation are data inputs fully written into SRAM array. Byte write operation is supported using SW[a:d] and the  
timing of SW[a:d] is the same as the SW signal.  
Bypass Read Operation  
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are  
identical. For this case, data outputs are from the data in registers instead of SRAM array. Bypass read operation occurs on a byte to  
byte basis. If only one byte is written during a write operation but a read operation is required on the same address, a partial bypass  
read operation occurs since the new byte data is from the data in registers while the remaing bytes are from SRAM arry.  
Sleep Mode  
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored  
and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep  
mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all  
pending operations have completed, since any pending operation will not guaranteed once sleep mode is initiated. Normal opera-  
tions can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.  
Mode Control  
There are two mode control select pins (M1 and M2) used to set the proper read protocol. This SRAM supports single clock pipelined  
operating mode. For proper specified device operation, M1 must be connected to VSS and M2 must be connected to VDDQ. These  
mode pins must be set at power-up and must not change during device operation.  
Programmable Impedance Output Driver  
The data output driver impedance is adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and is equal to RQ/5.  
For example, 250W resistor will give an output impedance of 50W. Output driver impedance tolerance is 15% by test(10% by design)  
and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates occur early in cycles that  
do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In all cases impedance  
updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. Imped-  
ance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is selected or not and  
proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 continuous read cycles  
have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are no power up  
requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-  
read cycles. The output buffers can also be programmed in a minimum impedance configuration by connecting ZQ to VSS or VDDQ.  
Power-Up/Power-Down Supply Voltage Sequencing  
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied  
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage  
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ  
does not exceed VDD by more than 0.5V during power-down.  
Rev 1.0  
Dec. 2001  
- 4 -  
K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
TRUTH TABLE  
K
X
X
•
ZZ  
H
L
G
X
H
L
SS  
X
X
H
L
SW SWa SWb SWc SWd DQa DQb DQc DQd  
Operation  
Hi-Z Hi-Z Hi-Z Hi-Z Power Down Mode. No Operation  
Hi-Z Hi-Z Hi-Z Hi-Z Output Disabled.  
X
X
X
H
L
L
L
L
L
L
X
X
X
X
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
H
L
X
X
X
X
H
H
H
H
L
L
Hi-Z Hi-Z Hi-Z Hi-Z Output Disabled. No Operation  
DOUT DOUT DOUT DOUT Read Cycle  
•
L
L
•
L
X
X
X
X
X
X
L
Hi-Z Hi-Z Hi-Z Hi-Z No Bytes Written  
•
L
L
DIN  
Hi-Z Hi-Z Hi-Z Write first byte  
Hi-Z Hi-Z Write second byte  
•
L
L
H
H
H
L
Hi-Z  
DIN  
•
L
L
H
H
L
Hi-Z Hi-Z  
DIN  
Hi-Z Write third byte  
DIN Write fourth byte  
DIN Write all bytes  
•
L
L
H
L
Hi-Z Hi-Z Hi-Z  
•
L
L
L
DIN  
DIN  
DIN  
NOTE : K & K are complementary  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Core Supply Voltage Relative to VSS  
Output Supply Voltage Relative to VSS  
Voltage on any pin Relative to VSS  
Output Short-Circuit Current(per I/O)  
Storage Temperature  
Symbol  
Value  
-0.5 to 3.9  
Unit  
V
VDD  
VDDQ  
VIN  
-0.5 to 2.3  
V
-0.5 to VDDQ+0.5 (2.3V MAX)  
25  
V
IOUT  
TSTR  
mA  
°C  
-55 to 125  
NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.  
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only  
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not  
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
RECOMMENDED DC OPERATING CONDITIONS  
Parameter  
Core Power Supply Voltage  
Output Power Supply Voltage  
Input High Level  
Symbol  
Min  
3.15  
1.4  
Typ  
3.3  
1.5  
-
Max  
3.45  
Unit  
V
Note  
VDD  
VDDQ  
1.9  
V
VIH  
VREF+0.1  
-0.3  
VDDQ+0.3  
VREF-0.1  
0.95  
V
Input Low Level  
VIL  
-
V
Input Reference Voltage  
Clock Input Signal Voltage  
Clock Input Differential Voltage  
Clock Input Common Mode Voltage  
VREF  
0.68  
-0.3  
0.75  
-
V
VIN-CLK  
VDIF-CLK  
VCM-CLK  
VDDQ+0.3  
VDDQ+0.3  
0.95  
V
0.1  
-
V
0.68  
0.75  
V
Rev 1.0  
Dec. 2001  
- 5 -  
K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
PIN CAPACITANCE  
Parameter  
Input Capacitance  
Symbol  
CIN  
Test Condition  
VIN=0V  
Min  
Max  
Unit  
pF  
-
-
4
5
Data Output Capacitance  
COUT  
VOUT=0V  
pF  
NOTE : Periodically sampled and not 100% tested.(TA=25°C, f=1MHz)  
DC CHARACTERISTICS  
Parameter  
Symbol  
Min  
Max  
Unit  
Note  
IDD33  
IDD30  
IDD25  
700  
620  
550  
Average Power Supply Operating Current-x36  
(VIN=VIH or VIL, ZZ & SS=VIL)  
-
mA  
1, 2  
IDD33  
IDD30  
IDD25  
650  
570  
500  
Average Power Supply Operating Current-x18  
(VIN=VIH or VIL, ZZ & SS=VIL)  
-
mA  
1, 2  
Power Supply Standby Current  
(VIN=VIH or VIL, ZZ=VIH)  
ISBZZ  
ISBSS  
ILI  
-
150  
200  
1
mA  
mA  
mA  
mA  
1
1
Active Standby Power Supply Current  
(VIN=VIH or VIL, SS=VIH, ZZ=VIL)  
-
Input Leakage Current  
(VIN=VSS or VDDQ)  
-1  
-1  
Output Leakage Current  
(VOUT=VSS or VDDQ, DQ in High-Z)  
ILO  
1
Output High Voltage(Programmable Impedance Mode)  
Output Low Voltage(Programmable Impedance Mode)  
Output High Voltage(IOH=-0.1mA)  
VOH1  
VOL1  
VOH2  
VOL2  
VOH3  
VOL3  
VDDQ/2  
VSS  
VDDQ  
VDDQ/2  
VDDQ  
0.2  
V
V
V
V
V
V
3,5  
4,5  
6
VDDQ-0.2  
VSS  
Output Low Voltage(IOL=0.1mA)  
6
Output High Voltage(IOH=-6mA)  
VDDQ-0.4  
VSS  
VDDQ  
0.4  
6
Output Low Voltage(IOL=6mA)  
6
NOTE :1. Minimum cycle. IOUT=0mA.  
2. 50% read cycles.  
3. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175W £ RQ £ 350W.  
4. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175W £ RQ £ 350W.  
5. Programmable Impedance Output Buffer Mode. The ZQ pin is connected to VSS through RQ.  
6. Minimum Impedance Output Buffer Mode. The ZQ pin is connected to VSS or VDDQ.  
Rev 1.0  
Dec. 2001  
- 6 -  
K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
AC TEST CONDITIONS (TA=0 to 70°C, VDD=3.15 -3.45V, VDDQ=1.5V)  
Parameter  
Core Power Supply Voltage  
Symbol  
VDD  
Value  
3.15~3.45  
1.5  
Unit  
V
Output Power Supply Voltage  
Input High/Low Level  
VDDQ  
V
VIH/VIL  
VREF  
1.25/0.25  
0.75  
V
Input Reference Level  
V
Input Rise/Fall Time  
TR/TF  
0.5/0.5  
0.75  
ns  
V
Input and Out Timing Reference Level  
Clock Input Timing Reference Level  
NOTE : Parameters are tested with RQ=250W and VDDQ=1.5V.  
Cross Point  
V
AC TEST OUTPUT LOAD  
50W  
0.75V  
50W  
50W  
5pF  
25W  
DQ  
0.75V  
50W  
0.75V  
5pF  
AC CHARACTERISTICS  
-33  
-30  
-25  
Parameter  
Symbol  
Unit  
Note  
Min  
3.0  
1.2  
1.2  
-
Max  
Min  
3.3  
1.3  
1.3  
-
Max  
Min  
4.0  
1.6  
1.6  
-
Max  
Clock Cycle Time  
tKHKH  
tKHKL  
tKLKH  
tKHQV  
tKHQX  
tAVKH  
tKHAX  
tDVKH  
tKHDX  
tWVKH  
tKHWX  
tSVKH  
tKHSX  
tKHQZ  
tKHQX1  
tGHQZ  
tGLQX  
tGLQV  
tZZE  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock High Pulse Width  
Clock Low Pulse Width  
Clock High to Output Valid  
Clock High to Output Hold  
Address Setup Time  
-
-
-
-
-
-
1.5  
1.6  
2.0  
0.5  
0.4  
0.5  
0.4  
0.5  
0.4  
0.5  
0.4  
0.5  
-
-
0.5  
0.4  
0.6  
0.4  
0.6  
0.4  
0.6  
0.4  
0.6  
-
-
0.5  
0.4  
0.7  
0.4  
0.7  
0.4  
0.7  
0.4  
0.7  
-
-
-
-
-
Address Hold Time  
-
-
-
-
-
-
Write Data Setup Time  
Write Data Hold Time  
-
-
-
SW, SW[a:d] Setup Time  
SW, SW[a:d] Hold Time  
SS Setup Time  
-
-
-
-
-
-
-
-
-
SS Hold Time  
-
-
-
Clock High to Output Hi-Z  
Clock High to Output Low-Z  
G High to Output High-Z  
G Low to Output Low-Z  
G Low to Output Valid  
ZZ High to Power Down(Sleep Time)  
ZZ Low to Recovery(Wake-up Time)  
1.5  
-
1.6  
-
2.0  
-
0.5  
-
0.5  
-
0.5  
-
1.5  
-
1.6  
-
2.0  
-
0.5  
-
0.5  
-
0.5  
-
1.5  
15  
20  
1.6  
15  
20  
2.0  
15  
20  
-
-
-
tZZR  
-
-
-
Rev 1.0  
Dec. 2001  
- 7 -  
K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (SS Controlled, G=Low)  
1
2
3
4
5
6
7
8
K
tKHKH  
tAVKH  
tKHKL  
tKLKH  
tKHAX  
tKHSX  
SAn  
SS  
A1  
A2  
A3  
A4  
A5  
A4  
A6  
A7  
tSVKH  
tKHWX  
tWVKH  
tWVKH  
tWVKH  
tKHWX  
tKHWX  
SW  
SWx  
DQn  
tKHDX  
tKHQZ  
tDVKH tKHDX  
tKHQV  
tKHQX  
tKHQX1  
Q2  
D4  
Q1  
D3  
Q5  
Q4  
NOTE  
1. D3 is the input data written in memory location A3.  
2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the  
last write cycle address.  
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (G Controlled, SS=Low)  
1
2
3
4
5
6
7
8
K
tKHKH  
A3  
SAn  
G
A1  
A2  
A4  
A5  
A4  
A6  
A7  
SW  
SWx  
DQn  
tGHQZ  
tGLQV  
tGLQX  
Q1  
Q2  
D3  
D4  
Q5  
Q4  
NOTE  
1. D3 is the input data written in memory location A3.  
2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last  
write cycle address.  
Rev 1.0  
Dec. 2001  
- 8 -  
K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
TIMING WAVEFORMS OF STANDBY CYCLES  
1
2
3
4
5
6
7
8
K
tKHKH  
SAn  
SS  
A1  
A2  
A1  
A2  
A3  
SW  
SWx  
ZZ  
tZZR  
tZZE  
tKHQV  
tKHQV  
DQn  
Q1  
Q2  
Q1  
Rev 1.0  
Dec. 2001  
- 9 -  
K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG  
The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing  
between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform-  
ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control-  
ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use  
this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM. TCK must  
be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the  
application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left uncon-  
nected.  
JTAG Instruction Coding  
JTAG Block Diagram  
IR2 IR1 IR0 Instruction  
TDO Output  
SAMPLE-Z Boundary Scan Register  
IDCODE Identification Register  
SAMPLE-Z Boundary Scan Register  
Notes  
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
3
4
3
3
3
0
0
0
BYPASS  
SAMPLE  
BYPASS  
BYPASS  
BYPASS  
Bypass Register  
Boundary Scan Register  
Bypass Register  
Bypass Register  
Bypass Register  
1
1
SRAM  
CORE  
1
1
M1  
M2  
NOTE :  
1. Places DQs in Hi-Z in order to sample all input data regardless of  
other SRAM inputs.  
2. TDI is sampled as an input to the first ID register to allow for the serial  
shift of the external TDI data.  
TDI  
BYPASS Reg.  
TDO  
Identification Reg.  
Instruction Reg.  
3. Bypass register is initiated to VSS when BYPASS instruction is  
invoked. The Bypass Register also holds serially loaded TDI when  
exiting the Shift DR states.  
4. SAMPLE instruction dose not places DQs in Hi-Z.  
Control Signals  
TAP Controller  
TMS  
TCK  
TAP Controller State Diagram  
1
0
Test Logic Reset  
0
1
1
1
0
Run Test Idle  
Select DR  
0
Select IR  
0
1
1
1
1
Capture DR  
0
Capture IR  
0
0
Shift DR  
1
Shift IR  
1
Exit1 DR  
0
Exit1 IR  
0
0
0
0
0
Pause DR  
1
Pause IR  
1
Exit2 DR  
1
Exit2 IR  
1
1
0
Update DR  
0
Update IR  
1
Rev 1.0  
Dec. 2001  
- 10  
K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
SCAN REGISTER DEFINITION  
Part  
Instruction Register  
Bypass Register  
1 bits  
ID Register  
32 bits  
Boundary Scan  
70 bits  
512Kx36  
1Mx18  
3 bits  
3 bits  
1 bits  
32 bits  
51 bits  
ID REGISTER DEFINITION  
Revision Number Part Configuration Vendor Definition Samsung JEDEC Code  
Part  
Start Bit(0)  
(31:28)  
(27:18)  
(17:12)  
XXXXXX  
XXXXXX  
(11: 1)  
512Kx36  
1Mx18  
0000  
00111 00100  
01000 00011  
00001001110  
00001001110  
1
1
0000  
BOUNDARY SCAN EXIT ORDER(x36)  
BOUNDARY SCAN EXIT ORDER(x18)  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
3B  
2B  
3A  
3C  
2C  
2A  
2D  
1D  
2E  
1E  
2F  
2G  
1G  
2H  
1H  
3G  
4D  
4E  
4G  
4H  
4M  
3L  
SA  
SA  
SA  
SA  
5B  
6B  
5A  
5C  
6C  
6A  
6D  
7D  
6E  
7E  
6F  
6G  
7G  
6H  
7H  
5G  
4F  
4K  
4L  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
26  
27  
28  
29  
30  
31  
3B  
2B  
3A  
3C  
2C  
2A  
SA  
SA  
SA  
SA  
SA  
SA  
SA  
SA  
5B  
6B  
5A  
5C  
6C  
6A  
6D  
25  
24  
23  
22  
21  
20  
19  
SA  
SA  
SA  
SA  
SA  
SA  
SA  
SA  
SA  
SA  
SA  
SA  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
SWc  
ZQ  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
SWb  
G
DQa  
32  
33  
1D  
2E  
DQb  
DQb  
DQa  
DQa  
7E  
6F  
18  
17  
34  
2G  
DQb  
DQa  
DQa  
7G  
6H  
16  
15  
35  
36  
37  
38  
39  
40  
41  
1H  
3G  
4D  
4E  
4G  
4H  
4M  
DQb  
SWb  
ZQ  
G
K
4F  
4K  
4L  
5L  
7K  
14  
13  
12  
11  
10  
SS  
K
SS  
NC*1  
NC*1  
SW  
K
NC  
K
SWa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
ZZ  
5L  
NC  
SWa  
DQa  
7K  
6K  
7L  
SW  
SWd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
SA  
1K  
2K  
1L  
6L  
42  
43  
2K  
1L  
DQb  
DQb  
DQa  
6L  
9
6M  
7N  
6N  
7P  
6P  
7T  
5T  
6R  
4T  
4P  
2L  
2M  
1N  
2N  
1P  
2P  
3T  
2R  
4N  
44  
45  
2M  
1N  
DQb  
DQb  
DQa  
DQa  
6N  
7P  
8
7
8
7
6
ZZ  
SA  
SA  
7T  
5T  
6R  
6
5
4
SA  
5
46  
47  
48  
49  
50  
51  
2P  
3T  
2R  
4N  
2T  
3R  
DQb  
SA  
SA  
SA  
SA  
M1  
SA  
4
SA  
SA  
3
SA  
SA  
2
SA  
SA  
M2  
4P  
6T  
5R  
3
2
1
70  
3R  
M1  
M2  
5R  
1
NOTE :1. Pins 4G and 4H are no connection pin to internal chip. These pins are forced to VSS.  
Rev 1.0  
Dec. 2001  
- 11  
K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
JTAG DC OPERATING CONDITIONS  
Parameter  
Power Supply Voltage  
Symbol  
Min  
3.15  
1.7  
Typ  
Max  
3.45  
Unit  
V
Note  
VDD  
VIH  
3.3  
Input High Level  
-
-
-
-
VDD+0.3  
0.8  
V
Input Low Level  
VIL  
-0.3  
2.4  
V
Output High Voltage(IOH=-2mA)  
Output Low Voltage(IOL=2mA)  
VOH  
VOL  
VDD  
V
VSS  
0.4  
V
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.  
JTAG AC TEST CONDITIONS  
Parameter  
Input High/Low Level  
Symbol  
VIH/VIL  
TR/TF  
Min  
3.0/0.0  
1.0/1.0  
1.25  
Unit  
V
Note  
Input Rise/Fall Time  
ns  
V
Input and Output Timing Reference Level  
NOTE : 1. See SRAM AC test output load on page 7.  
1
JTAG AC Characteristics  
Parameter  
TCK Cycle Time  
Symbol  
Min  
50  
20  
20  
5
Max  
Unit  
Note  
tCHCH  
tCHCL  
tCLCH  
tMVCH  
tCHMX  
tDVCH  
tCHDX  
tSVCH  
tCHSX  
tCLQV  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TCK High Pulse Width  
TCK Low Pulse Width  
TMS Input Setup Time  
TMS Input Hold Time  
TDI Input Setup Time  
TDI Input Hold Time  
-
-
5
-
5
-
5
-
SRAM Input Setup Time  
SRAM Input Hold Time  
Clock Low to Output Valid  
5
-
5
-
0
10  
JTAG TIMING DIAGRAM  
TCK  
tCHCH  
tCHCL  
tCLCH  
tMVCH  
tCHMX  
tCHDX  
TMS  
TDI  
tDVCH  
tSVCH  
tCHSX  
PI  
(SRAM)  
tCLQV  
TDO  
Rev 1.0  
Dec. 2001  
- 12  
K7P163611M  
K7P161811M  
512Kx36 & 1Mx18 SRAM  
119 BGA PACKAGE DIMENSIONS  
119-FCBGA-1422  
Units:millimeters/Inches  
Æ
0.300 MAX M  
1.27x6=7.620  
R1.250  
5.750  
CHIP BACK SIDE  
#A1 INDEX  
7
6 5 4 3 2 1  
CHIP AREA  
1.270  
153-Æ0.750±0.150  
14.000  
0.200 MAX  
BOTTOM VIEW  
TOP VIEW  
UNDERFILL  
119 BGA PACKAGE THERMAL CHARACTERISTICS  
Parameter  
Junction to Ambient(at still air)  
Junction to Case  
Symbol  
Theta_JA  
Theta_JC  
Theta_JB  
Thermal Resistance  
Unit  
°C/W  
°C/W  
°C/W  
Note  
22.8  
0.6  
1W Heating  
Junction to Board  
4.2  
2W Heating  
NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x Theta_JA.  
Rev 1.0  
Dec. 2001  
- 13  

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