K7P321866M-HC25T [SAMSUNG]
SRAM;
| 型号： | K7P321866M-HC25T |
| 厂家： | 
SAMSUNG |
| 描述： | SRAM 静态存储器 |
| 文件： | 总14页 (文件大小：446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
32Mb M-die LW SRAM Specification
119BGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Dec. 2005
Rev 1.2
- 1 -
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
Document Title
1Mx36 & 2Mx18 Synchronous Pipelined SRAM
Revision History
Draft Date
Remark
Rev. No.
History
Jan. 2002
Advance
Rev. 0.0
- Initial Document
Jan. 2002
Advance
Rev. 0.1
- x18 Organization Package Pin Configuration corrected(2T,4T, 6T)
JTAG Instruction Coding 101 changed from Bypass to Private
Feb. 2003
Advance
Rev. 0.2
- Absolute maximum ratings are changed
VDD : 2.815 - > 3.13
- Recommended DC operating conditions are changed
VREF / VCM-CLK : 0.68 - > 0.6, 0.95 - > 0.9
Max VDIF-CLK : VDDQ+0.3 -> VDDQ+0.6
- DC characteristics is changed
ISBZZ : 150 - > 128
- AC Characteristics are changed
TAVKH / TDVKH / TWVKH / TSVKH : 0.4 / 0.5 / 0.5 - > 0.3 / 0.3 / 0.3
TKHAX / TKHDX / TKHWX / TKHSX : 0.5 / 0.5 / 0.5 - > 0.5 / 0.5 / 0.5
Feb. 2003
Mar. 2003
May 2003
Sep. 2003
Sep. 2004
Advance
Advance
Advance
Advance
Final
Rev. 0.3
Rev. 0.4
Rev. 0.5
Rev. 0.6
Rev. 1.0
- PACKAGE PIN CONFIGURATION are changed
Numbering each SA pins.
- AC Characteristics are changed
TKHQV (-33) : 0.5 - > 0.6
- PIN CAPACITANCE is changed
Add Clock Pin capacitance
- Correct typo
VDD -> VDDQ: in MODE CONTROL at page4
- Fill the themal Data
- Remove 333MHz Bin
Oct. 2005
Dec. 2005
Final
Final
Rev. 1.1
Rev. 1.2
- Add Pb free.
- Modify package dimensions
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
Dec. 2005
Rev 1.2
- 2 -
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
1Mx36 & 2Mx18 Synchronous Pipelined SRAM
FEATURES
• 1Mx36 or 2Mx18 Organizations.
Maximum Access
Part Number
• 2.5V Core/1.5V Output Power Supply (1.9V max VDDQ).
• HSTL Input and Output Levels.
Org.
Frequency
Time
• Differential, HSTL Clock Inputs K, K.
K7P323666M-H(G)C30
K7P323666M-H(G)C25
K7P321866M-H(G)C30
K7P321866M-H(G)C25
300MHz
250MHz
300MHz
250MHz
1.6
2.0
1.6
2.0
1Mx36
2Mx18
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
* G : Lead free package
• Programmable Impedance Output Drivers.
• JTAG 1149.1 Compatible Test Access port.
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm).
FUNCTIONAL BLOCK DIAGRAM
SA[0:19] or SA[0:20]
Read
1
0
1Mx36
Address
or
Register
Write
2Mx18
Array
CK
Address
Register
SS
Latch
Latch
SW
SW
Column Decoder
Write/Read Circuit
Register
SW
Register
SWx
SWx
0
1
Register
Register
SWx
(x=a, b, c, d)
or (x=a, b)
Data In
Register
SS
SS
Register
Register
Data Out
Register
G
ZZ
DQx[1:9]
K
K
CK
(x=a, b, c, d)
or (x=a, b)
PIN DESCRIPTION
Pin Name
Pin Description
Pin Name
Pin Description
K, K
SAn
DQn
SW
Differential Clocks
VREF
M1, M2
G
HSTL Input Reference Voltage
Synchronous Address Input
Bi-directional Data Bus
Read Protocol Mode Pins ( M1=VSS, M2=VDDQ )
Asynchronous Output Enable
Synchronous Select
Synchronous Global Write Enable
Synchronous Byte a Write Enable
Synchronous Byte b Write Enable
Synchronous Byte c Write Enable
Synchronous Byte d Write Enable
Asynchronous Power Down
Core Power Supply
SS
SWa
SWb
SWc
SWd
ZZ
TCK
TMS
TDI
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
TDO
ZQ
JTAG Test Data Output
Output Driver Impedance Control
GND
VDD
VSS
NC
VDDQ
Output Power Supply
No Connection
Dec. 2005
Rev 1.2
- 3 -
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7P323666M(1Mx36)
1
2
3
4
5
6
7
A
B
C
D
E
F
VDDQ
NC
SA13
SA18
SA12
DQc9
DQc7
DQc5
DQc4
DQc2
VDD
SA10
SA9
SA11
VSS
VSS
VSS
SWc
VSS
VREF
VSS
SWd
VSS
VSS
VSS
M1
NC
SA19
VDD
ZQ
SS
SA7
SA8
SA6
VSS
VSS
VSS
SWb
VSS
VREF
VSS
SWa
VSS
VSS
VSS
M2
SA4
VDDQ
NC
SA17
SA5
NC
NC
DQc8
DQc6
VDDQ
DQc3
DQc1
VDDQ
DQd1
DQd3
VDDQ
DQd6
DQd8
NC
DQb9
DQb7
DQb5
DQb4
DQb2
VDD
DQb8
DQb6
VDDQ
DQb3
DQb1
VDDQ
DQa1
DQa3
VDDQ
DQa6
DQa8
NC
G
G
H
J
NC
NC
VDD
K
K
L
DQd2
DQd4
DQd5
DQd7
DQd9
SA15
NC
DQa2
DQa4
DQa5
DQa7
DQa9
SA2
K
M
N
P
R
T
SW
SA0
SA1
VDD
SA16
TCK
NC
SA14
TDI
SA3
TDO
NC
ZZ
U
VDDQ
TMS
NC
VDDQ
K7P321866M(2Mx18)
1
2
3
4
NC
SA20
VDD
ZQ
SS
5
6
7
A
B
C
D
E
F
VDDQ
NC
SA13
SA19
SA12
NC
SA10
SA9
SA11
VSS
VSS
VSS
SWb
VSS
VREF
VSS
NC
SA7
SA8
SA6
VSS
VSS
VSS
NC
SA4
SA17
SA5
DQa9
NC
VDDQ
NC
NC
NC
DQb1
NC
NC
DQb2
NC
DQa8
VDDQ
DQa6
NC
VDDQ
NC
G
DQa7
NC
G
H
J
DQb3
NC
NC
NC
VDD
K
DQb4
VDDQ
NC
VSS
VREF
VSS
SWa
VSS
VSS
VSS
M2
DQa5
VDD
NC
VDD
VDDQ
DQa4
NC
K
L
DQb5
NC
DQb6
VDDQ
DQb8
NC
K
DQa3
NC
M
N
P
R
T
DQb7
NC
VSS
VSS
VSS
M1
SW
SA0
SA1
VDD
NC
TCK
VDDQ
NC
DQa2
NC
DQb9
SA15
SA18
TMS
DQa1
NC
NC
SA2
SA16
NC
NC
SA14
TDI
SA3
TDO
ZZ
U
VDDQ
VDDQ
Dec. 2005
Rev 1.2
- 4 -
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
FUNCTION DESCRIPTION
The K7P323666M and K7P321866M are 37,748,736 bit Synchronous Pipeline Mode SRAM. It is organized as 1,048,576 words of
36 bits(or 2,097,152 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology.
Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the
rising edge of K clock, All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are
updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one
cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.
Read Operation
During reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the second
edge, and data is captured in the output register and driven to the CPU during the second clock edge. SS is driven low during this
cycle, signaling that the SRAM should drive out the data.
During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-
ple SRAM cycles to perform a single read operation.
Write(Store) Operation
All addresses and SW are sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock,
one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the
Address, SW and SW[a:d] are valid to signal that a valid operation is on the Address and Control Input.
Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write
cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of
read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is the
same as the SW signal.
Bypass Read Operation
Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be
done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is
the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored
write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the
SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have
new byte data from the write data buffer and the other bytes from the SRAM array.
Programmable Impedance Output Buffer Operation
This HSTL Late Write SRAM has been designed with programmable impedance output buffers. The SRAMs output buffer impedance
can be adjusted to match the system data bus impedance, by connecting a external resistor (RQ) between the ZQ pin of the SRAM
and VSS. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. For example, a 250Ω
resistor will give an output buffer impedance of 50Ω. The allowable range of RQ is from 175Ω to 350Ω. Internal circuits evaluate and
periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. One evalu-
ation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the
optimum level. Impedance updates occur when the SRAM is in High-Z state, and thus are triggered by write and deselect operations.
Updates will also be triggered with G HIGH initiated High-Z state, providing the specified G setup and hold times are met. Impedance
match is not instantaneous upon power-up. In order to guarantee optimum output driver impedance, the SRAM requires a minimum
number of non-read cycles (1,024) after power-up. The output buffers can also be programmed in a minimum impedance configura-
tion by connecting ZQ to VSS or VDDQ.
Mode Control
There are two mode control select pins (M1 and M2) used to set the proper read protocol. This SRAM supports single clock pipelined
operating mode. For proper specified device operation, M1 must be connected to VSS and M2 must be connected to VDDQ. These
mode pins must be set at power-up and must not change during device operation.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
Sleep Mode
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored
and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep
mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all
pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated.
Normal operations can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.
Dec. 2005
Rev 1.2
- 5 -
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
TRUTH TABLE
K
X
X
↑
↑
↑
↑
↑
↑
↑
↑
ZZ
H
L
G
X
H
L
SS
X
X
H
L
SW SWa SWb SWc SWd DQa DQb DQc DQd
Operation
Hi-Z Hi-Z Hi-Z Hi-Z Power Down Mode. No Operation
Hi-Z Hi-Z Hi-Z Hi-Z Output Disabled.
X
X
X
H
L
L
L
L
L
L
X
X
X
X
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
H
L
X
X
X
X
H
H
H
H
L
L
Hi-Z Hi-Z Hi-Z Hi-Z Output Disabled. No Operation
DOUT DOUT DOUT DOUT Read Cycle
L
L
L
X
X
X
X
X
X
L
Hi-Z Hi-Z Hi-Z Hi-Z No Bytes Written
L
L
DIN
Hi-Z Hi-Z Hi-Z Write first byte
Hi-Z Hi-Z Write second byte
L
L
H
H
H
L
Hi-Z
DIN
L
L
H
H
L
Hi-Z Hi-Z
DIN
Hi-Z Write third byte
DIN Write fourth byte
DIN Write all bytes
L
L
H
L
Hi-Z Hi-Z Hi-Z
L
L
L
DIN
DIN
DIN
NOTE : K & K are complementary
ABSOLUTE MAXIMUM RATINGS
Parameter
Core Supply Voltage Relative to VSS
Output Supply Voltage Relative to VSS
Voltage on any I/O pin Relative to VSS
Output Short-Circuit Current
Symbol
Value
-0.5 to 3.13
-0.5 to 2.4
Unit
V
VDD
VDDQ
VIN
V
-0.5 to VDDQ+0.5 (2.4V MAX)
25
V
IOUT
TOPR
TSTG
mA
°C
°C
Operating Temperature
0 to 70
Storage Temperature
-55 to 125
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level
Symbol
VDD
Min
2.37
1.4
Typ
2.5
1.5
-
Max
2.63
Unit
V
Note
VDDQ
1.9
V
VIH
VREF+0.1
-0.3
VDDQ+0.3
VREF-0.1
0.9
V
1, 2
1, 3
Input Low Level
VIL
-
V
Input Reference Voltage
Clock Input Signal Voltage
Clock Input Differential Voltage
Clock Input Common Mode Voltage
VREF
0.6
0.75
-
V
VIN-CLK
VDIF-CLK
VCM-CLK
-0.3
VDDQ+0.3
VDDQ+0.6
0.9
V
1, 4
1, 5
1, 6
0.1
-
V
0.6
0.75
V
NOTE : 1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring timing
parameters.
2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).
3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).
4. VIN-CLK specifies the maximum allowable DC level for the differential clock. i.e VIL-CLK and VIH-CLK.
5. VDIF-CLK specifies the minimum Clock differential voltage required for switching. i.e DC voltage difference between VIL-CLK and VIH-CLK.
6. VCM-CLK specifies the Clock crossing point for the differential clock or the allowable common clock level for a single ended clock.
Dec. 2005
Rev 1.2
- 6 -
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
PIN CAPACITANCE
Parameter
Symbol
CIN
Test Condition
VIN=0V
Min
Max
Unit
pF
Input Capacitance
-
-
-
4
5
5
Data Output Capacitance
Clock Capacitance
COUT
CCLK
VOUT=0V
pF
VCLK=0V
pF
NOTE : Periodically sampled and not 100% tested.(TA=25°C, f=1MHz)
DC CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Note
Average Power Supply Operating Current-x36
(VIN=VIH or VIL, ZZ & SS=VIL)
IDD30
IDD25
620
550
-
mA
1, 2
Average Power Supply Operating Current-x18
(VIN=VIH or VIL, ZZ & SS=VIL)
IDD30
IDD25
570
500
-
-
mA
mA
mA
µA
1, 2
1
Power Supply Standby Current
(VIN=VIH or VIL, ZZ=VIH)
ISBZZ
ISBSS
ILI
128
200
1
Active Standby Power Supply Current
(VIN=VIH or VIL, SS=VIH, ZZ=VIL)
-
1
Input Leakage Current
(VIN=VSS or VDDQ)
-1
-1
Output Leakage Current
(VOUT=VSS or VDDQ, DQ in High-Z)
ILO
1
µA
Output High Voltage(Programmable Impedance Mode)
Output Low Voltage(Programmable Impedance Mode)
Output High Voltage(IOH=-0.1mA)
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VDDQ/2
VSS
VDDQ
VDDQ/2
VDDQ
0.2
V
V
V
V
V
V
3,5
4,5
6
VDDQ-0.2
VSS
Output Low Voltage(IOL=0.1MA)
6
Output High Voltage(IOH=-6mA)
VDDQ-0.4
VSS
VDDQ
0.4
6
Output Low Voltage(IOL=6mA)
6
NOTE :1. Minimum cycle. IOUT=0mA.
2. 50% read cycles.
3. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω.
4. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω.
5. Programmable Impedance Output Buffer Mode. The ZQ pin is connected to VSS through RQ.
6. Minimum Impedance Output Buffer Mode. The ZQ pin is connected to VSS or VDD.
Dec. 2005
Rev 1.2
- 7 -
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
AC TEST CONDITIONS (TA=0 to 70°C, VDD=2.37 -2.63V, VDDQ=1.5V)
Parameter
Symbol
Value
2.37~2.63
1.5
Unit
V
Core Power Supply Voltage
VDD
Output Power Supply Voltage
Input High/Low Level
VDDQ
VIH/VIL
VREF
V
1.25/0.25
0.75
V
Input Reference Level
V
Input Rise/Fall Time
TR/TF
0.5/0.5
0.75
ns
V
Input and Out Timing Reference Level
Clock Input Timing Reference Level
NOTE : Parameters are tested with RQ=250Ω and VDDQ=1.5V.
Cross Point
V
AC TEST OUTPUT LOAD
50Ω
VDDQ/2
VDDQ/2
50Ω
50Ω
5pF
VDDQ/2
25Ω
DQ
50Ω
5pF
AC CHARACTERISTICS
-30
-25
Parameter
Symbol
Unit
Note
Min
Max
-
-
-
1.6
-
-
-
-
-
-
-
-
Min
4.0
1.6
1.6
-
0.5
0.3
0.5
0.3
0.5
0.3
0.5
0.3
0.5
-
Max
Clock Cycle Time
tKHKH
tKHKL
tKLKH
tKHQV
tKHQX
tAVKH
tKHAX
tDVKH
tKHDX
tWVKH
tKHWX
tSVKH
tKHSX
tKHQZ
tKHQX1
tGHQZ
tGLQX
tGLQV
tZZE
3.3
1.3
1.3
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock High Pulse Width
Clock Low Pulse Width
Clock High to Output Valid
Clock High to Output Hold
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
2.0
-
-
-
-
-
-
-
-
0.5
0.3
0.5
0.3
0.5
0.3
0.5
0.3
0.5
-
0.5
-
0.5
-
-
-
SW, SW[a:d] Setup Time
SW, SW[a:d] Hold Time
SS Setup Time
SS Hold Time
-
-
Clock High to Output Hi-Z
Clock High to Output Low-Z
G High to Output High-Z
G Low to Output Low-Z
G Low to Output Valid
ZZ High to Power Down(Sleep Time)
ZZ Low to Recovery(Wake-up Time)
1.6
-
1.6
-
1.6
15
20
2.0
-
2.0
-
2.0
15
20
0.5
-
0.5
-
-
-
tZZR
Dec. 2005
Rev 1.2
- 8 -
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (SS Controlled, G=Low)
1
2
3
4
5
6
7
8
K
tKHKH
tAVKH
tKHKL
tKLKH
tKHAX
tKHSX
SAn
SS
A1
A2
A3
A4
A5
A4
A6
A7
tSVKH
tWVKH
tKHWX
tWVKH
tWVKH
tKHWX
tKHWX
SW
SWx
DQn
tKHDX
tKHQZ
tDVKH tKHDX
tKHQV
tKHQX
tKHQX1
Q2
D4
Q1
D3
Q5
Q4
NOTE
1. D3 is the input data written in memory location A3.
2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the
last write cycle address.
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (G Controlled, SS=Low)
1
2
3
4
5
6
7
8
K
tKHKH
A3
SAn
G
A1
A2
A4
A5
A4
A6
A7
SW
SWx
DQn
tGHQZ
tGLQV
tGLQX
Q1
Q2
D3
D4
Q5
Q4
NOTE
1. D3 is the input data written in memory location A3.
2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last
write cycle address.
Dec. 2005
Rev 1.2
- 9 -
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
TIMING WAVEFORMS OF STANDBY CYCLES
1
2
3
4
5
6
7
8
K
tKHKH
SAn
SS
A1
A2
A1
A2
A3
SW
SWx
ZZ
tZZE
tZZR
tKHQV
tKHQV
DQn
Q1
Q2
Q1
Dec. 2005
Rev 1.2
- 10
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Teat Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
JTAG Instruction Coding
JTAG Block Diagram
IR2 IR1 IR0 Instruction
TDO Output
SAMPLE-Z Boundary Scan Register
IDCODE Identification Register
SAMPLE-Z Boundary Scan Register
Notes
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
3
4
5
3
3
0
0
0
BYPASS
SAMPLE
PRIVATE
BYPASS
BYPASS
Bypass Register
1
Boundary Scan Register
1
SRAM
1
Bypass Register
Bypass Register
CORE
1
M1
M2
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of
other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
3. Bypass register is initiated to VSS when BYPASS instruction is
invoked. The Bypass Register also holds serially loaded TDI when
exiting the Shift DR states.
TDI
BYPASS Reg.
Identification Reg.
Instruction Reg.
TDO
4. SAMPLE instruction dose not places DQs in Hi-Z.
Control Signals
TAP Controller
5. PRIVATE is reserved for the exclusive use of SAMSUNG. This
TMS
TCK
instruction should not be used.
TAP Controller State Diagram
1
0
Test Logic Reset
0
1
1
0
1
Run Test Idle
Select DR
0
Capture DR
0
Shift DR
1
Exit1 DR
0
Select IR
0
Capture IR
0
1
1
1
1
0
Shift IR
1
Exit1 IR
0
0
0
0
0
Pause DR
1
Exit2 DR
1
Update DR
0
Pause IR
1
Exit2 IR
1
Update IR
1
1
0
Dec. 2005
Rev 1.2
- 11
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
1 bits
ID Register
32 bits
32 bits
Boundary Scan
70 bits
1Mx36
2Mx18
3 bits
3 bits
1 bits
51 bits
ID REGISTER DEFINITION
Revision Number Part Configuration Vendor Definition Samsung JEDEC Code
Part
Start Bit(0)
(31:28)
0000
(27:18)
(17:12)
XXXXXX
XXXXXX
(11: 1)
1Mx36
2Mx18
01000 00100
00001001110
1
1
0000
01001 00011
00001001110
BOUNDARY SCAN EXIT ORDER(x36)
BOUNDARY SCAN EXIT ORDER(x18)
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
3B
2B
3A
3C
2C
2A
2D
1D
2E
1E
2F
2G
1G
2H
1H
3G
4D
4E
4B
4H
4M
3L
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
5B
6B
5A
5C
6C
6A
6D
7D
6E
7E
6F
6G
7G
6H
7H
5G
4F
4K
4L
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
26
27
28
29
30
31
3B
2B
3A
3C
2C
2A
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
5B
6B
5A
5C
6C
6A
6D
25
24
23
22
21
20
19
SA
SA
SA
DQa9
DQc9
DQc8
DQc7
DQc6
DQc5
DQc4
DQc3
DQc2
DQc1
SWc
ZQ
DQb9
DQb8
DQb7
DQb6
DQb5
DQb4
DQb3
DQb2
DQb1
SWb
G
32
33
1D
2E
DQb1
DQb2
DQa8
DQa7
7E
6F
18
17
34
2G
DQb3
DQa6
DQa5
7G
6H
16
15
35
36
37
38
39
40
41
1H
3G
4D
4E
4B
4H
4M
DQb4
SWb
ZQ
G
K
K
SWa
DQa4
4F
4K
4L
5L
7K
14
13
12
11
10
SS
SA
NC*1
SW
K
K
SS
SA
NC*
1
SWa
DQa1
DQa2
DQa3
DQa4
DQa5
DQa6
DQa7
DQa8
DQa9
ZZ
5L
7K
6K
7L
SW
SWd
DQd1
DQd2
DQd3
DQd4
DQd5
DQd6
DQd7
DQd8
DQd9
SA
1K
2K
1L
6L
42
43
2K
1L
DQb5
DQb6
DQa3
6L
9
6M
7N
6N
7P
6P
7T
5T
6R
4T
4P
2L
2M
1N
2N
1P
2P
3T
2R
4N
44
45
2M
1N
DQb7
DQb8
DQa2
DQa1
6N
7P
8
7
8
7
6
5
4
3
2
ZZ
SA
SA
7T
5T
6R
6
5
4
SA
SA
SA
SA
46
47
48
49
50
51
2P
3T
2R
4N
2T
3R
DQb9
SA
SA
SA
SA
SA
SA
SA
SA
M2
4P
6T
5R
3
2
1
70
3R
M1
M2
5R
1
M1
NOTE :1. Pin 4H is no connection pin to internal chip and the scanned data is "0".
Dec. 2005
Rev 1.2
- 12
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Symbol
Min
2.37
1.7
Typ
Max
2.63
Unit
V
Note
Power Supply Voltage
VDD
VIH
2.5
Input High Level
-
-
-
-
VDD+0.3
0.8
V
Input Low Level
VIL
-0.3
2.1
V
Output High Voltage(IOH=-2mA)
Output Low Voltage(IOL=2mA)
VOH
VOL
VDD
V
VSS
0.2
V
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Symbol
VIH/VIL
TR/TF
Min
2.5/0.0
1.0/1.0
1.25
Unit
V
Note
Input High/Low Level
Input Rise/Fall Time
ns
V
Input and Output Timing Reference Level
NOTE : 1. See SRAM AC test output load on page 7.
1
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
Note
TCK Cycle Time
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
-
-
5
-
5
-
5
-
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
5
-
5
-
0
10
JTAG TIMING DIAGRAM
TCK
tCHCH
tCLCH
tCHCL
tMVCH
tCHMX
tCHDX
TMS
TDI
tDVCH
tSVCH
tCHSX
PI
(SRAM)
tCLQV
TDO
Dec. 2005
Rev 1.2
- 13
K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
119 BGA PACKAGE DIMENSIONS
# A1 INDEX MARK
1.27 x 6 = 7.62
0.30 MAX
14.00 ± 0.10
7
6
5
4
3
2
1
A
B
C
D
E
F
2.00
1.00 Dp 0.10 ± 0.05
G
H
J
K
L
M
N
P
R
T
2.00
U
4x C0.70
4x C1.00
2.00 Dp 0.10 ± 0.05
119x 0.750±0.15
1.27
12.50 ± 0.10
NOTE :
1.All Dimensions are in Millimeters.
2. Cavity Surface : Mat finish (Rz 10~15um)
Pin Surface : polish (Rz 2um Max)
3. Solder Ball to PCB Offset : 0.10 MAX.
4. PCB to Cavity Offset : 0.10 MAX.
5. PKG Warpage : 0.05 MAX
119 BGA PACKAGE THERMAL CHARACTERISTICS
Parameter
Junction to Ambient (at still air)
Junction to Case
Symbol
Theta_JA
Theta_JC
Theta_JB
Thermal Resistance
Unit
°C/W
°C/W
°C/W
Note
20.0
4.3
1.5W Heating
Junction to Board
5.4
1.5W Heating
NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x Theta_JA.
Dec. 2005
Rev 1.2
- 14
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明