K9F1608W0B-TCB0 [SAMSUNG]

Flash, 2MX8, 45ns, PDSO40, 0.400 INCH, 0.8 MM PITCH, PLASTIC, TSOP2-44/40;


型号：	K9F1608W0B-TCB0
厂家：	SAMSUNG
描述：	Flash, 2MX8, 45ns, PDSO40, 0.400 INCH, 0.8 MM PITCH, PLASTIC, TSOP2-44/40 光电二极管内存集成电路
文件：	总25页 (文件大小：321K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

Document Title

2M x 8 Bit NAND Flash Memory

Revision History

Revision No. History

Draft Date

Remark

0.0

0.1

0.2

Initial issue.

April 10th 1999

Preliminary

1. Revised real-time map-out algorithm(refer to technical notes)

July 23th 1999

Sep. 15th 1999

Preliminary

1. Changed device name

- KM29W16000BT -> K9F1608W0B-TCB0

- KM29W16000BIT -> K9F1608W0B-TIB0

0.3

1. Changed invalid block(s) marking method prior to shipping

- The invalid block(s) information is written the 1st or 2nd page of the

invalid block(s) with 00h data

July 17th 2000

Finally

--->The invalid block(s) status is defined by the 6th byte in the spare

area. Samsung makes sure that either the 1st or 2nd page of every

invalid block has non-FFh data at the column address of 261.

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.

http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

2M x 8 Bit NAND Flash Memory

FEATURES

GENERAL DESCRIPTION

· Voltage Supply : 2.7V ~ 5.5V

· Organization

- Memory Cell Array : (2M + 64K)bit x 8bit

The K9F1608W0B is a 2M(2,097,152)x8bit NAND Flash Mem-

ory with a spare 64K(65,536)x8bit. Its NAND cell provides the

most cost-effective solution for the solid state mass storage

market. A program operation programs the 264-byte page in

typically 250ms and an erase operation can be performed in typ-

ically 2ms on a 4K-byte block.

- Data Register

: (256 + 8)bit x8bit

· Automatic Program and Erase

- Page Program : (256 + 8)Byte

- Block Erase : (4K + 128)Byte

- Status Register

Data in the page can be read out at 80ns cycle time per byte.

The I/O pins serve as the ports for address and data input/out-

put as well as command inputs. The on-chip write controller

automates all program and erase system functions, including

pulse repetition, where required, and internal verify and margin-

ing of data. Even the write-intensive systems can take advan-

tage of the K9F1608W0B extended reliability of 1,000,000

program/erase cycles by providing ECC(Error Correction Code)

with real time mapping-out algorithm.

The K9F1608W0B is an optimum solution for large nonvolatile

storage application such as solid state storage, digital voice

recorder, digital still camera and other portable applications

requiring nonvolatility.

· 264-Byte Page Read Operation

- Random Access

: 10ms(Max.)

- Serial Page Access : 80ns(Min.)

· Fast Write Cycle Time

- Program Time

: 250ms(typ.)

- Block Erase Time : 2ms (typ.)

· Command/Address/Data Multiplexed I/O port

· Hardware Data Protection

- Program/Erase Lockout During Power Transitions

· Reliable CMOS Floating-Gate Technology

- Endurance : 1Million Program/Erase Cycles

- Data Retention : 10 years

· Command Register Operation

· 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)

- Forward Type

PIN CONFIGURATION

PIN DESCRIPTION

Pin Name

I/O0 ~ I/O7

CLE

Pin Function

Data Inputs/Outputs

VSS

CLE

ALE

VCC

R/B

GND

N.C

Command Latch Enable

Address Latch Enable

Chip Enable

N.C

ALE

Read Enable

Write Enable

N.C

I/O0

I/O1

I/O2

I/O3

VSS

N.C

I/O7

I/O6

I/O5

I/O4

VCCQ

Write Protect

GND

R/B

Ground Input

Ready/Busy output

Power(2.7V~5.5V)

Output Butter Power(2.7V~5.5V)

Ground

VCC

VCCQ

VSS

44(40) TSOP (II)

STANDARD TYPE

N.C

No Connection

NOTE : Connect all VCC,VccQ and VSS pins of each device to power supply outputs.

Do not leave VCC or VSS disconnected.

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

Figure 1. FUNCTIONAL BLOCK DIAGRAM

X-Buffers

A8 - A20

Latches

16M + 512K Bit

NAND Flash

ARRAY

& Decoders

Y-Buffers

A0 - A7

Latches

(256 + 8)Bytes x 8192

& Decoders

Page Register & S/A

Y-Gating

Command

I/O Buffers & Latches

Command

VccQ

Vss

Control Logic

& High Voltage

Generator

I/0 0

I/0 7

Global Buffers

CLE ALE WP

Figure 2. ARRAY ORGANIZATION

1 Block =16 Pages

= (4K + 128)Byte

1 Page = 264 Bytse

1 Block = 264 Bytes x 16 Pages

= (4K + 128) Bytes

1 Device = 264Bytes x 16Pages x 512 Blocks

= 16.5 Mbits

16M : 8K Pages

(= 512 Blocks)

8 bit

256Bytes

8Bytes

I/O 0 ~ I/O 7

Page Register

256Bytes

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

1st Cycle

2nd Cycle

3rd Cycle

Column Address

Row Address

(Page Address)

A10

A18

A11

A19

A12

A20

A13

A14

A15

A16

A17

NOTE : A12 to A20 : Block Address

* : X can be VIL or VIH.

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

PRODUCT INTRODUCTION

The K9F1608W0B is a 16.5Mbit(17,301,504 bit) memory organized as 8192 rows(pages) by 264 columns. Spare eight columns are

located from column address of 256 to 263. A 264-byte data register is connected to memory cell arrays accommodating data trans-

fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells

that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16

pages formed by one NAND structures, totaling 2,112 NAND structures of 16 cells. The array organization is shown in Figure 2. The

program and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array

consists of 512 separately or grouped erasable 4K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the

K9F1608W0B.

The K9F1608W0B has addresses multiplexed into 8 I/O¢s. This scheme dramatically reduces pin counts and allows systems

upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through

I/O`s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address

Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle

except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block

address loading. The 2M byte physical space requires 21 addresses, thereby requiring three cycles for byte-level addressing : col-

umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address

cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.

Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of

the K9F1608W0B.

Table 1. COMMAND SETS

Function

1st. Cycle

00h

2nd. Cycle

Acceptable Command during Busy

50h

Read ID

90h

Reset

FFh

Page Program

Block Erase

Read Status

80h

10h

D0h

60h

70h

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

PIN DESCRIPTION

Command Latch Enable(CLE)

The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched

into the command register through the I/O ports on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of

WE with ALE high.

Chip Enable(CE)

The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.

However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to

standby mode.

Write Enable(WE)

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

Read Enable(RE)

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge

of RE which also increments the internal column address counter by one.

I/O Port : I/O 0 ~ I/O 7

The I/O pins are used to input command, address and data, and to outputs data during read operations. The I/O pins float to high-z

when the chip is deselected or the outputs are disabled.

Write Protect (WP)

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when

the WP pin is active low.

Ready/Busy(R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is

in process and return to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is

deselected or outputs are disabled.

Power Line(VCC & VCCQ)

The VCCQ is the power supply for I/O interface logic. It is electrically isolated from main power line(VCC=2.7~5.5V) for supporting 5V

tolerant I/O with 5V power supply at VCCQ.

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

Voltage on any pin relative to VSS

VIN

-0.6 to +7.0

-10 to +125

-40 to +125

-65 to +150

K9F1608W0B-TCB0

K9F1608W0B-TIB0

Temperature Under Bias

TBIAS

TSTG

°C

Storage Temperature

NOTE :

1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.

Maximum DC voltage on input/output pins is VCCQ+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND,K9F1608W0B-TCB0:TA=0 to 70°C, K9F1608W0B-TIB0:TA=-40 to 85°C)

Parameter

Supply Voltage

Symbol

Min

2.7

Typ.

Max

5.5

Unit

VCC

VCCQ¹⁾

VSS

Supply Voltage

NOTE : 1. Vcc and VccQ pins are separater each other.

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Vcc=2.7V ~ 3.6V

Vcc=3.6V ~ 5.5V

Parameter

Symbol

Test Conditions

Unit

Min

Max

Min

Max

Typ

tRC=80ns, CE=VIL,

IOUT=0mA

Sequential Read

ICC1

Operating

Current

Program

Erase

ICC2

ICC3

ISB1

ISB2

ILI

Stand-by Current(TTL)

Stand-by Current(CMOS)

Input Leakage Current

Output Leakage Current

CE=VIH, WP=0V/VCC

CE=VCC-0.2, WP=0V/VCC

VIN=0 to 5.5V

VOUT=0 to 5.5V

I/O Pins

±10

ILO

±10

2.0

-0.3

2.4

VCCQ+0.3 3.0

VCCQ+0.5

Input High Voltage

VIH

Except I/O Pins

VCC+0.3

3.0

-0.3

2.4

VCC+0.5

Input Low Voltage, All inputs

Output High Voltage Level

Output Low Voltage Level

Output Low Current(R/B)

VIL

VOH

VOL

0.6

0.8

IOH=-400mA

IOL=2.1mA

0.4

IOL(R/B) VOL=0.4V

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

VALID BLOCK

Parameter

Symbol

Min

Typ.

Max

Unit

Valid Block Number

NVB

502

508

512

Blocks

NOTE :

1. The K9F1608W0B may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid

blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try

to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block

AC TEST CONDITION

(K9F1608W0B-TCB0:TA=0 to 70°C, K9F1608W0B-TIB0:TA=-40 to 85°C, VCC=2.7V ~ 5.5V unless otherwise noted)

Value

Parameter

Vcc=2.7V ~ 3.6V

Vcc=3.6V ~ 5.5V

Input Pulse Levels

0.4V to 2.4V

0.4V to 3.4V

Input Rise and Fall Times

Input and Output Timing Levels

5ns

0.8V and 2.0V

1 TTL GATE and

Output Load

1 TTL GATE and CL = 100pF

CL=50pF(3.0V+/-10%),100pF(3.0V~3.6V)

CAPACITANCE(TA=25°C, Vcc=5.0V f=1.0MHz)

Item

Symbol

Test Condition

Min

Max

Unit

Input/Output Capacitance

Input Capacitance

CI/O

VIL=0V

CIN

VIN=0V

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE

ALE

Mode

Command Input

Read Mode

Write Mode

Address Input(3clock)

Command Input

Address Input(3clock)

Data Input

Sequential Read & Data Output

During Read(Busy)

During Program(Busy)

During Erase(Busy)

Write Protect

X⁽¹⁾

(2)

Stand-by

0V/VCC

NOTE : 1. X can be VIL or VIH

2. WP should be biased to CMOS high or CMOS low for standby.

Program/Erase Characteristics

Parameter

Symbol

Min

Typ

0.25

Max

1.5

Unit

Program Time

tPROG

Nop

Number of Partial Program Cycles in the Same Page

Block Erase Time

cycles

tBERS

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

AC Timing Characteristics for Command / Address / Data Input

Parameter

Symbol

tCLS

tCLH

tCS

Min

Max

Unit

CLE Set-up Time

CLE Hold Time

CE Setup Time

CE Hold Time

tCH

WE Pulse Width

ALE Setup Time

ALE Hold Time

Data Setup Time

Data Hold Time

Write Cycle Time

tWP

tALS

tALH

tDS

tDH

tWC

tWH

WE High Hold Time

AC Characteristics for Operation

Parameter

Data Transfer from Cell to Register

ALE to RE Delay

Symbol

Min

Max

Unit

150

200

tAR

ALE to RE Delay(read ID)

CE to RE Delay( ID read)

Ready to RE Low

tAR1

tCR

tRR

WE High to Busy

tWB

200

Read Cycle Time

tRC

RE Access Time

tREA

tRHZ

tCHZ

tREH

tIR

RE High to Output Hi-Z

CE High to Output Hi-Z

RE High Hold Time

Output Hi-Z to RE Low

Last RE High to Busy(at sequential read)

tRB

200

CE High to Ready(in case of interception by CE at read)

CE High Hold Time(at the last serial read)⁽²⁾

RE Low to Status Output

100+tr(R/B)⁽¹⁾

tCRY

tCEH

tRSTO

tCSTO

tRHW

tWHR

tRST

250

CE Low to Status Output

RE High to WE Low

WE High to RE Low

Device Resetting Time(Read/Program/Erase)

5/10/500

NOTE :

1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.

2. To break the sequential read cycle, CE must be held high for longer time than tCEH.

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

NAND Flash Technical Notes

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-

mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality

level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-

mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design

must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to

be a valid block.

Identifying Invalid Block(s)

All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid

block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid

block has non-FFh data at the column address of 261. Since the invalid block information is also erasable in most cases, it is impos-

sible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based

on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1). Any inten-

tional erasure of the original invalid block information is prohibited.

Start

Set Block Address = 0

Increment Block Address

Check "FFh" at the column address 261

of the 1st and 2nd page in the block

Create (or update)

Invalid Block(s) Table

Check "FFh" ?

Yes

Last Block ?

Yes

End

Figure 1. Flow chart to create invalid block table.

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

NAND Flash Technical Notes (Continued)

Error in write or read operation

Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual

data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-

ure after erase or program, block replacement should be done. To improve the efficiency of memory space, it is recommended that

the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block

failure rate does not include those reclaimed blocks.

Failure Mode

Detection and Countermeasure sequence

Erase Failure

Status Read after Erase --> Block Replacement

Status Read after Program --> Block Replacement

Read back ( Verify after Program) --> Block Replacement

or ECC Correction

Write

Read

Program Failure

Single Bit Failure

Verify ECC -> ECC Correction

: Error Correcting Code --> Hamming Code etc.

Example) 1bit correction & 2bit detection

ECC

Program Flow Chart

If ECC is used, this verification

operation is not needed.

Start

Write 00h

Write 80h

Write Address

Wait for tR Time

Write Address

Write Data

Write 10h

Program Error

Verify Data

Read Status Register

Yes

Program Completed

I/O 6 = 1 ?

or R/B = 1 ?

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

Yes

Program Error

I/O 0 = 0 ?

Yes

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

NAND Flash Technical Notes (Continued)

Erase Flow Chart

Read Flow Chart

Start

Write 60h

Write 00h

Write Block Address

Write Address

Read Data

Write D0h

Read Status Register

ECC Generation

I/O 6 = 1 ?

or R/B = 1 ?

Reclaim the Error

Verify ECC

Yes

Page Read Completed

Erase Error

I/O 0 = 0 ?

Yes

Erase Completed

: If erase operation results in an error, map out

the failing block and replace it with another block.

Block Replacement

Buffer

memory

error occurs

Page a

When the error happens with page "a" of Block "A", try

to write the data into another Block "B" from an exter-

nal buffer. Then, prevent further system access to

Block "A" (by creating a "invalid block" table or other

appropriate scheme.)

Block A

Block B

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

System Interface Using CE don’t-care.

For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal

256byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for

voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-

ing would provide significant savings in power consumption.

Figure 3. Program Operation with CE don’t-care.

CLE

CE don’t-care

ALE

80h

Start Add.(3Cycle)

Data Input

10h

I/O0~7

(Max. 55ns)

tCEA

tCS

tCH

tREA

tWP

I/O0~7

out

Timing requirements : If CE is is exerted high during sequential

data-reading, the falling edge of CE to valid data(tCEA) must

be kept greater than 55ns.

Figure 4. Read Operation with CE don’t-care.

CLE

CE don’t-care

Must be held

low during tR.

ALE

R/B

Data Output(sequential)

00h

Start Add.(3Cycle)

I/O0~7

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

* Command Latch Cycle

CLE

tCLS

tCS

tCLH

tCH

tWP

tALS

tALH

ALE

tDH

tDS

Command

I/O 0 ~ 7

* Address Latch Cycle

tCLS

CLE

tCS

tWC

tWP

tWH

tALS

tALH

ALE

tDH

tDS

tDH

tDS

A16~A20

A0~A7

I/O 0 ~ 7

A8~A15

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

* Input Data Latch Cycle

tCLH

CLE

tCH

tALS

tWC

ALE

tWP

tWH

tDH

tDS

I/O 0 ~ 7

DIN 255

DIN 0

DIN 1

* Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)

tRC

tCHZ*

tREH

tREA

tCHZ*

Dout

I/O 0 ~ 7

R/B

Dout

tRR

NOTES : Transition is measured ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

* Status Read Cycle

tCLS

CLE

tCLS

tCS

tCLH

tCH

tWP

tCHZ*

tCSTO

tWHR

tDH

tRHZ*

tRSTO

tDS

tIR

Status Output

I/O 0 ~ 7

70h

READ1 OPERATION(READ ONE PAGE)

CLE

tCEH

tCHZ

tCRY

tWB

tAR

ALE

tRHZ

tRC

tRR

00h

Dout N Dout N+1 Dout N+2 Dout N+3

Dout 263

tRB

A0 ~ A7

A8 ~ A15 A16 ~ A20

I/O 0 ~ 7

R/B

Column

Address

Page(Row)

Address

Busy

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

READ1 OPERATION(INTERCEPTED BY CE)

CLE

tWB

tCHZ

tAR

ALE

tRC

tRR

Dout N+2 Dout N+3

00h

Dout N

Dout N+1

A0 ~ A7

A8 ~ A15 A16 ~ A20

I/O 0 ~ 7

R/B

Column

Address

Page(Row)

Address

Busy

READ2 OPERATION(READ ONE PAGE)

CLE

ALE

tWB

tAR

tRR

Dout

255+M+1

Dout

255+M

50h

A8 ~ A15 A16 ~ A20

Dout 263

A0 ~ A7

I/O 0 ~ 7

R/B

Selected

Row

M Address

256

Start

address M

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

SEQUENTIAL ROW READ OPERATION

CLE

ALE

Dout

N+1

Dout

N+2

Dout

263

Dout

263

00h

A0 ~ A7 A8 ~ A15 A16 ~ A20

I/O 0 ~ 7

R/B

Ready

Busy

M+1

Output

PAGE PROGRAM OPERATION

CLE

ALE

tWB

tPROG

Din

263

Din

N+1

10h

Program

80h

A0 ~ A7 A8 ~ A15 A16 ~ A20

70h

I/O0

I/O 0 ~ 7

R/B

Sequential Data

Input Command Address

1 up to 264 Byte Data

Serial Input

Read Status

Command

Column

Page(Row)

Address

Command

I/O0=0 Successful Program

I/O0=1 Error in Program

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

BLOCK ERASE OPERATION(ERASE ONE BLOCK)

CLE

tWB

tBERS

ALE

I/O 0 ~ 7

R/B

60h

A8 ~ A15 A16 ~ A20

DOh

70h

I/O0

Block

Address

Busy

Erase Command

Auto Block Erase Setup Command

Read Status I/O0=0 Successful Erase

Command

I/O0=1 Error in Erase

MANUFACTURE & DEVICE ID READ OPERATION

CLE

ALE

tREA

90h

00h

ECh

EAh

I/O0~7

Read ID Command

Maker Code

Device Code

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

DEVICE OPERATION

PAGE READ

Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-

ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-

tion. Three types of operations are available : random read, sequential page read and sequential row read.

The random read mode is enabled when the page address is changed. The 264 bytes of data within the selected page are trans-

ferred to the data registers in less than 10ms(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output

of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 80ns cycle time by sequentially pulsing RE

with CE staying low. High to low transitions of the RE clock output the data starting from the selected column address up to the last

column address(column 264).

After the data of last column address is clocked out, the next page is automatically selected for sequential read.

Waiting 10ms again allows for reading of the page. The sequential row read operation is terminated by bringing CE to high. The way

the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 256 to

263 may be selectively accessed by writing the Read2 command. Addresses A0 to A2 set the starting address of the spare area while

addresses A3 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row

read as in Read1 operation and spare eight bytes of each page may be sequentially read. The Read1 command(00h) is needed to

move the pointer back to the main area. Figures 3 thru 6 show typical sequence and timings for each read operation.

Figure 3. Read1 Operation

CLE

ALE

R/B

Start Add.(3Cycle)

A0 ~ A7 & A8 ~ A20

00h

Data Output(Sequential)

I/O 0 ~ 7

(00H Command)

Seek Time

Data Field

Spare Field

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

Figure 4. Read2 Operation

CLE

ALE

R/B

Busy(Seek Time)

Start Add.(3Cycle)

A0 ~ A2 & A8 ~ A20

Data Output(Sequential)

Spare Field

50h

I/O 0 ~ 7

(A3 ~ A7 :

Don't Care)

Seek Time

Data Field

Spare Field

Figure 5. Sequential Row Read1 Operation

R/B

00h

Start Add.(3Cycle)

A0 ~ A7 & A8 ~ A20

I/O0~7

Data Output

1st

Data Output

2nd

(264 Byte)

Nth

(264 Byte)

1st

2nd

Nth

Data Field

Spare Field

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

Figure 6. Sequential Row Read2 Operation

R/B

I/O0~7

50h

Start Add.(3Cycle)

A0 ~ A2 & A8 ~ A20

Data Output

1st

Data Output

2nd

(8Byte)

Nth

(8Byte)

(A3 ~ A7 :

Don't Care)

1st

2nd

Nth

Data Field

Spare Field

PAGE PROGRAM

The device is programmed basically on a page basis. But it also allows multiple partial page programming of a byte or consecutive

bytes up to 264 may be programmed in a single page program cycle. The number of partial page programming operation in the same

page without an intervening erase operation must not exceed ten. The addressing may be done in random order in a block. A page

program cycle consist of a serial data loading period in which up to 264 bytes of data must be loaded into the device, and nonvolatile

programming period in which the loaded data is programmed into the appropriate cell.

The sequential data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address

input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.

In order to program the bytes in the spare columns of 256 to 263, the pointer should be set to the spare area by writing the Read 2

command(50h) to the command register. The pointer remains in the spare area unless the Read 1 command(00h) is entered to retum

to the main area. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without perviously

entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms

and timings necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts, the Status

Register may be read RE and CE low after the Read Status command(70h) is written to it. The CPU can detect the completion of pro-

gram cycle by monitoring the R/B output, or the Status bit(I/O6) of the Status Register. Only the Read Status command and Reset

command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O0) may be

checked(Figure 7). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command

Figure 7. Program & Read Status Operation

tPROG

R/B

Pass

I/O 0 ~ 7

80h

Address & Data Input

I/O0

Fail

10h

70h

A0 ~ A7 & A8 ~ A20

264 Byte Data

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

BLOCK ERASE

The Erase operation is done on a block(4K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase

Setup command(60h). Only address A12 to A20 is valid while A8 to A11 is ignored. The Erase Confirm command(D0h) following the

block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command

ensures that memory contents are not accidentally erased due to external noise conditions.

At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When

the erase operation is complete, the Write Status Bit(I/O0) may be checked. Figure 8 details the sequence.

Figure 8. Block Erase Operation

tBERS

R/B

I/O 0 ~ 7

Pass

60h

I/O0

Fail

D0h

70h

Address Input(2Cycle)

Block Add. : A8 ~ A20

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether

the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs

the contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows

the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE

does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register

remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read

cycle, a read command(00h or 50h) should be given before sequential page read cycle.

Table2. Read Status Register Definition

I/O #

Status

Definition

"0" : Successful Program / Erase

I/O0

Program / Erase

"1" : Error in Program / Erase

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

"0"

Reserved for Future

Use

Device Operation

Write Protect

"0" : Busy

"1" : Ready

"1" : Not Protected

"0" : Protected

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of

00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (EAh) respectively. The command regis-

ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.

Figure 9. Read ID Operation

CLE

tCR

tAR1

ALE

tREA

I/O 0 ~ 7

00h

Dout(EAh)

90h

Dout(ECh)

Maker code

Device code

Address. 1 cycle

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random

read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no

longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and

the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is

already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST

after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 10 below.

Figure 10. RESET Operation

tRST

R/B

I/O 0 ~ 7

FFh

Table3. Device Status

After Power-up

After Reset

Operation Mode

Waiting for next command

K9F1608W0B-TCB0, K9F1608W0B-TIB0

FLASH MEMORY

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random

read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-

ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin

is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper

operation and the value may be calculated by the following equation.

VCC

VCC(Max.) - VOL(Max.)

Note*

Rp =

IOL + SIL

8mA +SIL

R/B

open drain output

where IL is the sum of the input currents of all devices tied to the

R/B pin.

*Note: K9F1608W0B : 5.1V When Vcc=3.6V~5.5V

3.2V When Vcc=2.7V~3.6V

GND

Device

DATA PROTECTION

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector

disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL

during power-up and power-down as shown in Figure 11. The two step command sequence for program/erase provides additional

software protection.

Figure 11. AC Waveforms for Power Transition

~ 2.5V

VCC

High

Package Dimensions

FLASH MEMORY

PACKAGE DIMENSIONS

44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II)

44(40) - TSOP2 - 400F

Unit :mm/Inch

0~8°

0.25

TYP

0.010

#44(40)

#23(21)

0.50

0.020

#22(20)

+0.10

-0.05

0.15

+0.004

-0.002

0.006

18.81

0.741

Max.

18.41±0.10

0.725±0.004

0.10

MAX

0.004

0.805

0.032

0.35±0.10

0.014±0.004

0.80

(

)

0.0315

K9F1608W0B-TCB0 [SAMSUNG]

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