K9F2G08U0A-PCB00_技术文档

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

K9F2G08UXA

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Document Title

256M x 8 Bit NAND Flash Memory

Revision History

Revision No History

Draft Date

Nov. 09. 2005

Mar. 17th. 06

Remark

Advance

0.0

0.1

1. Initial issue

1. 1.8V part is added.

2. tRHW, tCSD parameter is defined.

3. 4G DDP LGA part is deleted.

4. Technical note is added.(p.18)

0.2

0.3

May 25th 2006 Preliminary

1. FBGA package size is changed

2. 1.8V TSOP is deleted

June 1st 2006

Preliminary

1. 1.8V Ioh/Iol condition is changed

2. Min. tADL @ 3.3V is changed form 70ns to 100ns

0.4

1.0

1.1

June 29th 2006 Preliminary

Aug 23th 2006 Final

Jan. 15th 2007

1. 1.8V device supports Copy-Back Program

1. 1.8V AC timing is changed

2. tRPB/tRCB/tREAB is added for 1.8V device

1.2

1.3

Mar. 15th 2007

June 4th 2007

1. tCSD is changed.(10ns -> 0ns)

1. tCS 31ns -> 25ns, tREH 15ns -> 10ns (@ 1.8V)

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near your office.

2

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

256M x 8 Bit NAND Flash Memory

PRODUCT LIST

Part Number

K9F2G08R0A-J

K9F2G08U0A-P

K9F2G08U0A-I

Vcc Range

Organization

PKG Type

FBGA

1.65 ~ 1.95V

X8

TSOP1

2.70 ~ 3.60V

52ULGA

FEATURES

• Fast Write Cycle Time

• Voltage Supply

- 1.65V ~ 1.95V

- Page Program time : 200µs(Typ.)

- Block Erase Time : 1.5ms(Typ.)

- 2.70V ~ 3.60V

• Organization

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Memory Cell Array : (256M + 8M) x 8bit

- Data Register : (2K + 64) x 8bit

• Automatic Program and Erase

- Page Program : (2K + 64)Byte

- Block Erase : (128K + 4K)Byte

• Page Read Operation

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

-Endurance : 100K Program/Erase Cycles(with 1bit/512Byte

ECC)

- Data Retention : 10 Years

• Command Driven Operation

- Page Size : (2K + 64)Byte

- Random Read : 25µs(Max.)

- Serial Access : 25ns(Min.)

(*K9F2G08R0A: tRC = 42ns(Min))

• Intelligent Copy-Back with internal 1bit/528Byte EDC

• Unique ID for Copyright Protection

• Package :

- K9F2G08R0A-JCB0/JIB0 : Pb-FREE PACKAGE

63 - Ball FBGA I (10 x 13 / 0.8 mm pitch)

- K9F2G08U0A-PCB0/PIB0 : Pb-FREE PACKAGE

48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F2G08U0A-ICB0/IIB0

52 - Pin ULGA (12 x 17 / 1.00 mm pitch)

GENERAL DESCRIPTION

Offered in 256Mx8bit, the K9F2G08X0A is a 2G-bit NAND Flash Memory with spare 64M-bit. Its NAND cell provides the most cost-

effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte

page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out

at 25ns(42ns with 1.8V device) cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as com-

mand input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and

internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F2G08X0A′s extended reli-

ability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The

K9F2G08X0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable

applications requiring non-volatility.

3

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

PIN CONFIGURATION (TSOP1)

K9F2G08U0A-PCB0/PIB0

N.C

I/O7

I/O6

I/O5

I/O4

N.C

Vcc

Vss

N.C

I/O3

I/O2

I/O1

I/O0

N.C

R/B

RE

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

CE

9

N.C

Vcc

Vss

N.C

CLE

ALE

WE

WP

N.C

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48-pin TSOP1

Standard Type

12mm x 20mm

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220F

Unit :mm/Inch

20.00±0.20

0.787±0.008

#1

#48

#24

#25

1.00±0.05

0.039±0.002

0.05

0.002

MIN

1.20

0.047

MAX

18.40±0.10

0.724±0.004

0~8°

0.45~0.75

0.018~0.030

0.50

0.020

(

)

4

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

PIN CONFIGURATION (FBGA)

K9F2G08R0A-JCB0/JIB0

1

2

3

4

5

6

N.C N.C

N.C

N.C N.C

A

B

/WP ALE Vss /CE /WE R/B

NC

/RE CLE NC

NC

C

D

E

NC

NC NC

F

NC I/O0 NC

NC

Vcc

G

H

NC I/O1 NC Vcc I/O5 I/O7

Vss I/O2 I/O3 I/O4 I/O6 Vss

N.C N.C

Top View

5

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

PACKAGE DEMENSIONS(FBGA)

Top View

Bottom View

#A1 INDEX MARK(OPTIONAL)

A

10.00±0.10

0.80 x 9= 7.20

0.80 x 5= 4.00

0.80

10.00±0.10

B

6

5

4

3

2

1

(Datum A)

#A1

A

B

C

D

E

F

(Datum B)

G

H

63-∅0.45±0.05

∅

0.20

M A B

2.00

Side View

13.00±0.10

0.10MAX

0.45±0.05

6

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

PIN CONFIGURATION (ULGA)

K9F2G08U0A-ICB0/IIB0

L

M

C

E

G

H

K

N

A

B

D

J

F

NC

7

NC

/RE

NC

6

5

Vcc

NC

Vss

IO7

IO1

IO5

Vcc

R/B

/CE

IO6

IO4

NC

4

3

IO0

/WE

IO2

Vss

CLE

2

Vss

NC

/WP

IO3

Vss

1

ALE

NC

PACKAGE DIMENSIONS

52-ULGA (measured in millimeters)

Bottom View

Top View

12.00±0.10

A

10.00

2.00

1.00

3

12.00±0.10

7

6

5

4

2

1

B

1.00

(Datum A)

#A1

A

B

C

D

(Datum B)

E

F

G

H

J

K

L

M

N

41-∅

0.70±0.05

12-∅

1.00±0.05

0.1

∅

M C AB

0.1

∅

M C AB

Side View

17.00±0.10

0.10 C

7

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

PIN DESCRIPTION

Pin Name

Pin Function

DATA INPUTS/OUTPUTS

I/O0 ~ I/O7

CLE

ALE

CE

The I/O pins are used to input command, address and data, and to output data during read operations. The I/

O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,

commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are

latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and

the device does not return to standby mode in program or erase operation.

READ ENABLE

RE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

WE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE pulse.

WRITE PROTECT

WP

The WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-

age generator is reset when the WP pin is active low.

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or

random read operation is in process and returns to high state upon completion. It is an open drain output and

does not float to high-z condition when the chip is deselected or when outputs are disabled.

R/B

POWER

Vcc

Vss

N.C

VCC is the power supply for device.

GROUND

NO CONNECTION

Lead is not internally connected.

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

8

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Figure 1. K9F2G08X0A Functional Block Diagram

VCC

VSS

2,048M + 64M Bit

NAND Flash

ARRAY

X-Buffers

A12 - A28

Latches

& Decoders

(2,048 + 64)Byte x 131,072

Y-Buffers

A0 - A11

Latches

& Decoders

Data Register & S/A

Y-Gating

Command

Register

VCC

VSS

I/O Buffers & Latches

Global Buffers

CE

RE

WE

Control Logic

& High Voltage

Generator

I/0 0

Output

Driver

I/0 7

CLE ALE

WP

Figure 2. K9F2G08X0A Array Organization

1 Block = 64 Pages

(128K + 4k) Byte

1 Page = (2K + 64)Bytes

1 Block = (2K + 64)B x 64 Pages

= (128K + 4K) Bytes

1 Device = (2K+64)B x 64Pages x 2,048 Blocks

= 2,112 Mbits

128K Pages

(=2,048 Blocks)

8 bit

2K Bytes

64 Bytes

I/O 0 ~ I/O 7

Page Register

2K Bytes

64 Bytes

I/O 0

A0

I/O 1

A1

I/O 2

I/O 3

A3

I/O 4

A4

I/O 5

A5

I/O 6

A6

I/O 7

A7

Column Address

Row Address

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

5th Cycle

A2

A10

A14

A22

*L

A8

A9

A11

A15

A23

*L

A12

A20

A28

A13

A21

*L

A16

A24

*L

A17

A25

*L

A18

A26

*L

A19

A27

*L

Row Address

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than required.

9

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Product Introduction

The K9F2G08X0A is a 2,112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2,112x8 columns. Spare 64x8

columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo-

dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made

up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists

of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program

and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con-

sists of 2,048 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F2G08X0A.

The K9F2G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades

to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by

bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For

example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block

erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 264M byte physical space

requires 29 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that

order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-

ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the

command register. Table 1 defines the specific commands of the K9F2G08X0A.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another

page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and

data-input cycles are removed, system performance for solid-state disk application is significantly increased.

Table 1. Command Sets

Function

1st Cycle

00h

2nd Cycle

Acceptable Command during Busy

Read

30h

Read for Copy Back

Read ID

00h

35h

90h

-

Reset

FFh

O

Page Program

80h

10h

Two-Plane Page Program⁽³⁾

Copy-Back Program

Two-Plane Copy-Back Program⁽³⁾

Block Erase

80h---11h

85h

81h---10h

10h

85h---11h

60h

81h---10h

D0h

Two-Plane Block Erase

Random Data Input⁽¹⁾

Random Data Output⁽¹⁾

Read Status

60h---60h

85h

D0h

-

05h

E0h

70h

O

Read EDC Status⁽²⁾

7Bh

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Read EDC Status is only available on Copy Back operation.

3. Any command between 11h and 81h is prohibited except 70h and FFh.

4. K9F2G08R0A does not support Two-Plane operation.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

10

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

1.8V

3.3V

VCC

VIN

-0.6 to +2.45

-0.6 to +4.6

Voltage on any pin relative to VSS

V

-0.6 to +4.6

VI/O

-0.6 to Vcc + 0.3 (< 2.45V)

-0.6 to Vcc + 0.3 (< 4.6V)

K9F2G08X0A-XCB0

K9F2G08X0A-XIB0

K9F2G08X0A-XCB0

K9F2G08X0A-XIB0

-10 to +125

Temperature Under

Bias

TBIAS

°C

-40 to +125

-65 to +150

5

Storage Temperature

TSTG

IOS

°C

mA

Short Circuit Current

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.

Maximum DC voltage on input/output pins is V^CC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F2G08X0A-XCB0 :TA=0 to 70°C, K9F2G08X0A-XIB0:TA=-40 to 85°C)

1.8V

Typ.

1.8

0

3.3V

Typ.

3.3

0

Parameter

Symbol

Unit

Min

1.65

0

Max

1.95

0

Min

2.7

0

Max

3.6

0

Supply Voltage

VCC

VSS

V

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

1.8V

3.3V

Parameter

Symbol

Test Conditions

Unit

Min

Typ

Max

Min

Typ

Max

tRC=25ns

(K9F2G08R0A: 42ns)

CE=VIL, IOUT=0mA

Page Read with

Serial Access

ICC1

Operating

Current

-

10

20

-

15

30

mA

Program

Erase

ICC2

ICC3

ISB1

ISB2

ILI

-

CE=VIH, WP=0V/VCC

CE=VCC-0.2, WP=0V/VCC

VIN=0 to Vcc(max)

VOUT=0 to Vcc(max)

-

Stand-by Current(TTL)

Stand-by Current(CMOS)

Input Leakage Current

Output Leakage Current

Input High Voltage

-

10

-

1

-

10

-

1

50

-

50

-

±10

µA

ILO

-

±10

(1)

0.8xVcc

-0.3

-

Vcc+0.3 0.8xVcc

-

Vcc+0.3

0.2xVcc

VIH

(1)

Input Low Voltage, All inputs

VIL

-

0.2xVcc

-

-0.3

2.4

-

K9F2G08R0A: IOH=-100µA

K9F2G08U0A: IOH=-400µA

V

Output High Voltage Level

VOH

VOL

Vcc-0.1

-

K9F2G08R0A: IOL=100µA

K9F2G08U0A: IOL=2.1mA

Output Low Voltage Level

Output Low Current(R/B)

-

0.1

-

0.4

-

IOL(R/B) VOL=0.4V

3

4

8

10

mA

NOTE : 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

2. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.

11

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

VALID BLOCK

Parameter

Symbol

Min

Typ.

Max

Unit

K9F2G08X0A

NVB

2,008

-

2,048

Blocks

NOTE :

1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is

presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-

gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.

3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.

AC TEST CONDITION

(K9F2G08X0A-XCB0 :TA=0 to 70°C, K9F2G08X0A-XIB0:TA=-40 to 85°C,

K9F2G08R0A: Vcc=1.65~1.95V, K9F2G08UA: Vcc=2.7V~3.6V unless otherwise noted)

Parameter

Input Pulse Levels

K9F2G08R0A

K9F2G08U0A

0V to Vcc

Input Rise and Fall Times

Input and Output Timing Levels

Output Load

5ns

Vcc/2

5ns

Vcc/2

1 TTL GATE and CL=30pF

1 TTL GATE and CL=50pF

CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)

Item

Symbol

Test Condition

Min

Max

10

Unit

Input/Output Capacitance

Input Capacitance

CI/O

VIL=0V

-

pF

CIN

VIN=0V

10

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE

H

L

ALE

L

CE

L

WE

RE

H

WP

Mode

X

Command Input

Read Mode

Write Mode

H

L

H

X

Address Input(5clock)

Command Input

H

L

H

L

H

Address Input(5clock)

L

H

Data Input

L

H

X

Data Output

X

H

X

During Read(Busy)

During Program(Busy)

During Erase(Busy)

Write Protect

X

H

X

H

L

X⁽¹⁾

X

(2)

X

Stand-by

0V/VCC

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

12

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Program / Erase Characteristics

Parameter

Symbol

tPROG

tDBSY

Nop

Min

Typ

200

0.5

-

Max

700

1

Unit

µs

Program Time

-

Dummy Busy Time for Two-Plane Page Program

Number of Partial Program Cycles

Block Erase Time

µs

4

cycles

ms

tBERS

1.5

2

NOTE : 1. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.

2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25°C temperature.

AC Timing Characteristics for Command / Address / Data Input

Min

Max

Parameter

Symbol

Unit

1.8V

21

5

3.3V

12

5

1.8V

3.3V

(1)

CLE Setup Time

-

ns

tCLS

CLE Hold Time

tCLH

(1)

CE Setup Time

25

5

20

5

tCS

CE Hold Time

tCH

tWP

WE Pulse Width

ALE Setup Time

ALE Hold Time

21

5

12

5

(1)

tALS

tALH

(1)

Data Setup Time

Data Hold Time

20

5

12

5

tDS

tDH

tWC

tWH

Write Cycle Time

WE High Hold Time

Address to Data Loading Time

42

15

100

25

10

100

(2)

tADL

NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low

2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle

13

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

AC Characteristics for Operation

Min

Max

Unit

Parameter

Symbol

1.8V

-

3.3V

-

1.8V

3.3V

Data Transfer from Cell to Register

ALE to RE Delay

tR

tAR

25

µs

ns

µs

ns

10

20

21

-

10

20

12

-

CLE to RE Delay

tCLR

tRR

-

Ready to RE Low

-

RE Pulse Width

tRP

-

WE High to Busy

tWB

100

Read Cycle Time

tRC

42

-

25

-

RE Access Time

tREA

tCEA

tRHZ

tCHZ

tCSD

tRHOH

tRLOH

tCOH

tREH

tIR

30

20

CE Access Time

-

35

25

RE High to Output Hi-Z

CE High to Output Hi-Z

CE High to ALE or CLE Don’t Care

RE High to Output Hold

RE Low to Output Hold

CE High to Output Hold

RE High Hold Time

-

100

-

30

0

-

15

5

15

5

-

15

10

0

15

-

10

0

-

Output Hi-Z to RE Low

RE High to WE Low

-

tRHW

tWHR

tRST

100

60

-

100

60

-

WE High to RE Low

-

5/10/500⁽¹⁾

Device Resetting Time(Read/Program/Erase)

RE Pulse Width during Busy State

Read Cycle Time during Busy State

RE Access Time during Busy State

(2)

35

50

-

tRPB

(2)

tRCB

(2)

40

tREAB

NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.

2. This parameter (tRPB/tRCB/tREAB) must be used only for 1.8V device.

14

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K9F2G08U0A

FLASH MEMORY

NAND Flash Technical Notes

Initial Invalid Block(s)

Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.

The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)

have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)

does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-

sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on

00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.

Identifying Initial Invalid Block(s)

All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-

tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every

initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in

most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the

initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following

suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.

Start

Set Block Address = 0

Increment Block Address

Check "FFh" at the column address 2048

*

of the 1st and 2nd page in the block

No

Create (or update)

Check "FFh"

Initial

Invalid Block(s) Table

Yes

No

Last Block ?

Yes

End

Figure 3. Flow chart to create initial invalid block table

15

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

NAND Flash Technical Notes (Continued)

Error in write or read operation

Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual

data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-

ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect

the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased

empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be

employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be

reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.

Failure Mode

Erase Failure

Detection and Countermeasure sequence

Status Read after Erase --> Block Replacement

Status Read after Program --> Block Replacement

Verify ECC -> ECC Correction

Write

Read

Program Failure

Single Bit Failure

: Error Correcting Code --> Hamming Code etc.

Example) 1bit correction & 2bit detection

ECC

Program Flow Chart

Start

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

No

I/O 6 = 1 ?

or R/B = 1 ?

Yes

*

No

Program Error

I/O 0 = 0 ?

Yes

Program Completed

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

*

16

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

NAND Flash Technical Notes (Continued)

Erase Flow Chart

Read Flow Chart

Start

Write 00h

Start

Write 60h

Write Block Address

Write Address

Write 30h

Write D0h

Read Data

Read Status Register

ECC Generation

No

I/O 6 = 1 ?

or R/B = 1 ?

No

Verify ECC

Reclaim the Error

Yes

*

No

Yes

Erase Error

I/O 0 = 0 ?

Page Read Completed

Yes

Erase Completed

: If erase operation results in an error, map out

the failing block and replace it with another block.

*

Block Replacement

Block A

1st

{

(n-1)th

1

nth

an error occurs.

(page)

Buffer memory of the controller.

Block B

1st

2

{

(n-1)th

nth

(page)

* Step1

When an error happens in the nth page of the Block ’A’ during erase or program operation.

* Step2

Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)

* Step3

Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.

* Step4

Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme.

17

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

NAND Flash Technical Notes (Continued)

Copy-Back Operation with EDC & Sector Definition for EDC

Generally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source

page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate

bit errors.

K9F2G08X0A supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation

should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input

before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial

modification smaller than a sector corrupts the on-chip EDC codes.

A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte

spare area.

Main Field (2,048 Byte)

Spare Field (64 Byte)

"A" area

"B" area

"C" area

"D" area

"E" area

"F" area

"G" area

"H" area

(1’st sector)

(2’nd sector)

(3’rd sector)

(4’th sector)

(1’st sector) (2’nd sector)(3’rd sector)(4’th sector)

512 Byte

16 Byte

Table 2. Definition of the 528-Byte Sector

Main Field (Column 0~2,047)

Spare Field (Column 2,048~2,111)

Sector

Area Name

Column Address

Area Name

Column Address

2,048 ~ 2,063

2,064 ~ 2,079

2,080 ~ 2,095

2,096 ~ 2,111

1’st 528-Byte Sector

2’nd 528-Byte Sector

3’rd 528-Byte Sector

4’th 528-Byte Sector

"A"

"B"

"C"

"D"

0 ~ 511

"E"

"F"

"G"

"H"

512 ~ 1,023

1,024 ~ 1,535

1,536 ~ 2,047

Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most

significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the

LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0.

(64)

Page 63

Page 31

Page 63

Page 31

:

(1)

:

(32)

:

(3)

(2)

(1)

Page 2

Page 1

Page 0

(3)

(32)

(2)

Page 2

Page 1

Page 0

Data register

From the LSB page to MSB page

DATA IN: Data (1)

Data (64)

Ex.) Random page program (Prohibition)

DATA IN: Data (1)

Data (64)

18

K9F2G08R0A

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FLASH MEMORY

System Interface Using CE don’t-care.

For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte

data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or

audio applications which use slow cycle time on the order of µ-seconds, de-activating CE during the data-loading and serial access

would provide significant savings in power consumption.

Figure 4. Program Operation with CE don’t-care.

CLE

CE don’t-care

CE

WE

ALE

I/Ox

80h

Address(5Cycles)

tCS

Data Input

10h

tCH

tCEA

CE

tREA

tWP

RE

WE

out

I/O0~7

Figure 5. Read Operation with CE don’t-care.

CLE

CE

CE don’t-care

RE

ALE

tR

R/B

WE

Data Output(serial access)

I/OX

00h

Address(5Cycle)

30h

19

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

NOTE

I/O

I/Ox

DATA

ADDRESS

Device

Data In/Out

2,112byte

Col. Add1

Col. Add2

Row Add1

Row Add2

Row Add3

K9F2G08X0A

I/O 0 ~ I/O 7

A0~A7

A8~A11

A12~A19

A20~A27

A28

Command Latch Cycle

CLE

tCLH

tCLS

tCS

tCH

CE

tWP

WE

tALS

tALH

ALE

I/Ox

tDH

tDS

Command

Address Latch Cycle

tCLS

CLE

tCS

tWC

CE

tWP

WE

tWH

tALH

tWH

tALH

tWH

tALH

tALS

tALH

tDH

tALS

ALE

I/Ox

tDH

tDS

Col. Add2

Row Add1

Col. Add1

Row Add2

Row Add3

20

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Input Data Latch Cycle

tCLH

CLE

tCH

CE

tWC

ALE

tALS

tWP

WE

tWH

tDH

tDS

I/Ox

DIN final

DIN 0

DIN 1

* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)

tRC

CE

tCHZ

tCOH

tREH

tREA

RE

tRHZ

tRHOH

I/Ox

Dout

tRR

R/B

NOTES : Transition is measured at ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

tRLOH is valid when frequency is higher than 33MHz.

tRHOH starts to be valid when frequency is lower than 33MHz.

21

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)

CE

tRC

tCHZ

tCOH

tRP

tREH

RE

tRHZ

tREA

tCEA

tREA

tRLOH

tRHOH

I/Ox

R/B

Dout

tRR

NOTES : Transition is measured at ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

tRLOH is valid when frequency is higher than 33MHz.

tRHOH starts to be valid when frequency is lower than 33MHz.

Status Read Cycle & EDC Status Read Cycle

tCLR

CLE

tCLS

tCLH

tCS

CE

tCH

tWP

WE

RE

tCEA

tCHZ

tCOH

tWHR

tRHZ

tDH

tDS

tREA

tIR

tRHOH

I/Ox

Status Output

70h or 7Bh

22

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Read Operation

tCLR

CLE

CE

tWC

WE

ALE

RE

tCSD

tWB

tAR

tRHZ

tR

tRC

tRR

Col. Add2 Row Add1 Row Add2

00h

Col. Add1

30h

Dout N

Dout N+1

Dout M

Row Add3

I/Ox

Column Address

Row Address

Busy

R/B

Read Operation(Intercepted by CE)

tCLR

CLE

CE

tCSD

WE

ALE

RE

tCHZ

tCOH

tWB

tAR

tR

tRC

tRR

Row Add2 Row Add3

Dout N+2

00h

Col. Add1 Col. Add2 Row Add1

30h

Dout N+1

Dout N

I/Ox

R/B

Row Address

Column Address

Busy

23

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

24

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Page Program Operation

CLE

CE

tWC

WE

ALE

RE

tPROG

tWHR

tWB

tADL

Din

N

Din

M

Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3

80h

I/Ox

R/B

10h

70h

I/O0

SerialData

Input Command

Program

Command

1 up to m Byte

Serial Input

Read Status

Command

Column Address

Row Address

I/O

0

=0 Successful Program

=1 Error in Program

I/O0

NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

25

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

≈

≈ ≈

≈

26

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

≈

≈ ≈

≈

27

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Block Erase Operation

CLE

CE

tWC

WE

tBERS

tWB

tWHR

ALE

RE

I/Ox

Row Add1 Row Add2 Row Add3

60h

D0h

70h

I/O 0

Row Address

Busy

R/B

Auto Block Erase

Setup Command

Erase Command

I/O

0

=0 Successful Erase

Read Status I/O

Command

0=1 Error in Erase

28

K9F2G08R0A

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FLASH MEMORY

≈

≈ ≈

≈

≈ ≈

≈

29

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

30

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Read ID Operation

CLE

CE

WE

ALE

RE

tAR

tREA

Device

Code

I/Ox

3rd cyc.

4th cyc.

5th cyc.

00h

ECh

90h

Read ID Command

Maker Code Device Code

Address 1cycle

Device

Device Code (2nd Cycle)

3rd Cycle

00h

4th Cycle

15h

5th Cycle

44h

K9F2G08R0A

K9F2G08U0A

AAh

DAh

10h

95h

44h

31

K9F2G08R0A

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FLASH MEMORY

ID Definition Table

90 ID : Access command = 90H

Description

1^stByte

2^ndByte

3^rdByte

4^thByte

5^thByte

Maker Code

Device Code

Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc

Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum

Plane Number, Plane Size

3rd ID Data

Internal Chip Number

Cell Type

Description

I/O7

I/O6

I/O5 I/O4

I/O3 I/O2

I/O1 I/O0

1

2

4

8

0

1

0

1

0

1

2 Level Cell

4 Level Cell

8 Level Cell

0

1

0

1

0

1

16 Level Cell

1

2

4

8

0

1

0

1

0

1

Number of

Simultaneously

Programmed Pages

Interleave Program

Between multiple chips

Not Support

Support

0

1

Not Support

Support

0

1

Cache Program

4th ID Data

Description

I/O7

I/O6

I/O5 I/O4

I/O3

I/O2

I/O1 I/O0

1KB

2KB

4KB

8KB

0

1

0

1

0

1

Page Size

(w/o redundant area )

64KB

128KB

256KB

512KB

0

1

0

1

0

1

Block Size

(w/o redundant area )

Redundant Area Size

( byte/512byte)

8

16

0

1

x8

x16

0

1

Organization

50ns/30ns

25ns

Reserved

0

1

0

1

0

1

Serial Access Minimum

32

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FLASH MEMORY

5th ID Data

Description

I/O7

I/O6 I/O5 I/O4

I/O3 I/O2

I/O1

I/O0

1

2

4

8

0

1

0

1

0

1

Plane Number

64Mb

128Mb

256Mb

512Mb

1Gb

2Gb

4Gb

8Gb

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Plane Size

(w/o redundant Area)

Reserved

0

33

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Device Operation

PAGE READ

Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command

is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data

within the selected page are transferred to the data registers in less than 25µs(tR). The system controller can detect the completion of

this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read

out in 25ns(42ns with 1.8V device) cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make

the device output the data starting from the selected column address up to the last column address.

The device may output random data in a page instead of the consecutive sequential data by writing random data output command.

The column address of next data, which is going to be out, may be changed to the address which follows random data output com-

mand. Random data output can be operated multiple times regardless of how many times it is done in a page.

Figure 6. Read Operation

CLE

CE

WE

ALE

tR

R/B

RE

I/Ox

00h

Address(5Cycle)

30h

Data Output(Serial Access)

Col. Add.1,2 & Row Add.1,2,3

Data Field

Spare Field

34

K9F2G08R0A

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FLASH MEMORY

Figure 7. Random Data Output In a Page

tR

R/B

RE

Address

5Cycles

Address

2Cycles

Data Output

30h

E0h

00h

05h

I/Ox

Col. Add.1,2 & Row Add.1,2,3

Col. Add.1,2

Data Field

Spare Field

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive

bytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the same

page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential

order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into

the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.

The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and

then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data

input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random

data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.

Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector

and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes.

The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the

serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-

ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the

Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-

gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset

command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be

checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command

register remains in Read Status command mode until another valid command is written to the command register.

Figure 8. Program & Read Status Operation

tPROG

R/B

"0"

Pass

80h

Address & Data Input

I/O0

Fail

I/Ox

10h

70h

Col. Add.1,2 & Row Add.1,2,3

Data

"1"

35

K9F2G08R0A

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FLASH MEMORY

Figure 9. Random Data Input In a Page

tPROG

R/B

"0"

Pass

80h

Address & Data Input

I/O0

I/Ox

85h

10h

70h

Col. Add.1,2

Data

Col. Add.1,2 & Row Add1,2,3

Data

"1"

Fail

Note: 1. For EDC operation, only one time random data input is possible at the same address.

Copy-Back Program

The Copy-Back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.

Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-

efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned

free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-

ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves

the whole 2,112-byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input com-

mand (85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to

actually begin the programming operation. During tPROG, the device executes EDC of itself. Once the program process starts, the

Read Status Register command (70h) or Read EDC Status command (7Bh) may be entered to read the status register. The system

controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register.

When the Copy-Back Program is complete, the Write Status Bit(I/O 0) and EDC Status Bits (I/O 1 ~ I/O 2) may be checked(Figure 10

& Figure 11& Figure 12). The internal write verification detects only errors for "1"s that are not successfully programmed to "0"s and

the internal EDC checks whether there is only 1-bit error for each 528-byte sector of the source page. More than 2-bit error detection

is not available for each 528-byte sector. The command register remains in Read Status command mode or Read EDC Status com-

mand mode until another valid command is written to the command register.

During copy-back program, data modification is possible using random data input command (85h) as shown in Figure11. But EDC

status bits are not available during copy back for some bits or bytes modified by Random Data Input operation.

However, in case of the 528 byte sector unit modification, EDC status bits are available.

Figure 10. Page Copy-Back Program Operation

tR

tPROG

R/B

I/Ox

"0"

Add.(5Cycles)

Pass

00h

35h

Add.(5Cycles)

10h

70h/7Bh

I/O0

85h

Col. Add.1,2 & Row Add.1,2,3

Destination Address

Col. Add.1,2 & Row Add.1,2,3

Source Address

"1"

Fail

Note: 1. Copy-Back Program operation is allowed only within the same memory plane.

2. On the same plane, It’s prohibited to operate copy-back program from an odd address page(source page) to an even

address page(target page) or from an even address page(source page) to an odd address page(target page).

Therefore, the copy-back program is permitted just between odd address pages or even address pages.

Figure 11. Page Copy-Back Program Operation with Random Data Input

tPROG

tR

R/B

Add.(5Cycles)

Add.(2Cycles)

Col. Add.1,2

I/Ox

35h

Add.(5Cycles)

70h

00h

85h

Data

85h

Data

10h

Col. Add.1,2 & Row Add.1,2,3

Source Address

Col. Add.1,2 & Row Add.1,2,3

Destination Address

There is no limitation for the number of repetition.

Note: 1. For EDC operation, only one time random data input is possible at the same address.

36

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FLASH MEMORY

EDC OPERATION

Note that for the user who use Copy-Back with EDC mode, only one time random data input is possible at the same address during

Copy-Back program or page program mode. For the user who use Copy-Back without EDC, there is no limitation for the random data

input at the same address.

Figure 12. Page Copy-Back Program Operation with EDC & Read EDC Status

tR

tPROG

R/B

I/Ox

Add.(5Cycles)

00h

35h

Add.(5Cycles)

10h

EDC Status Output

85h

7Bh

Col. Add.1,2 & Row Add.1,2,3

Destination Address

Col. Add.1,2 & Row Add.1,2,3

Source Address

BLOCK ERASE

The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup

command(60h). Only address A18 to A28 is valid while A12 to A17 is ignored. The Erase Confirm command(D0h) following the block

address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that

memory contents are not accidentally erased due to external noise conditions.

At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When

the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.

Figure 13. Block Erase Operation

tBERS

R/B

"0"

Pass

60h

I/O0

Fail

70h

Address Input(3Cycle)

Row Add 1,2,3

I/Ox

D0h

"1"

Two-Plane Page Program

Two-Plane Page Program is an extension of Page Program, for a single plane with 2112 byte page registers. Since the device is

equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous programming of two

pages.

After writing the first set of data up to 2112 byte into the selected page register, Dummy Page Program command (11h) instead of

actual Page Program command (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved,

R/B remains in Busy state for a short period of time(tDBSY). Read Status command (70h) may be issued to find out when the device

returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the

81h command and address sequences. After inputting data for the last plane, actual True Page Program(10h) instead of dummy

Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the

same as that of Page Program. Althougth two planes are programmed simultaneously, pass/fail is not available for each page when

the program operation completes. Status bit of I/O 0 is set to "1" when any of the pages fails.

Restriction in addressing with Two-Plane Page Program is shown is Figure14.

37

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Figure 14. Two-Plane Page Program

tDBSY

Note*²

tPROG

R/B

I/O0 ~ 7

Address & Data Input

80h

11h

70h

81h

10h

A0 ~ A11 : Valid

A12 ~ A17 : Fixed ’Low’

A⁰~ A11 : Valid

A12 ~ A17 : Valid

A18

: Fixed ’Low’

A18

: Fixed ’High’

A19 ~ A28 : Fixed ’Low’

A19 ~ A28 : Valid

NOTE :1. It is noticeable that same row address except for A¹⁸is applied to the two blocks

2. Any command between 11h and 81h is prohibited except 70h and FFh.

80h

11h

81h

10h

Data

Input

Plane 0

Plane 1

(1024 Block)

Block 0

Block 2

Block 1

Block 3

Block 2044

Block 2046

Block 2045

Block 2047

Two-Plane Block Erase

Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each

plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by

three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane.

The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/

Busy status bit (I/O 6).

Figure 15. Two-Plane Block Erase Operation

tBERS

R/B

"0"

60h

D0h

70h

Pass

I/OX

60h

Address (3 Cycle)

I/O0

A¹²~ A17 : Fixed ’Low’

"1"

Fail

A¹⁸

:Fixed ’Low’

A¹⁸

: Fixed ’High’

A¹⁹~ A28 : Fixed ’Low’

A¹⁹~ A28 : valid

38

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Two-Plane Copy-Back Program

Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 2112 byte page registers. Since the

device is equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous program-

ming of two pages.

Figure 16. Two-Plane Copy-Back Program Operation

tR

R/B

I/Ox

Add.(5Cycles)

Col. Add.1,2 & Row Add.1,2,3

Add.(5Cycles)

00h

35h

00h

35h

Col. Add.1,2 & Row Add.1,2,3

Source Address On Plane1

Source Address On Plane0

1

tPROG

tDBSY

R/B

I/Ox

Add.(5Cycles)

85h

Add.(5Cycles)

10h

11h

81h

70h

Note3

Col. Add.1,2 & Row Add.1,2,3

Destination Address

Col. Add.1,2 & Row Add.1,2,3

Destination Address

1

A⁰~ A11 : Fixed ’Low’

A¹²~ A17 : Fixed ’Low’

A⁰~ A11 : Fixed ’Low’

A¹²~ A17 : Valid

A¹⁸

: Fixed ’Low’

A¹⁸

: Fixed ’High’

A¹⁹~ A28 : Fixed ’Low’

A¹⁹~ A28 : Valid

Plane0

Plane1

Source page

Target page

(1) : Read for Copy Back On Plane0

(2) : Read for Copy Back On Plane1

(3) : Two-Plane Copy-Back Program

Target page

(1)

(3)

(2)

(3)

Data Field

Spare Field

Data Field

Spare Field

Note: 1. Copy-Back Program operation is allowed only within the same memory plane.

2. On the same plane, It’s prohibited to operate copy-back program from an odd address page(source page) to an even

address page(target page) or from an even address page(source page) to an odd address page(target page).

Therefore, the copy-back program is permitted just between odd address pages or even address pages.

3. Any command between 11h and 81h is prohibited except 70h and FFh.

39

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

Figure 17. Two-Plane Copy-Back Program Operation with Random Data Input

tR

R/B

I/Ox

Add.(5Cycles)

Col. Add.1,2 & Row Add.1,2,3

Source Address On Plane0

Add.(5Cycles)

00h

35h

00h

35h

Col. Add.1,2 & Row Add.1,2,3

Source Address On Plane1

1

tDBSY

R/B

I/Ox

Add.(5Cycles)

11h

Data

85h

Data

Add.(2Cycles)

Col. Add.1,2

85h

Note4

Col. Add.1,2 & Row Add.1,2,3

Destination Address

2

1

A0 ~ A11 : Valid

A¹²~ A17 : Fixed ’Low’

A¹⁸

: Fixed ’Low’

A¹⁹~ A28 : Fixed ’Low’

tPROG

R/B

Add.(5Cycles)

10h

Data

85h

Data

Add.(2Cycles)

Col. Add.1,2

I/Ox

81h

Col. Add.1,2 & Row Add.1,2,3

Destination Address

2

A0 ~ A11 : Valid

A¹²~ A17 : Valid

A¹⁸

: Fixed ’High’

A¹⁹~ A28 : Valid

Note: 1. Copy-Back Program operation is allowed only within the same memory plane.

2. On the same plane, It’s prohibited to operate copy-back program from an odd address page(source page) to an even

address page(target page) or from an even address page(source page) to an odd address page(target page).

Therefore, the copy-back program is permitted just between odd address pages or even address pages.

3. EDC status Bits are not available during copy back for some bits or bytes modified by Random Data Input operation.

In case of the 528 byte plane unit modification, EDC status bits are available.

4. Any command between 11h and 81h is prohibited except 70h and FFh.

40

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FLASH MEMORY

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether

the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs

the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows

the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE

does not need to be toggled for updated status. Refer to Table 3 for specific Status Register definitions. The command register

remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read

cycle, the read command(00h) should be given before starting read cycles.

Table 3. Status Register Definition for 70h Command

I/O

Page Program

Pass/Fail

Not use

Block Erase

Pass/Fail

Not use

Read

Not use

Definition

Fail : "1"

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

Pass : "0"

Not use

Don’t -cared

Busy : "0"

Not use

Not Use

Ready/Busy

Write Protect

Ready/Busy

Write Protect

Ready/Busy

Write Protect

Ready : "1"

Protected : "0"

Not Protected : "1"

NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.

READ EDC STATUS

Read EDC status operation is only available on ’Copy Back Program’. The device contains an EDC Status Register which may be

read to find out whether there is error during ’Read for Copy Back’. After writing 7Bh command to the command register, a read cycle

outputs the content of the EDC Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line

control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired.

RE or CE does not need to be toggled for updated status. Refer to Table 4 for specific Status Register definitions. The command reg-

ister remains in EDC Status Read mode until further commands are issued to it.

Table 4. Status Register Definition for 7Bh Command

I/O

Copy Back Program

Pass/Fail of Copy Back Program

EDC Status

Page Program Block Erase

Read

Definition

Pass : "0", Fail : "1"

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

Pass/Fail

Not use

Pass/Fail

Not use

Not Use

No Error : "0", Error : "1"

Valid : "1", Invalid : "0"

Don’t -cared

Validity of EDC Status

Not Use

Not use

Not Use

Don’t -cared

Not Use

Don’t -cared

I/O 6 Ready/Busy of Copy Back Program

Ready/Busy

Ready/Busy Busy : "0", Ready : "1"

I/O 7 Write Protect of Copy Back Program Write Protect

Write Protect Write Protect Protected : "0", Not Protected :"1"

NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.

2. More than 2-bit error detection isn’t available for each 528 Byte sector.

That is to say, only 1-bit error detection is avaliable for each 528 Byte sector.

41

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FLASH MEMORY

Read ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of

00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively.

The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation sequence.

Figure 18. Read ID Operation

tCLR

CLE

CE

tCEA

WE

ALE

RE

tAR

tWHR

tREA

Device

Code

I/OX

90h

ECh

3rd Cyc.

4th Cyc.

5th Cyc.

00h

Address. 1cycle

Maker code

Device code

Device

Device Code (2nd Cycle)

3rd Cycle

00h

4th Cycle

15h

5th Cycle

44h

K9F2G08R0A

K9F2G08U0A

AAh

DAh

10h

95h

44h

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random

read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no

longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and

the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be

accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 19

below.

Figure 19. RESET Operation

tRST

R/B

I/OX

FFh

Table 5. Device Status

After Power-up

After Reset

Operation mode

00h Command is latched

Waiting for next command

42

K9F2G08R0A

K9F2G08U0A

FLASH MEMORY

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random

read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-

ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is

an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and

current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig.20). Its value can be

determined by the following guidance.

Rp

ibusy

VCC

1.8V device - VOL : 0.1V, VOH : VCC-0.1V

3.3V device - VOL : 0.4V, VOH : 2.4V

Ready Vcc

R/B

open drain output

VOH

C_L

VOL

Busy

tf

tr

GND

Device

Figure 19. Rp vs tr ,tf & Rp vs ibusy

@ Vcc = 3.3V, Ta = 25°C , C_L= 50pF

@ Vcc = 1.8V, Ta = 25°C , C_L= 30pF

Ibusy [A]

200

2.4

Ibusy

300n

3m 300n

3m

150

1.2

Ibusy

1.70

200n

100n

200n

2m

100

0.8

2m

1m

120

0.85

60

90

tr

30

50

1.8

0.6

1.8

tr

1m 100n

0.57

1.70

0.43

1.70

1.8

2K

1.8

tf

1.70

2K

tf

tr,tf [s]

4K

1K

3K

1K

3K

Rp(ohm)

Rp value guidance

VCC(Max.) - VOL(Max.)

1.85V

Rp(min, 1.8V part) =

Rp(min, 3.3V part) =

=

IOL + ΣIL

3mA + ΣIL

VCC(Max.) - VOL(Max.)

3.2V

IOL + ΣIL

8mA + ΣIL

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp(max) is determined by maximum permissible limit of tr

43

K9F2G08R0A

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FLASH MEMORY

Data Protection & Power up sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector

disables all functions whenever Vcc is below about 1.1V(1.8V device), 2V(3.3V device). WP pin provides hardware protection and is

recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 100µs is required before internal cir-

cuit gets ready for any command sequences as shown in Figure 21. The two step command sequence for program/erase provides

additional software protection.

Figure 21. AC Waveforms for Power Transition

1.8V device : ~ 1.5V

3.3V device : ~ 2.5V

1.8V device : ~ 1.5V

3.3V device : ~ 2.5V

VCC

High

WP

WE

100µs

44


型号：	K9F2G08U0A-PCB00
厂家：	SAMSUNG
描述：	Flash, 256MX8, 30ns, PDSO48, 12 X 20 MM, 0.50 MM PITCH, LEAD FREE, TSOP1-48 光电二极管
文件：	总44页 (文件大小：999K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K9F2G08U0A-PCB00 [SAMSUNG]

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