K9GAG08B0M-P_技术文档

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

K9XXG08UXM

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure couldresult in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Document Title

2G x 8 Bit NAND Flash Memory

Revision History

Revision No History

Draft Date

Remark

0.0

0.1

1. Initial issue

April 12th 2006 Advance

Sep. 21th 2006 Advance

1. Add read status 2 command F1h

2. Add 2-plane read operation

3. Add address map (Table2)

4. Remove adjacent page relationship table

5. Modify figure of 2-plane copy-back program with random data input

6. Modify figure of Rp vs tr ,tf & Rp vs ibusy

7. Data retention 5years -> 10 years

8. Remove K9LBG08U1M

9. Modify figure of 2-plane page program

10. Add nWP timing guide

11. Add 2-plane read for copy-back operation

12. Add 2-plane random data out operation

13. Modify command table and note

14. Modify invalid block definition

15. Add program operation with 2KB data loading timing guide

16. tRLOH is valid when frequency is higher than 20MHz.

tRHOH starts to be valid when frequency is lower than 20MHz.

-> tRLOH is valid when frequency is higher than 33MHz.

tRHOH starts to be valid when frequency is lower than 33MHz.

0.2

1. Add 2.7V part

Dec. 8th 2006

Advance

2. tCDS is added. (min. 10ns)

0.3

0.4

0.5

0.6

1. Endurance is changed (10K->5K)

Dec. 12th 2006 Advance

Dec. 21st 2006 Preliminary

Jan. 12th 2007 Preliminary

Feb. 12th 2007 Preliminary

1. Endurance is changed (5K -> TBD)

1. K9GAG08U0M-I/K9LBG08U0M-I is added.

2. Random data output for copy back is added.

3. Wafer level capacitance is added.

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near your office.

2

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

2G x 8 Bit NAND Flash Memory

PRODUCT LIST

Part Number

K9GAG08U0M-P

K9GAG08B0M-P

K9GAG08U0M-I

K9LBG08U1M-I

Vcc Range

2.7V ~ 3.6V

2.5V ~ 2.9V

Organization

PKG Type

TSOP1

X8

2.7V ~ 3.6V

52ULGA

FEATURES

• Voltage Supply

• Fast Write Cycle Time

- 2.7V Device(K9F8G08B0M) : 2.5V ~ 2.9V

- 3.3V Device(K9F8G08U0M) : 2.7V ~ 3.6V

• Organization

- Program time : 800µs(Typ.)

- Block Erase Time : 1.5ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Memory Cell Array : (2G + 64M) x 8bit

- Data Register

: (4K + 128) x 8bit

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : TBD(with 4bit/512byte ECC)

- Data Retention : 10 Years

• Automatic Program and Erase

- Page Program : (4K + 128)Byte

- Block Erase : (512K + 16K)Byte

• Page Read Operation

• Command Register Operation

- Page Size : (4K + 128)Byte

- Random Read : 60µs(Max.)

- Serial Access : 25ns(Min.)

• Memory Cell : 2bit / Memory Cell

• Unique ID for Copyright Protection

• Package :

- K9GAG08U0M-PCB0/PIB0 : Pb-FREE PACKAGE

48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9GAG08B0M-PCB0/PIB0 : Pb-FREE PACKAGE

48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9GAG08U0M-ICB0/IIB0

52 - Pin ULGA (12 x 17 / 1.00 mm pitch)

- K9LBG08U1M-ICB0/IIB0

52 - Pin ULGA (12 x 17 / 1.00 mm pitch)

GENERAL DESCRIPTION

Offered in 2Gx8bit, the K9GAG08X0M is a 16G-bit NAND Flash Memory with spare 512M-bit. The device is offered in 2.7V and 3.3V

Vcc. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be per-

formed in typical 800µs on the 4,224-byte page and an erase operation can be performed in typical 1.5ms on a (512K+16K)byte

block. Data in the data register can be read out at 25ns cycle time per byte. The I/O pins serve as the ports for address and data

input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repe-

tition, where required, and internal verification and margining of data. The K9GAG08X0M is an optimum solution for large nonvolatile

storage applications such as solid state file storage and other portable applications requiring non-volatility.

3

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

PIN CONFIGURATION (TSOP1)

K9GAG08X0M-PCB0/PIB0

N.C

I/O7

I/O6

I/O5

I/O4

N.C

Vcc

Vss

N.C

I/O3

I/O2

I/O1

I/O0

N.C

R/B

RE

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

CE

9

N.C

Vcc

Vss

N.C

CLE

ALE

WE

WP

N.C

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48-pin TSOP1

Standard Type

12mm x 20mm

PACKAGE DIMENSIONS

48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220AF

Unit :mm/Inch

20.00±0.20

0.787±0.008

#1

#48

#24

#25

1.00±0.05

0.039±0.002

0.05

0.002

MIN

1.20

0.047

MAX

18.40±0.10

0.724±0.004

0~8°

0.45~0.75

0.018~0.030

0.50

0.020

(

)

4

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

PIN CONFIGURATION (ULGA)

K9GAG08U0M-ICB0/IIB0

L

M

C

E

G

H

K

N

A

B

D

J

F

NC

7

6

NC

/RE

NC

Vcc

NC

Vss

IO7

IO1

IO5

Vcc

5

4

3

R/B

/CE

IO6

IO4

NC

IO0

/WE

IO2

Vss

CLE

2

1

Vss

NC

/WP

IO3

Vss

ALE

NC

PACKAGE DIMENSIONS

52-ULGA (measured in millimeters)

Bottom View

Top View

12.00±0.10

A

10.00

2.00

1.00

3

12.00±0.10

7

6

5

4

2

1

B

1.00

(Datum A)

#A1

A

B

C

D

(Datum B)

E

F

G

H

J

K

L

M

N

41-∅

0.70±0.05

12-∅

1.00±0.05

0.1

∅

M C AB

0.1

∅

M C AB

Side View

17.00±0.10

0.10 C

5

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

K9LBG08U1M-ICB0/IIB0

L

M

C

E

G

H

K

N

A

B

D

J

F

NC

7

6

NC

/RE1

/CE2

R/B2

IO7-2

NC

IO6-2

IO7-1

IO6-1

IO5-2

Vcc

/RE2

Vss

IO5-1

Vcc

5

4

3

R/B1

/WE1

/CE1

/WP2

IO4-1

IO4-2

IO3-2

CLE2

ALE2

ALE1

NC

IO0-1

IO2-1

IO1-1 IO3-1

IO0-2

Vss

CLE1

2

1

Vss

/WP1

/WE2

NC

Vss

NC

IO1-2

NC

IO2-2

NC

PACKAGE DIMENSIONS

52-ULGA (measured in millimeters)

Bottom View

Top View

12.00±0.10

A

10.00

2.00

1.00

3

12.00±0.10

7

6

5

4

2

1

B

1.00

(Datum A)

#A1

A

B

C

D

(Datum B)

E

F

G

H

J

K

L

M

N

41-∅

0.70±0.05

12-∅

1.00±0.05

0.1

∅

M C AB

0.1

∅

M C AB

Side View

17.00±0.10

0.10 C

6

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

PIN DESCRIPTION

Pin Name

Pin Function

DATA INPUTS/OUTPUTS

I/O0 ~ I/O7

CLE

The I/O pins are used to input command, address and data, and to output data during read operations. The I/

O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,

commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ADDRESS LATCH ENABLE

ALE

The ALE input controls the activating path for address to the internal address registers. Addresses are

latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and

the device does not return to standby mode in program or erase operation. Regarding CE control during

read operation, refer to ’Page read’ section of Device operation.

CE

READ ENABLE

RE

WE

WP

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE pulse.

WRITE PROTECT

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage

generator is reset when the WP pin is active low.

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or

random read operation is in process and returns to high state upon completion. It is an open drain output and

does not float to high-z condition when the chip is deselected or when outputs are disabled.

R/B

POWER

Vcc

Vss

N.C

VCC is the power supply for device.

GROUND

NO CONNECTION

Lead is not internally connected.

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

7

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Figure 1. K9GAG08X0M Functional Block Diagram

VCC

VSS

16,384M + 512M Bit

NAND Flash

ARRAY

X-Buffers

A13 - A31

Latches

& Decoders

(4,096 + 128)Byte x 524,288

Y-Buffers

Latches

A0 - A12

& Decoders

Data Register & S/A

Y-Gating

Command

Register

VCC

VSS

I/O Buffers & Latches

CE

RE

WE

Control Logic

& High Voltage

Generator

I/0 0

Output

Driver

Global Buffers

I/0 7

CLE ALE

WP

Figure 2. K9GAG08X0M Array Organization

1 Block = 128 Pages

(512K + 16K) Bytes

1 Page = (4K + 128)Bytes

1 Block = (4K + 128)B x 128 Pages

= (512K + 16K) Bytes

1 Device = (4K+128)B x 128Pages x 4,096 Blocks

= 16,896 Mbits

512K Pages

(=4,096 Blocks)

8 bit

4K Bytes

128 Bytes

I/O 0 ~ I/O 7

Page Register

4K Bytes

128 Bytes

I/O 0

A0

I/O 1

A1

I/O 2

I/O 3

A3

I/O 4

A4

I/O 5

A5

I/O 6

A6

I/O 7

A7

Column Address

Row Address

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

5th Cycle

A2

A8

A9

A10

A15

A23

A31

A11

A16

A24

*L

A12

A17

A25

*L

A13

A21

A29

A14

A22

A30

A18

A26

*L

A19

A27

*L

A20

A28

*L

Row Address

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than required.

8

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Product Introduction

The K9GAG08X0M is a 16,896Mbit(17,716,740,096 bit) memory organized as 524,288 rows(pages) by 4,224x8 columns. Spare 128

columns are located from column address of 4,096~4,223. A 4,224-byte data register is connected to memory cell arrays for accom-

modating data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array

is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block

consists of two NAND structured strings. A NAND structure consists of 32 cells. A cell has 2-bit data. Total 2,162,688 NAND cells

reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block

basis. The memory array consists of 4,096 separately erasable 512K-byte blocks. It indicates that the bit by bit erase operation is pro-

hibited on the K9GAG08X0M.

The K9GAG08X0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades

to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by

bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For

example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block

erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 2112M-byte physical space

requires 32 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that

order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-

ation, however, only three row address cycles are used. Device operations are selected by writing specific commands into the com-

mand register. Table 1 defines the specific commands of the K9GAG08X0M.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another

page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and

data-input cycles are removed, system performance for solid-state disk application is significantly increased.

Table 1. Command Sets

Function

1st Set

00h

2nd Set

30h

35h

-

Acceptable Command during Busy

Read

Read for Copy Back

Read ID

00h

90h

Reset

FFh

-

O

Page Program

Copy-Back Program

Block Erase

80h

10h

D0h

-

85h

60h

Random Data Input⁽¹⁾

85h

Random Data Output⁽¹⁾

Read Status

05h

E0h

70h

O

Read Status 2

F1h

Two-Plane Read ⁽³⁾

60h----60h

00h----05h

80h----11h

85h----11h

60h----60h

80h----11h

85h----11h

30h

35h

Two-Plane Read for Copy-Back

Two-Plane Random Data Output ^{(1) (3)}

Two-Plane Page Program⁽²⁾

E0h

81h----10h

D0h

Two-Plane Copy-Back Program⁽²⁾

Two-Plane Block Erase

Page Program with 2KB Data ⁽²⁾

80h----10h

85h----10h

Copy-Back Program with 2KB Data ⁽²⁾

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h and FFh.

3. Two-Plane Random Data out must be used after Two-Plane Read operation

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

9

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

ABSOLUTE MAXIMUM RATINGS

Rating

Unit

2.7V / 3.3V Device

Parameter

Symbol

VCC

VIN

-0.6 to + 4.6

Voltage on any pin relative to VSS

V

-0.6 to + 4.6

-0.6 to Vcc+0.3 (<4.6V)

-10 to +125

VI/O

K9XXG08X0M-XCB0

Temperature Under Bias

TBIAS

°C

K9XXG08X0M-XIB0

-40 to +125

K9XXG08X0M-XCB0

Storage Temperature

TSTG

Ios

-65 to +150

5

°C

K9XXG08X0M-XIB0

Short Circuit Current

mA

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.

Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9XXG08X0M-XCB0 :TA=0 to 70°C, K9GAG08X0M-XIB0:TA=-40 to 85°C)

K9GAG08B0M(2.7V)

K9XXG08UXM(3.3V)

Parameter

Symbol

Unit

Min

2.5

0

Typ.

2.7

0

Max

2.9

0

Min

2.7

0

Typ.

3.3

0

Max

3.6

0

Supply Voltage

VCC

VSS

V

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

K9GAG08X0M

Parameter

Symbol

Test Conditions

2.7V

3.3V

Unit

Min

Typ Max

Min

Typ Max

Page Read with

Serial Access

tRC=25ns

CE=VIL, IOUT=0mA

ICC1

Operating

Current

-

15

30

-

15

30

Program

Erase

ICC2

ICC3

ISB1

ISB2

ILI

-

mA

-

Stand-by Current(TTL)

Stand-by Current(CMOS)

Input Leakage Current

Output Leakage Current

CE=VIH, WP=0V/VCC

CE=VCC-0.2, WP=0V/VCC

VIN=0 to Vcc(max)

VOUT=0 to Vcc(max)

-

10

-

1

-

10

-

1

50

±10

µA

ILO

-

0.8

Vcc

(1)

Input High Voltage

VIH

-

+0.3

xVcc

0.2

(1)

Input Low Voltage, All inputs

Output High Voltage Level

Output Low Voltage Level

Output Low Current(R/B)

-0.3

2.4

-

VIL

xVcc

V

K9GAG08B0M :IOH=-100µA

K9GAG08U0M :IOH=-400µA

VCC

-0.4

VOH

VOL

-

0.4

-

0.4

-

K9GAG08B0M :IOL=100uA

K9GAG08U0M :IOL=2.1mA

-

K9GAG08B0M :VOL=0.1V

K9GAG08U0M :VOL=0.4V

IOL(R/B)

3

4

8

10

mA

NOTE : 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

2. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.

3. The typical value of the K9LBG08U1M’s ISB2 is 20µA and the maximum value is 100µA.

10

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

VALID BLOCK

Parameter

K9GAG08X0M

K9LBG08U1M

Symbol

NVB

Min

Typ.

Max

4,096

8,192

Unit

3,996

7,992

-

Blocks

NVB

NOTE :

1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is

presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits which cause status fail-

ure during program and erase operation. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate

management of initial invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.

3. The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations.

* : Each K9GAG08U0M chip in the K9LBG08U1M has Maximum 100 invalid blocks

AC TEST CONDITION

(K9XXG08X0M-XCB0: TA=0 to 70°C, K9XXG08X0M-XIB0:TA=-40 to 85°C,

K9GAG08B0M: Vcc=2.5V~2.9V, K9XXG08UXM: Vcc=2.7V~3.6V unless otherwise noted)

Parameter

Input Pulse Levels

K9GAG08B0M

K9XXG08UXM

0V to Vcc

Input Rise and Fall Times

Input and Output Timing Levels

Output Load

5ns

Vcc/2

5ns

Vcc/2

1 TTL GATE and CL=30pF

1 TTL GATE and CL=50pF

CAPACITANCE(TA=25°C, VCC=2.7V/3.3V, f=1.0MHz)

Item

Symbol

Test Condition

Min

Max

Unit

pF

CI/O

VIL=0V

-

5

Input/Output Capacitance

CI/O(W)*

CIN

VIL=0V

pF

VIN=0V

pF

Input Capacitance

CIN(W)*

VIN=0V

pF

NOTE :1. Capacitance is periodically sampled and not 100% tested.

2. CI/O(W)* and CIN(W)* are tested at wafer level.

MODE SELECTION

CLE

H

L

ALE

L

CE

L

WE

RE

H

WP

Mode

Command Input

X

Read Mode

Write Mode

H

L

H

X

Address Input(5clock)

Command Input

H

L

H

L

H

Address Input(5clock)

L

H

Data Input

L

H

X

Data Output

X

H

X

During Read(Busy)

During Program(Busy)

During Erase(Busy)

Write Protect

X

H

X

H

L

X⁽¹⁾

X

(2)

X

Stand-by

0V/VCC

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

11

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Program / Erase Characteristics

Parameter

Symbol

tPROG

tDBSY

Nop

Min

Typ

0.8

0.5

-

Max

3

Unit

ms

Program Time

-

Dummy Busy Time for Multi Plane Program

Number of Partial Program Cycles in the Same Page

Block Erase Time

1

µs

-

1

cycle

ms

tBERS

1.5

10

NOTE: 1.Typical program time is measured at Vcc=3.3V, TA=25°C. Not 100% tested.

2. Typical Program time is defined as the time within which more than 50% of the whole pages are programed at 3.3V Vcc and 25°C temperature.

3. Within a same block, program time(tPROG) of page group A is faster than that of page group B. Typical tPROG is the average program time of

the page group A and B(Table 5).

Page Group A: Page 0, 1, 2, 3, 6, 7, 10, 11, ... , 110, 111, 114, 115, 118, 119, 122, 123

Page Group B: Page 4, 5, 8, 9, 12, 13, 16, 17, ... , 116, 117, 120, 121, 124, 125, 126, 127

AC Timing Characteristics for Command / Address / Data Input

Min

Max

Parameter

Symbol

Unit

3.3V(2.7V)

(1)

CLE Setup Time

CLE Hold Time

CE Setup Time

CE Hold Time

12

5

-

ns

tCLS

tCLH

(1)

20

5

tCS

tCH

tWP

WE Pulse Width

ALE Setup Time

ALE Hold Time

Data Setup Time

Data Hold Time

Write Cycle Time

12

5

(1)

tALS

tALH

(1)

12

5

tDS

tDH

tWC

tWH

25

10

100

WE High Hold Time

(2)

Address to Data Loading Time

tADL

NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low.

2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

12

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

AC Characteristics for Operation

Min

Max

Unit

Parameter

Symbol

3.3V(2.7V)

Data Transfer from Cell to Register

ALE to RE Delay

tR

tAR

-

10

20

12

-

60

µs

ns

µs

-

CLE to RE Delay

tCLR

tRR

-

Ready to RE Low

-

RE Pulse Width

tRP

-

WE High to Busy

tWB

100

Read Cycle Time

tRC

25

-

RE Access Time

tREA

tCEA

tRHZ

tCHZ

tCSD

tRHOH

tRLOH

tCOH

tREH

tIR

20

CE Access Time

-

25

RE High to Output Hi-Z

CE High to Output Hi-Z

CE High to ALE or CLE Don’t Care

RE High to Output Hold

RE Low to Output Hold

CE High to Output Hold

RE High Hold Time

-

100

-

30

10

15

5

-

15

10

0

-

Output Hi-Z to RE Low

RE High to WE Low

WE High to RE Low

-

tRHW

tWHR

tRST

100

60

-

5/10/500⁽¹⁾

Device Resetting Time(Read/Program/Erase)

NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.

13

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

NAND Flash Technical Notes

Initial Invalid Block(s)

Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.

The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)

have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)

does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-

sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on

00h block address, is guaranteed to be a valid block at the time of shipment.

Identifying Initial Invalid Block(s)

All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The

initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that the last page of every initial invalid

block has non-FFh data at the column address of 4,096.The initial invalid block information is also erasable in most cases, and it is

impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid

block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow

chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.

Start

Set Block Address = 0

Increment Block Address

Check "FFh" at the column address

4,096 of the last page in the block

*

No

Create (or update)

Check "FFh" ?

Initial

Invalid Block(s) Table

Yes

No

Last Block ?

Yes

End

Figure 3. Flow chart to create initial invalid block table.

14

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

NAND Flash Technical Notes (Continued)

Error in write or read operation

Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual

data. Block replacement should be done upon erase or program error.

Failure Mode

Detection and Countermeasure sequence

Status Read after Erase --> Block Replacement

Status Read after Program --> Block Replacement

Verify ECC -> ECC Correction

Erase Failure

Write

Read

Program Failure

Up to Four Bit Failure

: Error Correcting Code --> RS Code etc.

Example) 4bit correction / 512-byte

ECC

Program Flow Chart

Start

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

No

I/O 6 = 1 ?

or R/B = 1 ?

Yes

*

No

Program Error

I/O 0 = 0 ?

Yes

Program Completed

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

*

15

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

NAND Flash Technical Notes (Continued)

Erase Flow Chart

Read Flow Chart

Start

Write 00h

Start

Write 60h

Write Block Address

Write Address

Write 30h

Write D0h

Read Data

Read Status Register

ECC Generation

No

I/O 6 = 1 ?

or R/B = 1 ?

No

Verify ECC

Reclaim the Error

Yes

*

No

Yes

Erase Error

I/O 0 = 0 ?

Page Read Completed

Yes

Erase Completed

: If erase operation results in an error, map out

the failing block and replace it with another block.

*

Block Replacement

Block A

1st

{

(n-1)th

1

nth

an error occurs.

(page)

Buffer memory of the controller.

Block B

1st

2

{

(n-1)th

nth

(page)

* Step1

When an error happens in the nth page of the Block ’A’ during erase or program operation.

* Step2

Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)

* Step3

Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.

* Step4

Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme.

16

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

NAND Flash Technical Notes (Continued)

Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-

nificant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB

among the pages to be programmed. Therefore, LSB doesn't need to be page 0.

(128)

Page 127

Page 31

Page 127

Page 31

:

(32)

:

(1)

:

(3)

(2)

(1)

Page 2

Page 1

Page 0

(3)

(32)

(2)

Page 2

Page 1

Page 0

Data register

From the LSB page to MSB page

DATA IN: Data (1)

Ex.) Random page program (Prohibition)

DATA IN: Data (1)

Data (128)

17

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

System Interface Using CE don’t-care.

For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 4,224byte

data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or

audio applications which use slow cycle time on the order of µ-seconds, de-activating CE during the data-loading and serial access

would provide significant savings in power consumption.

Figure 4. Program Operation with CE don’t-care.

CLE

CE don’t-care

CE

WE

ALE

I/Ox

Address(5Cycles)

tCS

80h

Data Input

10h

tCH

tCEA

CE

RE

CE

tREA

tWP

WE

out

I/O0~7

Figure 5. Read Operation with CE don’t-care.

CLE

CE

CE don’t-care

RE

ALE

tR

R/B

WE

I/Ox

Data Output(serial access)

00h

Address(5Cycle)

30h

18

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

NOTE

I/O

I/Ox

DATA

ADDRESS

Device

Data In/Out

Col. Add1

Col. Add2

Row Add1

Row Add2

Row Add3

K9GAG08X0M

I/O 0 ~ I/O 7

~4,224byte

A0~A7

A8~A12

A13~A20

A21~A28

A29~A31

Command Latch Cycle

CLE

tCLS

tCS

tCLH

tCH

CE

tWP

WE

tALS

tALH

ALE

I/Ox

tDH

tDS

Command

Address Latch Cycle

CLE

tWC

tCS

CE

tWP

WE

tWH

tALH

tWH

tALH

tWH

tALH

tDH

tALS

ALE

I/Ox

tDH

tDS

Col. Add2

Row Add1

Col. Add1

Row Add2

Row Add3

19

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Input Data Latch Cycle

tCLH

CLE

tCH

CE

tWC

tALS

ALE

tWP

WE

tWH

tDH

tDS

I/Ox

DIN final

DIN 0

DIN 1

* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)

tRC

CE

(1)

tCHZ

tREH

tREA

tCOH

RE

(1)

tRHZ

(2)

tRHOH

I/Ox

Dout

tRR

R/B

NOTES : 1. Transition is measured at ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

2. tRHOH starts to be valid when frequency is lower than 33MHz.

20

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)

CE

(1)

tRC

tCHZ

tCOH

tRP

tREH

RE

(1)

tRHZ

tREA

tCEA

tREA

tRLOH

(2)

tRHOH

I/Ox

R/B

Dout

tRR

NOTES : 1. Transition is measured at ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

2. tRLOH is valid when frequency is higher than 33MHz.

tRHOH starts to be valid when frequency is lower than 33MHz.

Status Read Cycle

tCLR

CLE

CE

tCLS

tCLH

tCS

tCH

tWP

WE

tCEA

tCHZ

tCOH

tWHR

RE

tRHZ

tDH

tREA

tDS

tIR

tRHOH

I/Ox

Status Output

70h/F1h

21

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Read Operation

tCLR

CLE

CE

tWC

WE

ALE

RE

tCSD

tWB

tAR

tRHZ

tR

tRC

tRR

Col. Add2 Row Add1 Row Add2

00h

Col. Add1

30h

Dout N

Dout N+1

Dout M

Row Add3

I/Ox

R/B

Column Address

Row Address

Busy

Read Operation(Intercepted by CE)

tCLR

CLE

CE

tCSD

WE

ALE

RE

tCHZ

tWB

tAR

tCOH

tR

tRC

tRR

Row Add2 Row Add3

Dout N+2

00h

Col. Add1 Col. Add2 Row Add1

30h

Dout N+1

Dout N

I/Ox

R/B

Row Address

Column Address

Busy

22

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

23

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Page Program Operation

CLE

CE

tWC

WE

tPROG

tWHR

tWB

tADL

ALE

RE

Din

N

Din

M

Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3

70h

80h

I/Ox

10h

I/O0

SerialData

Input Command

Program

Command

1 up to m Byte

Serial Input

Read Status

Command

Column Address

Row Address

R/B

I/O

0

=0 Successful Program

=1 Error in Program

I/O0

NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

24

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

≈

≈ ≈

≈

25

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

≈

≈ ≈

≈

26

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Block Erase Operation

CLE

CE

tWC

WE

tBERS

tWB

tWHR

ALE

RE

I/Ox

Row Add1 Row Add2 Row Add3

Row Address

60h

D0h

70h

I/O 0

Busy

R/B

Auto Block Erase

Setup Command

Erase Command

I/O

0

=0 Successful Erase

Read Status I/O

Command

0=1 Error in Erase

27

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

28

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

≈

≈ ≈

≈

≈ ≈

≈

29

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

30

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Read ID Operation

CLE

CE

WE

ALE

tAR

RE

tREA

Device

Code

I/Ox

3rd cyc.

4th cyc.

5th cyc.

00h

ECh

90h

Read ID Command

Maker Code Device Code

Address. 1cycle

Device

Device Code(2nd Cycle)

3rd Cycle

4th Cycle

5th Cycle

K9GAG08B0M

K9GAG08U0M

K9LBG08U1M

Same as K9GAG08U0M

14h

D5h

B6h

74h

Same as K9GAG08U0M in it

31

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

ID Definition Table

90 ID : Access command = 90H

Description

1^stByte

2^ndByte

3^rdByte

4^thByte

5^thByte

Maker Code

Device Code

Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, etc

Page Size, Block Size, Spare Size, Organization, Serial Access Minimum

Plane Number, Plane Size

3rd ID Data

Internal Chip Number

Cell Type

Description

I/O7

I/O6

I/O5 I/O4

I/O3 I/O2

I/O1 I/O0

1

2

4

8

0

1

0

1

0

1

2 Level Cell

4 Level Cell

8 Level Cell

0

1

0

1

0

1

16 Level Cell

1

2

4

8

0

1

0

1

0

1

Number of

Simultaneously

Programmed Pages

Interleave Program

Between multiple chips

Not Support

Support

0

1

Not Support

Support

0

1

Cache Program

4th ID Data

Description

I/O7

I/O6 I/O5 I/O4

I/O3

I/O2

I/O1 I/O0

1KB

2KB

4KB

8KB

0

1

0

1

0

1

Page Size

(w/o redundant area )

64KB

0

1

0

1

0

1

Block Size

(w/o redundant area )

128KB

256KB

512KB

Redundant Area Size

( byte/512byte)

8

16

0

1

x8

x16

0

1

Organization

50ns/30ns

25ns

Reserved

0

1

0

1

0

1

Serial Access Minimum

32

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

5th ID Data

Description

1

I/O7

I/O6 I/O5 I/O4

I/O3 I/O2

I/O1

I/O0

0

1

0

1

0

1

2

4

Plane Number

8

64Mb

128Mb

256Mb

512Mb

1Gb

2Gb

4Gb

8Gb

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Plane Size

(w/o redundant Area)

Reserved

0

33

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Device Operation

PAGE READ

Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command

is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 4,224 bytes of data

within the selected page are transferred to the data registers in less than 60µs(tR). The system controller can detect the completion of

this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read

out in 25ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the

data starting from the selected column address up to the last column address.

The device may output random data in a page instead of the consecutive sequential data by writing random data output command.

The column address of next data, which is going to be out, may be changed to the address which follows random data output com-

mand. Random data output can be operated multiple times regardless of how many times it is done in a page.

Figure 6. Read Operation

CLE

CE

WE

ALE

tR

R/B

RE

I/Ox

00h

Address(5Cycle)

30h

Data Output(Serial Access)

Col. Add.1,2 & Row Add.1,2,3

Data Field

Spare Field

34

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Figure 7. Random Data Output In a Page

tR

R/B

RE

Address

5Cycles

Address

2Cycles

Data Output

30h/35h

E0h

00h

05h

I/Ox

Col Add1,2 & Row Add1,2,3

Data Field

Spare Field

PAGE PROGRAM

The device is programmed basically on a page basis, and the number of consecutive partial page programming operation within the

same page without an intervening erase operation must not exceed 1 time for the page. The addressing should be done in sequential

order in a block. A page program cycle consists of a serial data loading period in which up to 4,224bytes of data may be loaded into

the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.

The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and

then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data

input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random

data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.

The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the

serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-

ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the

Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-

gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset

command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be

checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command

register remains in Read Status command mode until another valid command is written to the command register.

Figure 8. Program & Read Status Operation

tPROG

R/B

"0"

Pass

80h

Address & Data Input

I/O0

Fail

I/Ox

10h

70h

Col Add1,2 & Row Add1,2,3

Data

"1"

35

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Figure 9. Random Data Input In a Page

tPROG

R/B

"0"

Pass

80h

Address & Data Input

I/O0

Fail

85h

10h

70h

I/Ox

Col Add1,2

Data

Col Add1,2 & Row Add1,2,3

Data

"1"

COPY-BACK PROGRAM

Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-

loading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is

improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to

the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with

the destination page address. A read operation with "35h" command and the address of the source page moves the whole 4,224-byte

data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error,

the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command

(85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once

the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system control-

ler can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When

the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10 & Figure 11). The command register

remains in Read Status command mode until another valid command is written to the command register.

During copy-back program, data modification is possible using random data input command (85h) as shown in Figure11.

Figure 10. Page Copy-Back Program Operation

tR

tPROG

R/B

I/Ox

"0"

Data Output

Add.(5Cycles)

Pass

00h

35h

85h

10h

70h

I/O0

Col. Add.1,2 & Row Add.1,2,3

Destination Address

Col. Add.1,2 & Row Add.1,2,3

Source Address

"1"

Fail

Note: 1. Copy-Back Program operation is allowed only within the same memory plane.

Figure 11. Page Copy-Back Program Operation with Random Data Input

tPROG

tR

R/B

Add.(5Cycles)

I/Ox

00h

35h

Data Output

85h Add.(5Cycles)

Add.(2Cycles)

Col. Add.1,2

10h

70h

Data 85h

Data

Col. Add.1,2 & Row Add.1,2,3

Source Address

Col. Add.1,2 & Row Add.1,2,3

Destination Address

There is no limitation for the number of repetition.

36

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

BLOCK ERASE

The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup

command(60h). Only address A20 to A31 is valid while A13 to A19 is ignored. The Erase Confirm command(D0h) following the block

address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that

memory contents are not accidentally erased due to external noise conditions.

At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When

the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.

Figure 12. Block Erase Operation

tBERS

R/B

"0"

Pass

60h

I/O0

Fail

70h

Address Input(3Cycle)

Row Add. : A13 ~ A31

I/Ox

D0h

"1"

TWO-PLANE PAGE READ

Two-Plane Page Read is an extension of Page Read, for a single plane with 4,224 byte page registers. Since the device is equipped

with two memory planes, activating the two sets of 4,224 byte page registers enables a random read of two pages. Two-Plane Page

Read is initiated by repeating command 60h followed by three address cycles twice. In this case only same page of same block can

be selected from each plane.

After Read Confirm command(30h) the 8,448 bytes of data within the selected two page are transferred to the data registers in less

than 60us(tR). The system controller can detect the completion of data transfer(tR) by monitoring the output of R/B pin.

Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h with Five

Address Cycles, command 05h with two column address and finally E0h. The data output of second plane can be read out using the

identical command sequences. The restrictions for Two-Plane Page Program are shown in Figure 13. Two-Plane Read must be

used in the block which has been programmed with Two-Plane Page Program.

Figure 13. Two-Plane Page Read Operation with Two-Plane Random Data Out

tR

R/B

60h

30h

I/OX

60h

Address (3 Cycle)

Row Add.1,2,3

A¹³~ A19 : Valid

A¹³~ A19 : Fixed ’Low’

A²⁰

: Fixed ’Low’

A²⁰

: Fixed ’High’

1

2

A²¹~ A31 : Fixed ’Low’

A²¹~ A31 :Valid

R/B

I/Ox

E0h

Data Output

Address (2 Cycle)

05h

00h

Address (5 Cycle)

Col. Add. 1,2 & Row Add.1,2,3

Col. Add.1,2

A⁰~ A12 : Fixed ’Low’

A¹³~ A19 : Fixed ’Low’

A0 ~ A12 : Valid

1

A²⁰

: Fixed ’Low’

A²¹~ A31 : Fixed ’Low’

R/B

I/Ox

E0h

Data Output

Address (2 Cycle)

05h

00h

Address (5 Cycle)

Col. Add. 1,2 & Row Add.1,2,3

Col. Add.1,2

A0 ~ A12 : Fixed ’Low’

A¹³~ A19 : Fixed ’Low’

A⁰~ A12 : Valid

2

A²⁰

: Fixed ’High’

A²¹~ A31 : Fixed ’Low’

37

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

TWO-PLANE PAGE PROGRAM

Two-Plane Page Program is an extension of Page Program, for a single plane with 4,224 byte page registers. Since the device is

equipped with two memory planes, activating the two sets of 4,224 byte page registers enables a simultaneous programming of two

pages.

After writing the first set of data up to 4,224 byte into the selected page register, Dummy Page Program command (11h) instead of

actual Page Program (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved, R/B

remains in Busy state for a short period of time(tDBSY). Read Status command (70h/F1h) may be issued to find out when the device

returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the

81h command and address sequences. After inputting data for the last plane, actual True Page Program(10h) instead of dummy

Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the

same as that of Page Program. Status bit of I/O 0 is set to "1" when any of the pages fails. Restriction in addressing with Two-Plane

Page Program is shown in Figure14.

Figure 14. Two-Plane Page Program

tDBSY

Note*²

tPROG

R/B

I/O0 ~ 7

70h/F1h

Address & Data Input

80h

11h

81h

10h

A⁰~ A12 : Valid

A¹³~ A19 : Fixed ’Low’

A0 ~ A12 : Valid

A¹³~ A19 : Valid

A²⁰

: Fixed ’Low’

A²⁰

: Fixed ’High’

A²¹~ A31 : Fixed ’Low’

A²¹~ A31 : Valid

NOTE : 1. It is noticeable that physically same row address is applied to two planes ^.

2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.

80h

11h

81h

10h

Data

Input

Plane 0

Plane 1

(2048 Block)

Block 0

Block 2

Block 1

Block 3

Block 4092

Block 4094

Block 4093

Block 4095

38

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

TWO-PLANE COPY-BACK PROGRAM

Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 4224 byte page registers. Since the

device is equipped with two memory planes, activating the two sets of 4224 byte page registers enables a simultaneous program-

ming of two pages.

Figure 15. Two-Plane Copy-Back Program Operation

tR

R/B

60h

35h

I/OX

60h

Address (3 Cycle)

Row Add.1,2,3

A¹³~ A19 : Fixed ’Low’

A¹³~ A19 : Valid

A²⁰

: Fixed ’Low’

A²⁰

: Fixed ’High’

1

2

3

A²¹~ A31 : Fixed ’Low’

A²¹~ A31 : Valid

R/B

I/Ox

E0h

Data Output

Address (2 Cycle)

05h

00h

Address (5 Cycle)

Col. Add. 1,2 & Row Add.1,2,3

Col. Add.1,2

A⁰~ A12 : Fixed ’Low’

A¹³~ A19 : Fixed ’Low’

A²⁰

A⁰~ A12 : Valid

1

: Fixed ’Low’

A²¹~ A31 : Fixed ’Low’

R/B

I/Ox

E0h

Data Output

Address (2 Cycle)

05h

00h

Address (5 Cycle)

Col. Add. 1,2 & Row Add.1,2,3

Col. Add.1,2

A⁰~ A12 : Fixed ’Low’

A¹³~ A19 : Fixed ’Low’

A0 ~ A12 : Valid

2

A²⁰

: Fixed ’High’

A²¹~ A31 : Fixed ’Low’

tPROG

tDBSY

Note3

R/B

I/Ox

Add.(5Cycles)

11h

Add.(5Cycles)

10h

85h

81h

70h

Col. Add.1,2 & Row Add.1,2,3

Destination Address

Col. Add.1,2 & Row Add.1,2,3

Destination Address

3

A0 ~ A12 : Fixed ’Low’

A13 ~ A19 : Fixed ’Low’

A⁰~ A12 : Fixed ’Low’

A13 ~ A19 : Valid

A20

: Fixed ’Low’

A20

: Fixed ’High’

A21 ~ A31 : Fixed ’Low’

A21 ~ A31 : Valid

39

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Plane0

Plane1

Source page

(1) : Two-Plane Read for Copy Back

Target page

(2) : Two-Plane Random Data Out

(3) : Two-Plane Copy-Back Program

(1)

(2)

(3)

(1)

(3)

Data Field

Spare Field

(2)

Note: 1. Copy-Back Program operation is allowed only within the same memory plane.

2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.

40

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Figure 16. Two-Plane Copy-Back Program Operation with Random Data Input

tR

R/B

60h

35h

I/OX

60h

Address (3 Cycle)

Row Add.1,2,3

A13 ~ A19 : Fixed ’Low’

A¹³~ A19 : Valid

A²⁰

: Fixed ’Low’

A²⁰

: Fixed ’High’

1

2

A²¹~ A31 : Fixed ’Low’

A²¹~ A31 : Valid

R/B

I/Ox

E0h

Data Output

Address (2 Cycle)

05h

00h

Address (5 Cycle)

Col. Add. 1,2 & Row Add.1,2,3

Col. Add.1,2

A⁰~ A12 : Fixed ’Low’

A¹³~ A19 : Fixed ’Low’

A⁰~ A12 : Valid

1

A²⁰

: Fixed ’Low’

A²¹~ A31 : Fixed ’Low’

R/B

I/Ox

E0h

Data Output

Address (2 Cycle)

05h

00h

Address (5 Cycle)

Col. Add. 1,2 & Row Add.1,2,3

Col. Add.1,2

3

A⁰~ A12 : Fixed ’Low’

A¹³~ A19 : Fixed ’Low’

A⁰~ A12 : Valid

2

A²⁰

: Fixed ’High’

A²¹~ A31 : Fixed ’Low’

tDBSY

R/B

I/Ox

Add.(5Cycles)

11h

Data

85h

Data

Add.(2Cycles)

Col. Add.1,2

85h

Note3

Col. Add.1,2 & Row Add.1,2,3

Destination Address

4

3

A0 ~ A12 : Valid

A¹³~ A19 : Fixed ’Low’

A²⁰

: Fixed ’Low’

A²¹~ A31 : Fixed ’Low’

tPROG

R/B

I/Ox

Add.(5Cycles)

10h

Data

85h

Data

Add.(2Cycles)

Col. Add.1,2

81h

Col. Add.1,2 & Row Add.1,2,3

Destination Address

4

A0 ~ A12 : Valid

A13 ~ A19 : Valid

A20

: Fixed ’High’

A21 ~ A31 : Valid

Note: 1. Copy-Back Program operation is allowed only within the same memory plane.

2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.

41

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

TWO-PLANE BLOCK ERASE

Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each

plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by

three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane.

The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/

Busy status bit (I/O 6).

Figure 17. Two-Plane Erase Operation

tBERS

R/B

"0"

60h

D0h

70h

Pass

I/OX

60h

Address (3 Cycle)

I/O0

A¹³~ A19 : Fixed ’Low’

"1"

Fail

A²⁰

: Fixed ’Low’

A²⁰

: Fixed ’High’

A²¹~ A31 : Fixed ’Low’

A²¹~ A31 : Valid

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether

the program or erase operation is completed successfully. After writing 70h or F1h command to the command register, a read cycle

outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control

allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or

CE does not need to be toggled for updated status. Refer to table 2 for specific 70h Status Register definitions and table 3 for specific

F1h Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. There-

fore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles.

Table 2. 70h Read Status Register Definition

I/O No.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

Page Program

Pass/Fail

Not use

Block Erase

Pass/Fail

Not use

Read

Not use

Definition

Fail : "1"

Pass : "0"

Not use

Don’t -cared

Busy : "0"

Not use

Not Use

Ready/Busy

Write Protect

Ready/Busy

Write Protect

Ready/Busy

Write Protect

Ready : "1"

Protected : "0"

Not Protected : "1"

NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.

Table 3. F1h Read Status Register Definition

I/O No.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

Page Program

Chip Pass/Fail

Plane0 Pass/Fail

Plane1 Pass/Fail

Not Use

Block Erase

Chip Pass/Fail

Plane0 Pass/Fail

Plane1 Pass/Fail

Not Use

Read

Not use

Definition

Pass : "0"

Fail : "1"

Not use

Pass : "0"

Not use

Pass : "0"

Not Use

Don’t -cared

Busy : "0"

Not Use

Ready/Busy

Write Protect

Ready/Busy

Write Protect

Ready/Busy

Write Protect

Ready : "1"

Protected : "0"

Not Protected : "1"

NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.

42

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of

00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd cycle ID, 4th cycle ID, 5th cycle

respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation

sequence.

Figure 18. Read ID Operation

tCLR

CLE

CE

tCEA

WE

ALE

RE

tAR

tWHR

Device

Code

tREA

I/OX

90h

00h

Address. 1cycle

ECh

3rd Cyc.

4th Cyc.

5th Cyc.

Maker code

Device code

Device

Device Code(2nd Cycle)

3rd Cycle

4th Cycle

5th Cycle

K9GAG08B0M

K9GAG08U0M

K9LBG08U1M

Same as K9GAG08U0M

14h

D5h

B6h

74h

Same as K9GAG08U0M in it

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random

read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no

longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and

the Status Register is cleared to value C0h when WP is high. Refer to Table 4 for device status after reset operation. If the device is

already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the

Reset command is written. Refer to Figure 19 below.

Figure 19. RESET Operation

tRST

R/B

I/OX

FFh

Table 4. Device Status

After Power-up

After Reset

Operation mode

00h Command is latched

Waiting for next command

43

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Table 5. Paired Page Address Information

Paired Page Address

00h

02h

06h

0Ah

0Eh

12h

16h

1Ah

1Eh

22h

26h

2Ah

2Eh

32h

36h

3Ah

3Eh

42h

46h

4Ah

4Eh

52h

56h

5Ah

5Eh

62h

66h

6Ah

6Eh

72h

76h

7Ah

04h

08h

0Ch

10h

14h

18h

1Ch

20h

24h

28h

2Ch

30h

34h

38h

3Ch

40h

44h

48h

4Ch

50h

54h

58h

5Ch

60h

64h

68h

6Ch

70h

74h

78h

7Ch

7Eh

01h

03h

07h

0Bh

0Fh

13h

17h

1Bh

1Fh

23h

27h

2Bh

2Fh

33h

37h

3Bh

3Fh

43h

47h

4Bh

4Fh

53h

57h

5Bh

5Fh

63h

67h

6Bh

6Fh

73h

77h

7Bh

05h

09h

0Dh

11h

15h

19h

1Dh

21h

25h

29h

2Dh

31h

35h

39h

3Dh

41h

45h

49h

4Dh

51h

55h

59h

5Dh

61h

65h

69h

6Dh

71h

75h

79h

7Dh

7Fh

Note: When program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also

paired page data may be damaged(Table 5).

44

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random

read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-

ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is

an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and

current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 20). Its value can be

determined by the following guidance.

Rp

ibusy

VCC

Ready Vcc

2.7V device - VOL : 0.4V, VOH : Vcc-0.4V

3.3V device - VOL : 0.4V, VOH : 2.4V

R/B

VOH

open drain output

C_L

VOL

Busy

tf

tr

GND

Device

45

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Figure 20. Rp vs tr ,tf & Rp vs ibusy

@ Vcc = 2.7V, Ta = 25°C , C_L= 30pF

2.3

Ibusy

200n

100n

2m

1m

1.1

60

120

90

tr

0.55

2.3

0.75

2.3

30

2.3

2K

2.3

tf

4K

1K

3K

Rp(ohm)

@ Vcc = 3.3V, Ta = 25°C , C_L= 50pF

2.4

200

Ibusy

200n

100n

2m

1m

150

0.8

1.2

100

tr

tf

0.6

3.6

50

3.6

2K

3.6

3K

3.6

4K

1K

Rp(ohm)

Rp value guidance

VCC(Max.) - VOL(Max.)

2.5V

Rp(min, 2.7V part) =

Rp(min, 3.3V part) =

=

IOL + ΣIL

3mA + ΣIL

VCC(Max.) - VOL(Max.)

3.2V

IOL + ΣIL

8mA + ΣIL

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp(max) is determined by maximum permissible limit of tr

46

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

DATA PROTECTION & POWER UP SEQUENCE

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector

disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL

during power-up and power-down. A recovery time of minimum 10µs is required before internal circuit gets ready for any command

sequences as shown in Figure 21. The two step command sequence for program/erase provides additional software protection.

Figure 21. AC Waveforms for Power Transition

2.7V device : ~ 2.0V

3.3V device : ~ 2.5V

2.7V device : ~ 2.0V

3.3V device : ~ 2.5V

VCC

High

WP

WE

10µs

47

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

2KB PROGRAM OPERATION TIMING GUIDE

K9GAG08X0M is designed also to support the program operation with 2KByte data to offer the backward compatibility to the control-

ler which uses the NAND with 2KByte page. The command sequences are as follows.

Figure A-1. (2KB X 2) Program Operation

tDBSY

tPROG

R/B

80h

11h

80h

Address & Data Input

10h

70h

I/O0~7

Address & Data Input

Note

Col Add1,2 & Row Add 1,2,3

2112 Byte Data

Col Add1,2 & Row Add 1,2,3

2112 Byte Data

A⁰~ A12 : Valid

A¹³~ A19 : Fixed ’Low’

A⁰~ A12 : Valid

A¹³~ A19 : Vaild

A²⁰

: Valid

A²⁰

: Must be same with the previous

A²¹~ A31 : Fixed ’Low’

A²¹~ A31 : Valid

Note: Any command between 11h and 81h is prohibited except 70h/F1h and FFh.

Figure A-2. (2KB X 2) Copy-Back Program Operation

tR

R/B

Add.(5Cycles)

Data Output

00h

35h

I/Ox

Col. Add.1,2 & Row Add.1,2,3

Source Address

1

tDBSY

tPROG

R/B

I/Ox

Add.(5Cycles)

11h

10h

85h

Data

Add.(5Cycles)

Data

85h

Col. Add.1,2 & Row Add.1,2,3

Destination Address

Col. Add.1,2 & Row Add.1,2,3

Destination Address

1

A⁰~ A12 : Valid

A13 ~ A19 : Valid

A0 ~ A12 : Valid

A¹³~ A19 : Fixed ’Low’

A20

: Must be same with the previous

A²⁰

: Valid

A21 ~ A31 : Valid

A²¹~ A31 : Fixed ’Low’

Note: 1. Copy-Back Program operation is allowed only within the same memory plane.

2. Any command between 11h and 85h is prohibited except 70h/F1h and FFh.

48

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

Figure A-3. (2KB X 2) Copy-Back Program Operation with Random Data Input

tR

R/B

Add.(5Cycles)

Data Output

00h

35h

I/Ox

Col. Add.1,2 & Row Add.1,2,3

Source Address

1

tDBSY

R/B

I/Ox

Add.(5Cycles)

11h

Data

85h

Data

Add.(2Cycles)

Col. Add.1,2

85h

Note3

Col. Add.1,2 & Row Add.1,2,3

Destination Address

2

1

A0 ~ A12 : Valid

A¹³~ A19 : Fixed ’Low’

A²⁰

: Valid

A²¹~ A31 : Fixed ’Low’

tPROG

R/B

Add.(5Cycles)

10h

Data

85h

Data

Add.(2Cycles)

Col. Add.1,2

I/Ox

85h

Col. Add.1,2 & Row Add.1,2,3

Destination Address

2

A⁰~ A12 : Valid

A¹³~ A19 : Valid

A²⁰

: Must be same with the previous

A²¹~ A31 : Valid

Note: 1. Copy-Back Program operation is allowed only within the same memory plane.

2. Any command between 11h and 85h is prohibited except 70h/F1h and FFh.

49

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

TWO-PLANE PAGE PROGRAM OPERATION USING 4KB BUFFER RAM

K9GAG08X0M consists of 4KB pages and can support Two-Plane program operation. The internal RAM requirement for a controller

is 8KB, but for those controllers which support less than 8KB RAM, the following sequence can be used for Two-Plane program oper-

ation.

Plane0

Plane1

(1) : Two-Plane Read for Copy Back

(2) : Random Data Out On Plane 0 (Up to 4224Byte)

(3) : Random Data In On Plane 0 (Up to 4224Byte)

(4) : Random Data Out On Plane 1 (Up to 4224Byte)

(5) : Random Data In On Plane 1 (Up to 4224Byte)

(6): Two-Plane Program for Copy Back

Source page

Target page

(1)

(6)

(1)

(6)

4KByte

Data Field

(2)

Data Field

(4)

Spare Field

(5)

(3)

Figure A-4. 2-Plane Copy-Back Program Operation with Random Data Input

tR

R/B

Add(3 Cycle)

I/OX

60h

35h

Add(5 Cycle)

Add(2 Cycle)

00h

05h

E0h

DOUT

Row Add.1,2,3

A¹³~ A19 : Valid

Col. Add. 1,2 & Row Add.1,2,3

Col. Add.1,2

Up to 4224Byte

A¹³~ A19 : Fixed ’Low’

A²⁰: Fixed ’Low’

A²¹~ A31 : Fixed ’Low’

A⁰~ A12 : Valid

A⁰~ A12 : Fixed ’Low’

A¹³~ A19 : Fixed ’Low’

A²⁰

: Fixed ’High’

1

A²¹~ A31 : Valid

A20

: Fixed ’Low’

A²¹~ A31 : Fixed ’Low’

tDBSY

R/B

I/Ox

Add(5 Cycle)

Add(2 Cycle)

00h

05h

E0h

DOUT

Up to 4224Byte

2

Add(5 Cycle)

Add(2 Cycle)

Col. Add.1,2

85h

DIN

85h

DIN

11h

Col. Add.1,2 & Row Add.1,2,3

Col. Add. 1,2 & Row Add.1,2,3

Col. Add.1,2

Destination Address

A0 ~ A12 : Valid

A⁰~ A12 : Valid

A⁰~ A12 : Fixed ’Low’

A¹³~ A19 : Fixed ’Low’

1

A13 ~ A19 : Fixed ’Low’

A²⁰

: Fixed ’High’

A²⁰

: Fixed ’Low’

A²¹~ A31 : Fixed ’Low’

tPROG

R/B

I/Ox

Add(5 Cycle)

Add(2 Cycle)

Col. Add.1,2

70h/F1h

81h

DIN

85h

DIN

10h

Col. Add.1,2 & Row Add.1,2,3

Destination Address

2

A0 ~ A12 : Valid

A13 ~ A19 : Valid

A20

: Fixed ’High’

A21 ~ A31 : Valid

Note: 1. Copy-Back Program operation is allowed only within the same memory plane.

50

Preliminary

FLASH MEMORY

K9GAG08B0M

K9GAG08U0M K9LBG08U1M

WP AC TIMING GUIDE

Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows:

Figure B-1. Program Operation

1. Enable Mode

WE

I/O

80h

10h

WP

R/B

tww(min.100ns)

2. Disable Mode

WE

I/O

80h

10h

WP

R/B

tww(min.100ns)

Figure B-2. Erase Operation

1. Enable Mode

WE

I/O

60h

D0h

WP

R/B

tww(min.100ns)

2. Disable Mode

WE

I/O

60h

D0h

WP

R/B

tww(min.100ns)

51


型号：	K9GAG08B0M-P
厂家：	SAMSUNG
描述：	2G x 8 Bit NAND Flash Memory
文件：	总51页 (文件大小：1364K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K9GAG08B0M-P [SAMSUNG]

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