K9K1G08Q0A-YIB0 [SAMSUNG]
Flash, 128MX8, 30ns, PDSO48,;
| 型号： | K9K1G08Q0A-YIB0 |
| 厂家： | 
SAMSUNG |
| 描述： | Flash, 128MX8, 30ns, PDSO48, 光电二极管 内存集成电路 |
| 文件： | 总43页 (文件大小：674K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Document Title
128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial issue.
Mar. 17th 2003 Preliminary
0.1
1. Note is added.
Jun. 4th 2003
Preliminary
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
2. 63FBGA,1.8V product is added.
K9K1GXXQ0A-GCB0,GIB0,JCB0,JIB0
Aug. 1st 2003
Errata is deleted.
AC parameters are changed.
Preliminary
0.2
tWC tWH tWP tRC tREH tRP tREA tCEA
Before 45 15 25 50 15 25 30
After 60 20 40 60 20 40 40
45
55
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
PRODUCT LIST
Part Number
Vcc Range
Organization
PKG Type
K9K1G08Q0A-G,J
K9K1G16Q0A-G,J
K9K1G08U0A-Y,P
K9K1G08U0A-G,J
K9K1G08U0A-V,F
K9K1G16U0A-Y,P
K9K1G16U0A-G,J
X8
1.70 ~ 1.95V
FBGA
X16
TSOP1
FBGA
X8
2.7 ~ 3.6V
WSOP1
TSOP1
FBGA
X16
FEATURES
· Voltage Supply
· Fast Write Cycle Time
- 1.8V device(K9K1GXXQ0A) : 1.70~1.95V
- 3.3V device(K9K1GXXU0A) : 2.7 ~ 3.6 V
· Organization
- Program time : 200ms(Typ.)
- Block Erase Time : 2ms(Typ.)
· Command/Address/Data Multiplexed I/O Port
· Hardware Data Protection
- Memory Cell Array
- X8 device(K9K1G08X0A) : (128M + 4096K)bit x 8 bit
- X16 device(K9K1G16X0A) : (64M + 2048K)bit x 16bit
- Data Register
- Program/Erase Lockout During Power Transitions
· Reliable CMOS Floating-Gate Technology
- Endurance
: 100K Program/Erase Cycles
- X8 device(K9K1G08X0A) : (512 + 16)bit x 8bit
- X16 device(K9K1G16X0A) : (256 + 8)bit x16bit
· Automatic Program and Erase
- Data Retention : 10 Years
· Command Register Operation
· Intelligent Copy-Back
- Page Program
· Unique ID for Copyright Protection
· Package
- K9K1GXXU0A-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9K1GXXX0A-GCB0/GIB0
63- Ball FBGA
- X8 device(K9K1G08X0A) : (512 + 16)Byte
- X16 device(K9K1G16X0A) : (256 + 8)Word
- Block Erase :
- X8 device(K9K1G08X0A) : (16K + 512)Byte
- X16 device(K9K1G16X0A) : ( 8K + 256)Word
· Page Read Operation
- K9K1G08U0A-VCB0/VIB0
- Page Size
- X8 device(K9K1G08X0A) : (512 + 16)Byte
- X16 device(K9K1G16X0A) : (256 + 8)Word
48 - Pin WSOP I (12X17X0.7mm)
- K9K1GXXU0A-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - Pb-free Package
- K9K1GXXX0A-JCB0/JIB0
- Random Access
: 12ms(Max.)
- Serial Page Access : 50ns(Min.)*
* K9F12XXQ0A : 60ns(Min.)
63- Ball FBGA - Pb-free Package
- K9K1G08U0A-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9K1G08U0A-V,F(WSOPI ) is the same device as
K9K1G08U0A-Y,P(TSOP1) except package type.
GENERAL DESCRIPTION
The K9K1G08U0A is a 128M(134,217,728)x8bit NAND Flash Memory with a spare 4.096K(4,194,304)x8bit. Its NAND cell provides
the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typically 200ms on
the 528-byte(x8 device) or 264-word(x16 device) page and an erase operation can be performed in typically 2ms on a 16K-byte(x8
device) or 8K-word(x16 device) block. Data in the data register can be read out at 50ns(1.8V device : 60ns) cycle time per byte(X8
device) or word(X16 device).. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-
chip write controller automates all program and erase functions including pulse repetition, where required, and internal verify and mar-
gining of data. Even the write-intensive systems can take advantage of the K9K1G08U0A¢s extended reliability of 100K program/
erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K1G08U0A is an optimum solu-
tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
2
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
PIN CONFIGURATION (TSOP1)
K9K1G08U0A-YCB0,PCB0/YIB0,PIB0
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
CE
9
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1
#48
#24
#25
1.00±0.05
0.039±0.002
0.05
0.002
MIN
1.20
0.047
MAX
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
0.50
0.020
(
)
3
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
PIN CONFIGURATION (FBGA)
K9K1GXXX0A-GCB0,JCB0/GIB0,JIB0
X8
X16
1
2
3
4
5
6
1
2
3
4
5
6
N.C N.C
N.C
N.C N.C
N.C N.C
N.C N.C
N.C
N.C N.C
N.C N.C
A
B
A
B
/WP ALE Vss /CE /WE R/B
/WP ALE Vss /CE /WE R/B
NC
NC
NC
NC
/RE CLE NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
/RE CLE NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C
D
E
C
D
E
NC
NC
NC
NC NC
NC NC
NC
NC
NC
NC NC
NC NC
NC NC
NC I/O5 I/O7 NC
Vcc
F
F
I/O8 I/O1 I/O10 I/O12 IO14
NC I/O0 NC
NC
NC
Vcc
G
H
G
H
I/O0 I/O9 I/O3 VccQ I/O6 I/O15
Vss I/O2 I/O11 I/O4 I/O13 Vss
I/O1 NC VccQ I/O5 I/O7
Vss I/O2 I/O3 I/O4 I/O6 Vss
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
Top View
Top View
4
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
PACKAGE DIMENSIONS
63-Ball FBGA (measured in millimeters)
Top View
Bottom View
Side View
A1 INDEX MARK
8.50±0.10
A
0.10 MAX
0.80x9=7.20
8.50±0.10
B
10
9 8 7 6 5 4 3 2 1
(Datum A)
#A1
0.80
A
B
C
D
E
F
(Datum B)
G
H
J
K
L
M
0.32±0.05
1.10±0.10
3.60
63-Æ 0.45±0.05
Æ
0.20 M A B
5
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
PIN CONFIGURATION (WSOP1)
K9K1G08U0A-VCB0,FCB0/VIB0,FIB0
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
CE
DNU
N.C
Vcc
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vss
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
N.C
DNU
CLE
ALE
WE
WP
N.C
N.C
DNU
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
Unit :mm
48 - WSOP1 - 1217F
0.70 MAX
0.58±0.04
15.40±0.10
#1
#48
#24
#25
(0.1Min)
0.45~0.75
17.00±0.20
6
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Figure 1-1. Functional Block Diagram
VCC
VSS
X-Buffers
A9 - A26
Latches
1,024M + 32M Bit
NAND Flash
ARRAY
& Decoders
Y-Buffers
A0 - A7
Latches
& Decoders
(512 + 16)Byte x 262,144
Page Register & S/A
Y-Gating
A8
Command
Command
Register
VCC
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 7
CLE ALE
WP
Figure 2-1. Array Organization
1 Block = 32 Pages
(16K + 512) Byte
1 Page = 528 Bytes
1 Block = 528 B x 32 Pages
= (16K + 512) Bytes
1 Device = 528B x 32Pages x 8,192 Blocks
= 1,056 Mbits
256K Pages
(=8,192 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
8 bit
512B Bytes
16 Bytes
16 Bytes
I/O 0 ~ I/O 7
Page Register
512 Bytes
I/O 0
A0
I/O 1
A1
I/O 2
A2
I/O 3
A3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
1st Cycle
Column Address
Row Address
(Page Address)
2nd Cycle
3rd Cycle
4th Cycle
A9
A10
A18
A26
A11
A19
*L
A12
A20
*L
A13
A21
*L
A14
A22
*L
A15
A23
*L
A16
A24
*L
A17
A25
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
7
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Figure 1-2. K9K1G16X0A (X16) FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
X-Buffers
A9 - A25
Latches
512M + 16M Bit
NAND Flash
ARRAY
& Decoders
Y-Buffers
Latches
A0 - A7
& Decoders
(256 + 8)Word x 262144
Page Register & S/A
Y-Gating
Command
Command
Register
VCC/VccQ
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 15
CLE ALE
WP
Figure 2-2. K9K1G16X0A (X16) ARRAY ORGANIZATION
1 Block =32 Pages
= (8K + 256) Word
1 Page = 264 Word
1 Block = 264 Word x 32 Pages
= (8K + 256) Word
1 Device = 264Words x 32Pages x 8192 Blocks
= 1056 Mbits
256K Pages
(=8192 Blocks)
Page Register
(=256 Words)
16 bit
256Word
8 Word
8 Word
I/O 0 ~ I/O 15
Page Register
256 Word
I/O 0
A0
I/O 1
A1
I/O 2
A2
I/O 3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
I/O8 to 15
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
A3
A12
A20
L*
L*
L*
L*
L*
Column Address
Row Address
(Page Address)
A9
A10
A18
A26
A11
A19
L*
A13
A21
L*
A14
A22
L*
A15
A23
L*
A16
A24
L*
A17
A25
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
8
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Product Introduction
The K9K1G08U0A is a 1,026Mbit(1,107,296,436 bit) memory organized as 262,144 rows(pages) by 528 columns. Spare sixteen col-
umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two
NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is
shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block
basis. The memory array consists of 8,192 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is pro-
hibited on the K9K1G08U0A.
The K9K1G08U0A has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 128M byte physical space requires
27 addresses(X8 device) or 26 addresses(X16 device), thereby requiring four cycles for byte-level addressing: column address, low
row address and high row address, in that order. Page Read and Page Program need the same four address cycles following the
required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are
selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K1G08U0A.
The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into eight 128Mbit
separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining
the conventional 512 byte structure.
The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of
selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
of the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burst-
reading and data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
Function
1st. Cycle
00h/01h(1)
50h
2nd. Cycle
3rd. Cycle
Acceptable Command during Busy
Read 1
Read 2
Read ID
Reset
-
-
-
-
90h
-
-
FFh
-
-
O
Page Program (True)(2)
Page Program (Dummy)(2)
Copy-Back Program(True)(2)
Copy-Back Program(Dummy)(2)
Block Erase
80h
10h
11h
8Ah
8Ah
D0h
D0h
-
-
80h
-
00h
10h
00h
10h
60h
-
-
-
-
Multi-Plane Block Erase
Read Status
60h---60h
70h
O
O
71h(3)
Read Multi-Plane Status
-
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation.
Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation.
3. The 71h command should be used for read status of Multi Plane operation.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
9
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Memory Map
The device is arranged in eight 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows
it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is
configured so that multi-plane program/erase operations can be executed for every four sequential blocks by dividing the memory
array into plane 0~3 or plane 4~7 separately. For example, multi-plane program/erase operations into plane 2,3,4 and 5 are prohib-
ited.
Figure 3. Memory Array Map
Plane 3
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Plane 0
(1024 Block)
Block 0
Block 2
Block 3
Block 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Block 4092
Block 4094
Block 4095
Block 4093
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
Plane 7
(1024 Block)
Plane 6
(1024 Block)
Plane 5
(1024 Block)
Plane 4
(1024 Block)
Block 4096
Block 4098
Block 4099
Block 4097
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Block 8188
Block 8190
Block 8191
Block 8189
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
10
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
PIN DESCRIPTION
Pin Name
Pin Function
DATA INPUTS/OUTPUTS
I/O0 ~ I/O7
(K9K1G08X0A)
I/O0 ~ I/O15
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
(K9K1G16X0A)
COMMAND LATCH ENABLE
CLE
ALE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation .
CE
READ ENABLE
RE
WE
WP
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
R/B
OUTPUT BUFFER POWER
VccQ
VccQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
POWER
Vcc
Vss
N.C
VCC is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
DO NOT USE
Leave it disconnected.
DNU
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
11
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
ABSOLUTE MAXIMUM RATINGS
Rating
K9K1GXXQ0A(1.8V) K9K1GXXU0A(3.3V)
Parameter
Symbol
Unit
V
VIN/OUT
VCC
-0.6 to + 2.45
-0.2 to + 2.45
-0.2 to + 2.45
-0.6 to + 4.6
-0.6 to + 4.6
-0.6 to + 4.6
Voltage on any pin relative to VSS
VCCQ
K9K1GXXX0A-XCB0
Temperature Under Bias
-10 to +125
TBIAS
°C
K9K1GXXX0A-XIB0
-40 to +125
-65 to +150
5
K9K1GXXX0A-XCB0
Storage Temperature
TSTG
Ios
°C
K9K1GXXX0A-XIB0
Short Circuit Current
mA
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9K1GXXX0A-XCB0 :TA=0 to 70°C, K9K1GXXX0A-XIB0 :TA=-40 to 85°C)
K9K1GXXQ0A(1.8V)
K9K1GXXU0A(3.3V)
Parameter
Symbol
Unit
Min
1.70
1.70
0
Typ.
1.8
1.8
0
Max
1.95
1.95
0
Min
2.7
2.7
0
Typ.
3.3
3.3
0
Max
3.6
3.6
0
Supply Voltage
Supply Voltage
Supply Voltage
VCC
VCCQ
VSS
V
V
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
K9K1GXXQ0A(1.8V)
K9K1GXXU0A(3.3V)
Unit
Parameter
Symbol
Test Conditions
Min
Typ
Max
Min Typ
Max
tRC=50ns, CE=VIL
IOUT=0mA
Operat-
ing
Sequential Read
ICC1
-
10
20
-
15
30
Current Program
ICC2
ICC3
ISB1
ISB2
ILI
-
-
-
-
-
-
-
10
10
-
20
20
-
-
-
-
-
-
15
15
-
30
30
mA
Erase
-
Stand-by Current(TTL)
Stand-by Current(CMOS)
Input Leakage Current
Output Leakage Current
CE=VIH, WP=0V/VCC
CE=VCC-0.2, WP=0V/VCC
VIN=0 to Vcc(max)
VOUT=0 to Vcc(max)
1
1
20
-
100
±20
±20
20
-
100
±20
±20
mA
ILO
-
-
VCCQ
I/O pins
VCCQ-0.4
-
2.0
-
VCCQ+0.3
+0.3
Input High Voltage
VIH*
VCC
Except I/O pins
-
VCC-0.4
-0.3
-
-
-
2.0
-0.3
2.4
-
-
-
VCC+0.3
+0.3
V
Input Low Voltage, All inputs
Output High Voltage Level
VIL*
0.4
0.8
-
K9K1GXXQ0A :IOH=100mA
K9K1GXXU0A :IOH=400mA
VOH
VccQ-0.1
-
K9K1GXXQ0A :IOL=100uA
K9K1GXXU0A :IOL=2.1mA
Output Low Voltage Level
Output Low Current(R/B)
VOL
-
-
0.1
-
-
-
0.4
-
K9K1GXXQ0A :VOL=0.1V
K9K1GXXU0A :VOL=0.4V
IOL(R/B)
3
4
8
10
mA
NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less
12
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Valid Block
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
8,042
-
8,192
Blocks
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access
these invalid blocks for program and erase. Refer to the attached technical notes for an appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC TEST CONDITION
(K9K1GXXX0A-XCB0 :TA=0 to 70°C, K9K1GXXX0A-XIB0 :TA=-40 to 85°C
K9K1GXXQ0A : Vcc=1.70V~1.95V , K9K1GXXU0A : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9K1GXXQ0A
0V to VccQ
5ns
K9K1GXXU0A
0.4V to 2.4V
5ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
VccQ/2
1.5V
K9K1GXXQ0A:Output Load (VccQ:1.8V +/-10%)
K9K1GXXU0A:Output Load (VccQ:3.0V +/-10%)
1 TTL GATE and CL=30pF
-
1 TTL GATE and CL=50pF
1 TTL GATE and CL=100pF
K9K1GXXU0A:Output Load (VccQ:3.3V +/-10%)
Capacitance(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
20
Unit
pF
Input/Output Capacitance
Input Capacitance
CI/O
VIL=0V
-
-
CIN
VIN=0V
20
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
GND
WP
X
Mode
Command Input
X
X
X
X
L
Read Mode
Write Mode
H
L
L
H
X
Address Input(4clock)
Command Input
H
L
L
H
H
H
L
L
H
H
Address Input(4clock)
L
L
H
H
Data Input
L
L
L
H
H
L
X
Data Output
L
L
L
H
H
L
X
During Read(Busy) on K9K1G08U0A_Y,P or K9K1G08U0A_V,F
During Read(Busy) on the devices except K9K1G08U0A_Y,P and
K9K1G08U0A_V,F
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
L
X
H
H
During Program(Busy)
During Erase(Busy)
Write Protect
X(1)
X
X
L
0V
0V/
Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
500
10
1
Unit
ms
Program Time
tPROG
tDBSY
-
200
Dummy Busy Time for Multi Plane Program
1
-
ms
Main Array
-
-
-
cycle
cycles
ms
Number of Partial Program Cycles
in the Same Page
Nop
Spare Array
-
2
Block Erase Time
tBERS
2
3
13
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
AC Timing Characteristics for Command / Address / Data Input
Min
Max
Parameter
Symbol
Unit
K9K1GXXQ0A
K9K1GXXU0A
K9K1GXXQ0A
K9K1GXXU0A
CLE Set-up Time
CLE Hold Time
CE Setup Time
CE Hold Time
tCLS
tCLH
tCS
0
0
10
0
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
0
.-
-
.-
-
tCH
10
40
0
10
25(1)
0
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
tWP
tALS
tALH
tDS
-
-
-
-
10
20
10
60
20
10
20
10
45
15
-
-
-
-
tDH
-
-
tWC
tWH
-
-
-
-
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Min
Max
Parameter
Symbol
Unit
K9K1GXXQ0A K9K1GXXU0A K9K1GXXQ0A K9K1GXXU0A
Data Transfer from Cell to Register
ALE to RE Delay
tR
-
10
10
20
40
-
-
10
10
20
25
-
12
12
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tAR
-
-
CLE to RE Delay
tCLR
tRR
-
-
Ready to RE Low
-
-
RE Pulse Width
tRP
-
-
WE High to Busy
tWB
tRC
100
100
Read Cycle Time
60
-
50
-
-
-
RE Access Time
tREA
tCEA
tRHZ
tCHZ
tOH
40
30
CE Access Time
-
-
55
45
RE High to Output Hi-Z
CE High to Output Hi-Z
RE or CE High to Output hold
RE High Hold Time
-
-
30
30
-
-
20
20
15
20
0
15
15
0
-
-
tREH
tIR
-
-
Output Hi-Z to RE Low
WE High to RE Low
-
-
tWHR
tRST
60
-
60
-
-
-
5/10/500(1)
5/10/500(1)
Device Resetting Time(Read/Program/Erase)
Parameter
Symbol
tRB
Min
Max
Unit
ns
Last RE High to Busy(at sequential read)
-
-
100
K9K1G08U0A-
Y,P only
50 +tr(R/B)(3)
-
CE High to Ready(in case of interception by CE at read)
CE High Hold Time(at the last serial read)(2)
tCRY
ns
tCEH
100
ns
NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
14
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guar-
anteed to be a valid block, does not require Error Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte(X8 device) or 1st word(X16 device) in the spare area. Samsung makes sure that either the
1st or 2nd page of every invalid block has non-FFh(X8 device) or non-FFFFh(X16 device) data at the column address of 517(X8
device) or 256 and 261(X16 device). Since the invalid block information is also erasable in most cases, it is impossible to recover the
information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original
invalid block information and create the invalid block table via the following suggested flow chart(Figure 4). Any intentional erasure of
the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFh" at the column address 512
*
of the 1st and 2nd page in the block
No
Create (or update)
Invalid Block(s) Table
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 4. Flow chart to create invalid block table.
15
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of mem-
ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Write
Read
Program Failure
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 80h
Write 00h
Write Address
Wait for tR Time
Write Address
Write Data
Write 10h
*
No
Program Error
Verify Data
Read Status Register
Yes
Program Completed
No
I/O 6 = 1 ?
or R/B = 1 ?
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Yes
*
No
Program Error
I/O 0 = 0 ?
Yes
16
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Read Data
Write D0h
Read Status Register
ECC Generation
No
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
Verify ECC
Yes
Yes
*
No
Page Read Completed
Erase Error
I/O 0 = 0 ?
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Buffer
memory
error occurs
Page a
When the error happens with page "a" of Block "A", try
to write the data into another Block "B" from an exter-
nal buffer. Then, prevent further system access to
Block "A" (by creating a "invalid block" table or other
appropriate scheme.)
Block A
Block B
17
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Pointer Operation of K9K1G08X0A(X8)
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
Table 2. Destination of the pointer
"A" area
(00h plane)
"B" area
(01h plane)
"C" area
(50h plane)
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
256 Byte
256 Byte
16 Byte
"A"
"B"
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 5. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
Address / Data input
80h 10h
00h
80h
10h
00h
’A’,’B’,’C’ area can be programmed.
’00h’ command can be omitted.
It depends on how many data are inputted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~511), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
Address / Data input
80h 10h
01h
80h
10h
01h
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
’01h’ command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
Address / Data input
80h 10h
50h
80h
10h
50h
Only ’C’ area can be programmed.
’50h’ command can be omitted.
18
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Pointer Operation of K9K1G16X0A(X16)
Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’ command
sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the
starting column address can be set to any of a whole page(0~263word). ’00h’ or ’50h’ is sustained until another address pointer com-
mand is inputted. To program data starting from ’A’ or ’B’ area, ’00h’ or ’50h’ command must be inputted before ’80h’ command is writ-
ten. A complete read operation prior to ’80h’ command is not necessary.
Table 3. Destination of the pointer
"A" area
(00h plane)
"B" area
(50h plane)
Command
Pointer position
Area
00h
50h
0 ~ 255 word
256 ~ 263 word
main array(A)
spare array(B)
256 Word
8 Word
"A"
"B"
Internal
Page Register
Pointer select
command
(00h, 50h)
Pointer
Figure 6. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
Address / Data input
80h 10h
00h
80h
10h
00h
’A’,’B’ area can be programmed.
’00h’ command can be omitted.
It depends on how many data are inputted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~263), and sustained
Address / Data input
Address / Data input
80h 10h
50h
80h
10h
50h
Only ’B’ area can be programmed.
’50h’ command can be omitted.
19
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte(x8 device), 264word(x16 device) page registers are utilized as separate buffers for this operation and the system design gets
more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during
the data-loading and reading would provide significant savings in power consumption.
Figure 7. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
80h
Start Add.(4Cycle)
Data Input
Data Input
10h
I/OX
tCS
tCH
tCEA
CE
CE
tREA
RE
tWP
WE
I/OX
out
Figure 8. Read Operation with CE don’t-care.
On K9K1G08U0A_Y,P or K9K1G08U0A_V,F
CE must be held
low during tR
CLE
CE
CE don’t-care
RE
ALE
tR
R/B
WE
Data Output(sequential)
I/OX
00h
Start Add.(4Cycle)
20
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
I/O
DATA
Device
I/Ox
Data In/Out
~528byte
~264word
K9K1G08X0A(X8 device)
K9K1G16X0A(X16 device)
I/O 0 ~ I/O 7
I/O 0 ~ I/O 151)
NOTE: I/O8~15 must be set to "0" during command or address input.
I/O8~15 are used only for data bus.
Command Latch Cycle
CLE
tCLH
tCH
tCLS
tCS
CE
tWP
WE
tALS
tALH
ALE
tDH
tDS
Command
I/O0~7
Address Latch Cycle
tCLS
CLE
CE
tCS
tWC
tWC
tWC
tWP
tWP
tWP
tWP
WE
tWH
tALH
tALS
tWH
tALH
tALS
tWH
tALH
tALS
tALH
tDH
tALS
ALE
tDH
tDH
tDH
tDS
tDS
tDS
tDS
A0~A7
A9~A16
A17~A24
I/O0~7
A25,,A26
21
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
ALE
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/O0~7
DIN 1
DIN 511
DIN 0
Serial access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
CE
tCHZ*
tOH
tREH
tREA
tREA
tREA
RE
tRHZ*
tOH
tRHZ*
I/Ox
Dout
Dout
Dout
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
22
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCEA
tCHZ
tOH
tWHR
RE
tRHZ
tOH
tDH
tREA
tDS
tIR
Status Output
I/OX
70h
Read1 Operation(Read One Page)
CLE
tCEH
tCHZ
CE
tWC
WE
ALE
RE
tWB
tCRY
tAR2
tRHZ
tR
tRC
tRR
A17 ~ A24
00h or 01h A0 ~ A7 A9 ~ A16
Dout N+1 Dout N+2
Dout 527
tRB
Dout N
A25,A26
I/O0~7
R/B
Column
Address
Page(Row)
Address
Busy
23
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Read1 Operation(Intercepted by CE)
CLE
CE
WE
ALE
RE
tWB
tCHZ
tAR
tR
tRC
tRR
A9 ~ A16 A17 ~ A24
Dout N+2
00h or 01h A0 ~ A7
Dout N
Dout N+1
A25,A26
I/O0~7
Page(Row)
Address
Column
Address
Busy
R/B
Read2 Operation(Read One Page)
CLE
CE
WE
ALE
RE
tR
tWB
tAR
tRR
Dout
511+M
50h
A9 ~ A16 A17 ~ A24
Dout 527
A0 ~ A7
A25,A26
I/O0~7
R/B
Selected
Row
M Address
A0~A3 : Valid Address
A4~A7 : Don¢t care
16
512
Start
address M
24
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Sequential Row Read Operation (Within a Block)
CLE
CE
WE
ALE
RE
Dout
N
Dout
N+1
Dout
527
Dout
0
Dout
1
Dout
527
00h
A0 ~ A7 A9 ~ A16
A17 ~ A24
A25,A26
I/O0~7
R/B
Ready
Busy
Busy
M
M+1
Output
N
Output
Page Program Operation
CLE
CE
tWC
tWC
tWC
WE
ALE
RE
tPROG
tWB
Din
N
Din
527
A25,A26
10h
80h
A0 ~ A7 A9 ~ A16 A17 ~ A24
70h
I/O0
I/O0~7
R/B
Sequential Data Column
Input Command Address
Program
Command
1 up to 528 Byte Data
Serial Input
Read Status
Command
Page(Row)
Address
I/O0=0 Successful Program
I/O0=1 Error in Program
25
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
60h
A9 ~ A16 A17 ~ A24
DOh
70h
I/O 0
A25,A26
I/O0~7
R/B
Page(Row)
Address
Busy
I/O0=0 Successful Erase
Read Status I/O0=1 Error in Erase
Command
Auto Block Erase Setup Command
Erase Command
26
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
»
» »
»
»
» »
»
27
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Multi-Plane Block Erase Operation into Plane 0~3 or Plane 4~7
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
60h
A9 ~ A16 A17 ~ A24
DOh
71h
I/O 0
A25,A26
I/O0~7
R/B
Page(Row)
Address
Busy
Erase Confirm Command
Block Erase Setup Command
Read Multi-Plane
Status Command
Max. 4 times repeatable
* For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command.
Ex.) Four-Plane Block Erase Operation
R/B
tBERS
Address
D0h
60h
Address
Address
71h
60h
60h
Address
A9 ~ A26
60h
I/O0~7
28
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Read ID Operation
CLE
CE
WE
ALE
RE
tREAD
Device*
Code
C0h
00h
Address. 1cycle
ECh
A5h
90h
I/O 0 ~ 7
Read ID Command
Maker Code
Multi Plane Code
Device
Device Code
K9K1G08Q0A
K9K1G08U0A
K9K1G16Q0A
K9K1G16U0A
78h
79h
XX72h
XX74h
ID Defintition Table
90 ID : Access command = 90H
Value
Description
1st Byte
2nd Byte
3rd Byte
4th Byte
ECh
79h
A5h
C0h
Maker Code
Device Code
Must be don’t -cared
Supports Multi Plane Operation
29
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Copy-Back Program Operation
CLE
CE
tWC
WE
ALE
RE
tWB
tPROG
tWB
tR
8Ah
00h
A0~A7 A9~A16 A17~A24 A25,A26
10h
70h
I/O0
A0~A7 A9~A16 A17~A24 A25,A26
I/O0~7
R/B
Column
Address
Column
Read Status
Command
Page(Row)
Address
Page(Row)
Address
Address
Busy
Busy
I/O0=0 Successful Program
I/O0=1 Error in Program
Copy-Back Data
Input Command
30
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Device Operation
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-
ister along with four address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 12ms(tR). The system controller can detect the completion of this data transfer(tR) by analyz-
ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns(1.8V device : 60ns)
cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column
address up to the last column address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 12ms again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The
way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes
512 to 527 may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare
area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for
sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 com-
mand(00h/01h) is needed to move the pointer back to the main area. Figures 9 to 12 show typical sequence and timings for each
read operation.
Figure 9. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
00h
Start Add.(4Cycle)
A0 ~ A7 & A9 ~ A26
Data Output(Sequential)
I/O0~7
(00h Command)
(01h Command)*
1st half array 2st half array
1st half array 2st half array
Data Field
Spare Field
Data Field
Spare Field
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
31
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Figure 10. Read2 Operation
CLE
CE
WE
ALE
R/B
RE
tR
50h
Data Output(Sequential)
Spare Field
Start Add.(4Cycle)
A0 ~ A3 & A9 ~ A26
I/O0~7
(A4 ~ A7 :
Don¢t Care)
1st half array
2nd half array
Data Field
Spare Field
Figure 11. Sequential Row Read1 Operation
tR
tR
tR
R/B
Data Output
1st
Data Output
Data Output
I/O0 ~ 7
00h
01h
Start Add.(4Cycle)
A0 ~ A7 & A9 ~ A26
2nd
(528 Byte)
Nth
(528 Byte)
( 00h Command)
( 01h Command)
1st half array
2nd half array
1st half array
2nd half array
1st
1st
2nd
Nth
Block
2nd
Nth
Data Field
Spare Field
Data Field
Spare Field
The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read-
out, the sequential read operation must be terminated by bringing CE high. When the page address moves onto
the next block, read command and address must be given.
32
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Figure 12. Sequential Row Read2 Operation
tR
tR
tR
R/B
Start Add.(4Cycle)
A0 ~ A3 & A9 ~ A26
Data Output
1st
I/O0~7
50h
Data Output
Data Output
2nd
(16Byte)
Nth
(16Byte)
(A4 ~ A7 :
Don¢t Care)
1st
Block
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes
up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page with-
out an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in any ran-
dom order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded
into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached
technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write state control automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command
may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle
by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 13).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.
Figure 13. Program & Read Status Operation
tPROG
R/B
Pass
I/O0~7
80h
Address & Data Input
I/O0
Fail
10h
70h
A0 ~ A7 & A9 ~ A26
528 Byte Data
33
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase
Setup command(60h). Only address A14 to A26 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 14 details the sequence.
Figure 14. Block Erase Operation
tBERS
R/B
Pass
I/O0~7
60h
I/O0
Fail
70h
Address Input(3Cycle)
Block Add. : A14 ~ A26
D0h
Multi-Plane Page Program into Plane 0~3 or Plane 4~7
Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Since
the device is equipped with eight memory planes, activating the four sets of 528 byte page registers into plane 0~3 or plane 4~7
enables a simultaneous programming of four pages. Partial activation of four planes is also permitted.
After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming
process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate
71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set
of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane,
actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming pro-
cess. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages into plane 0~3 or plane
4~7 are programmed simultaneously, pass/fail status is available for each page when the program operation completes. The
extended status bits (I/O1 through I/O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1"
when any of the pages fails.
Multi-Plane page Program with "01h" pointer is not supported, thus prohibited.
Figure 15. Four-Plane Page Program
tDBSY
tPROG
tDBSY
tDBSY
R/B
Address &
Data Input
A0 ~ A7 & A9 ~ A26
528 Byte Data
Address &
Data Input
A0 ~ A7 & A9 ~ A26
528 Byte Data
Address &
Data Input
A0 ~ A7 & A9 ~ A26
528 Byte Data
Address &
Data Input
A0 ~ A7 & A9 ~ A26
528 Byte Data
71h
80h
10h
80h
11h
11h
80h
80h
11h
I/O0~7
80h
80h
10h
80h
11h
11h
80h
11h
Data
input
Plane 3
(1024 Block)
Plane 0
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Block 3
Block 7
Block 2
Block 6
Block 1
Block 5
Block 0
Block 4
Block 4091
Block 4095
Block 4090
Block 4094
Block 4089
Block 4093
Block 4088
Block 4092
34
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Restirction in addressing with Multi Plane Page Program
While any block in each plane may be addressable for Multi-Plane Page Program, the four least significant addresses(A9-A13) for
the selected pages at one operation must be the same. Figure 16 shows an example where 2nd page of each addressed block is
selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure17.
Figure 16. Multi-Plane Program & Read Status Operation
Plane 3
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Plane 0
(1024 Block)
Block 0
Block 2
Block 3
Block 1
Page 0
Page 1
Page 0
Page 0
Page 1
Page 0
Page 1
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Figure 17. Addressing Multiple Planes
Plane 1
Plane3
80h
10h
Plane 2
Plane 0
80h
11h
80h
11h
80h
11h
Figure 18. Multi-Plane Page Program & Read Status Operation
tPROG
R/B
Last Plane input
Pass
I/O0~7
80h
Address & Data Input
I/O
10h
71h
A0 ~ A7 & A9 ~ A26
528 Byte Data
Fail
Multi-Plane Block Erase into Plane 0~3 or Plane 4~7
Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by three
address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane.
The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busy
status (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1
through I/O 4).
Figure 19. Four Block Erase Operation
R/B
tBERS
Address
(3 Cycle)
Address
(3 Cycle)
Address
(3 Cycle)
Address
(3 Cycle)
60h
60h
60h
D0h
71h
Pass
60h
I/O0~7
I/O
A0 ~ A7 & A9 ~ A26
Fail
35
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Copy-Back Program
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within
the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential
execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read opera-
tion with "00h" command and the address of the source page moves the whole 528byte data into the internal buffer. As soon as the
device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of destination page followed may be
written. The Program Confirm command (10h) is required to actually begin the programming operation. Copy-Back Program opera-
tion is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page program-
ming into the copied pages is prohibited before erase. A14, A15 and A26 must be the same between source and target page.
Figure20 shows the command sequence for single plane operation. "When there is a program-failure at Copy-Back operation,
error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is
not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the
use of Copy-Back operation."
Figure 20. One Page Copy-Back program Operation
tR
tPROG
R/B
Add.(4Cycles)
Pass
I/O0~7
00h
Add.(4Cycles)
I/O0
Fail
10h
8Ah
70h
A0 ~ A7 & A9 ~ A26
Source Address
A0 ~ A7 & A9 ~ A26
Destination Address
36
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Multi-Plane Copy-Back Program
Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is
equipped with four memory planes, activating the four sets of 528 bytes(x8 device) or 264words(x16 device)page registers enables a
simultaneous Multi-Plane Copy-Back programming of four pages. Partial activation of four planes is also permitted.
First, normal read operation with the "00h"command and address of the source page moves the whole 528 byte data into internal
page buffers. Any further read operation for transferring the addressed pages to the corresponding page register must be executed
with "03h" command instead of "00h" command. Any plane may be selected without regard to "00h" or "03h". Up to four planes may
be addressed. Data moved into the internal page registers are loaded into the destination plane addresses. After the input of com-
mand sequences for reading the source pages, the same procedure as Multi-Plane Page programming except for a replacement
address command with "8Ah" is executed. Since no programming process is involved during data loading at the destination plane
address , R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be
issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). After inputting data for the last
plane, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming
process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed
simultaneously, pass/fail status is available for each page when the program operation completes. No pointer operation is supported
with Multi-Plane Copy-Back Program. Once the Multi-Plane Copy-Back Program is finished, any additional partial page pro-
gramming into the copied pages is prohibited before erase once the Multi-Plane Copy-Back Program is finished.
Figure 21. Four-Plane Copy-Back Program
Max Three Times Repeatable
03h
03h
00h
03h
Source
Address
Input
Plane 3
(1024 Block)
Plane 0
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Block 3
Block 7
Block 2
Block 6
Block 1
Block 5
Block 0
Block 4
Block 4091
Block 4095
Block 4089
Block 4093
Block 4090
Block 4094
Block 4088
Block 4092
Max Three Times Repeatable
8Ah
10h
8Ah
11h
8Ah
11h
8Ah
11h
Destination
Address
Input
Plane 3
(1024 Block)
Plane 0
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Block 3
Block 7
Block 2
Block 6
Block 1
Block 5
Block 0
Block 4
Block 4091
Block 4095
Block 4090
Block 4094
Block 4089
Block 4093
Block 4088
Block 4092
37
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
»
»
»
»
»
»
38
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether
multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The
pass/fail status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation.
Table4. Read Staus Register Definition
I/O No.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Status
Definition by 70h Command
Definition by 71h Command
Pass : "0"(1)
Fail : "1"
Fail : "1"
Total Pass/Fail
Plane 0 Pass/Fail
Plane 1 Pass/Fail
Plane 2 Pass/Fail
Plane 3 Pass/Fail
Reserved
Pass : "0"
Fail : "1"
Pass : "0"(2)
Must be don’t -cared
Must be don’t -cared
Must be don’t -cared
Must be don’t -cared
Must be don’t -cared
Busy : "0"
Pass : "0"(2)
Fail : "1"
Fail : "1"
Fail : "1"
Pass : "0"(2)
Pass : "0"(2)
Must be don’t-cared
Busy : "0"
Device Operation
Write Protect
Ready : "1"
Ready : "1"
Protected : "0"
Not Protected : "1"
Protected : "0"
Not Protected : "1"
NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/
Erase operation, it sets "Fail" flag.
2. The pass/fail status applies only to the corresponding plane.
39
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Four read cycles sequentially output the manufacture code(ECh), and the device code*, Reserved(A5h), Multi plane operation
code(C0h) respectively. A5h must be don’t-cared. C0h means that device supports Multi Plane operation. The command register
remains in Read ID mode until further commands are issued to it. Figure 23 shows the operation sequence.
Figure 23. Read ID Operation 1
CLE
tCEA
CE
WE
tAR
ALE
RE
tWHR
tREA
Device*
Code
I/O0~7
90h
00h
ECh
A5h
C0h
Maker code
Address. 1cycle
Multi-Plane code
Device
Device Code
K9K1G08Q0A
78h
79h
K9K1G08U0A
K9K1G16Q0A
K9K1G16U0A
XX72h
XX74h
40
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 24 below.
Figure 24. RESET Operation
tRST
R/B
I/O0~7
FFh
Table5. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
41
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 25). Its value can be
determined by the following guidance.
Rp
ibusy
VCC
1.8V device - VOL : 0.1V, VOH : VccQ-0.1V
3.3V device - VOL : 0.4V, VOH : 2.4V
Ready Vcc
R/B
open drain output
VOH
CL
VOL
Busy
tf
tr
GND
Device
Figure 25. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
400
2.4
Ibusy
Ibusy
300n
3m
300n
3m
300
1.2
1.7
200n
100n
2m
1m
200n
100n
200
0.8
2m
1m
120
0.85
60
90
tr
tr
30
100
3.6
0.6
3.6
0.57
1.7
0.43
3.6
2K
3.6
tf
1.7
1.7
2K
tf
1.7
4K
1K
3K
4K
1K
3K
Rp(ohm)
Rp(ohm)
Rp value guidance
VCC(Max.) - VOL(Max.)
1.85V
Rp(min, 1.8V part) =
=
=
3mA + SIL
IOL + SIL
VCC(Max.) - VOL(Max.)
3.2V
Rp(min, 3.3V part) =
IOL + SIL
8mA + SIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
42
Preliminary
FLASH MEMORY
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V(1.8V device) or 2V(3.3V device). WP pin provides hardware protection and
is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 10ms is required before internal
circuit gets ready for any command sequences as shown in Figure 26. The two step command sequence for program/erase provides
additional software protection.
Figure 26. AC Waveforms for Power Transition
1.8V device : ~ 1.5V
3.3V device : ~ 2.5V
1.8V device : ~ 1.5V
3.3V device : ~ 2.5V
VCC
High
WP
WE
10ms
43
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