K9K2G08R0A-JIB0T00 [SAMSUNG]
EEPROM Card, 256MX8, 45ns, Parallel, CMOS, PBGA63;
| 型号： | K9K2G08R0A-JIB0T00 |
| 厂家： | 
SAMSUNG |
| 描述： | EEPROM Card, 256MX8, 45ns, Parallel, CMOS, PBGA63 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总38页 (文件大小：977K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
K9K2G08X0A
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Document Title
256M x 8 Bit NAND Flash Memory
Revision History
Revision No History
Draft Date
Remark
Advance
0.0
0.1
1. Initial issue
May. 31. 2004
1. Technical note is changed
Preliminary
Oct. 25. 2004
2. Notes of AC timing characteristics are added
3. The description of Copy-back program is changed
4. TSOP package is deleted
0.2
0.3
0.4
1.0
Feb. 14. 2005
1. CE access time : 23ns->35ns (p.9)
1. The value of tREA is changed. (18ns->20ns)
2. EDO mode is added.
May
May
4
6
2005
2005
1. The flow chart to creat the initial invalid block table is changed.
Feb. 1 2006
1. 1.8V FBGA spec is merged
2. 3.3V FBGA package is added
3. FBGA package size is changed to 9.5 x 12
4. Leaded part is deleted
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
2
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
256M x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9K2G08U0A-F
K9K2G08R0A-J
Vcc Range
2.7 ~ 3.6V
1.65 ~ 1.95V
Organization
PKG Type
WSOP1
FBGA
X8
X8
FEATURES
• Voltage Supply
• Fast Write Cycle Time
- 2.7 V ~3.6 V
- Program time : 300µs(Typ.)
- 1.65V ~ 1.95V
• Organization
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
- Memory Cell Array
- (256M + 8,192K)bit x 8bit
- Data Register
- (2K + 64)bit x8bit
• Automatic Program and Erase
- Page Program
• Command Register Operation
- (2K + 64)Byte
- Block Erase
• Unique ID for Copyright Protection
• Package :
- (128K + 4K)Byte
• Page Read Operation
- Page Size
- K9K2G08U0A-FIB0
48 - Pin WSOP I (12x17x0.7mm)- Pb-free Package
- K9K2G08R0A-JCB0/JIB0
- 2K-Byte
63- Ball FBGA (9.5x12) - Pb-free Package
- Random Read : 25µs(Max.)
- Serial Access : 50ns(Min.)
GENERAL DESCRIPTION
Offered in 256Mx8bit the K9K2G08X0A is 2G bit with spare 64M bit capacity. Its NAND cell provides the most cost-effective solution
for the solid state mass storage market. A program operation can be performed in typical 300µs on the 2112byte page and an erase
operation can be performed in typical 2ms on a 128K-byte block. Data in the data page can be read out at 50ns cycle time per byte.
The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all
program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the
write-intensive systems can take advantage of the K9K2G08X0A′s extended reliability of 100K program/erase cycles by providing
ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K2G08X0A is an optimum solution for large nonvolatile
storage applications such as solid state file storage and other portable applications requiring non-volatility.
3
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
PIN CONFIGURATION (WSOP1)
K9K2G08U0A-FIB0
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
CE
9
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
WP
N.C
N.C
DNU
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
Unit :mm
48 - WSOP1 - 1217F
0.70 MAX
0.58±0.04
15.40±0.10
#1
#48
#24
#25
(0.01Min)
0.45~0.75
17.00±0.20
4
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
PIN CONFIGURATION (FBGA)
K9F1G08R0A-JCB0/JIB0
1
2
3
4
5
6
N.C N.C
N.C N.C
N.C
N.C N.C
A
B
/WP ALE Vss /CE /WE R/B
NC
NC
NC
NC
/RE CLE NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C
D
E
NC
NC
NC
NC NC
NC NC
NC NC
F
NC I/O0 NC
NC
Vcc
G
H
NC I/O1 NC Vcc I/O5 I/O7
Vss I/O2 I/O3 I/O4 I/O6 Vss
N.C N.C
N.C N.C
N.C N.C
N.C N.C
Top View
5
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
PACKAGE DEMENSIONS(FBGA)
Top View
Bottom View
#A1 INDEX MARK(OPTIONAL)
A
9.50±0.10
0.80 x 9= 7.20
0.80 x 5= 4.00
0.80
9.50±0.10
B
6
5
4
3
2
1
(Datum A)
#A1
A
B
C
D
E
F
(Datum B)
G
H
63-∅0.45±0.05
∅
0.20
M A B
2.00
Side View
12.00±0.10
0.10MAX
0.45±0.05
6
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
PIN DESCRIPTION
Pin Name
Pin Function
DATA INPUTS/OUTPUTS
I/O0 ~ I/O7
CLE
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase opertion. Regarding CE control during read
operation, refer to ’Page read’ section of Device operation .
CE
READ ENABLE
RE
WE
WP
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output
and does not float to high-z condition when the chip is deselected or when outputs are disabled.
R/B
POWER
Vcc
Vss
N.C
VCC is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
NOTE:
1. Connect all VCC and VSS pins of each device to common power supply outputs.
2. Do not leave VCC or VSS disconnected.
7
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Figure 1. Functional Block Diagram
VCC
VSS
2048M + 64M Bit
NAND Flash
ARRAY
X-Buffers
A12 - A28
Latches
& Decoders
(2048 + 64)Byte x 131072
Y-Buffers
A0 - A11
Latches
& Decoders
Data Register & S/A
Y-Gating
Command
Command
Register
VCC
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 7
CLE ALE
WP
Figure 2 Array Organization
1 Block = 64 Pages
(128K + 4k) Byte
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 2048 Blocks
= 2112 Mbits
128K Pages
(=2,048 Blocks)
8 bit
2K Bytes
64 Bytes
64 Bytes
I/O 0 ~ I/O 7
Page Register
2K Bytes
I/O 0
A0
I/O 1
A1
I/O 2
I/O 3
A3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
Column Address
Column Address
Row Address
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
A2
A10
A14
A22
*L
A8
A9
A11
A15
A23
*L
*L
*L
*L
*L
A12
A20
A28
A13
A21
*L
A16
A24
*L
A17
A25
*L
A18
A26
*L
A19
A27
*L
Row Address
Row Address
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
8
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Product Introduction
The K9K2G08X0A is a 2112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2112x8 columns. Spare 64 col-
umns are located from column address of 2048~2111. A 2112-byte data register is connected to memory cell arrays for accommodat-
ing data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array is
made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block
consists of two NAND structures. A NAND structure consists of 32 cells. Total 135,168 NAND cells reside in a block. The program and
read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of
2048 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K2G08X0A.
The K9K2G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command and etc require just one cycle bus. Some other commands, like Page Read, Block
Erase and Page Program, require two cycles: one cycle for setup and the other cycle for execution. The 264M byte physical space
requires 29 addresses, thereby requiring five cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that order.
Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation,
however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command
register. Table 1 defines the specific commands of the K9K2G08X0A.
Table 1. Command Sets
Function
1st. Cycle
00h
2nd. Cycle
Acceptable Command during Busy
Read
30h
35h
-
Read for Copy Back
Read ID
00h
90h
Reset
FFh
80h
-
O
Page Program
Cache Program
Copy-Back Program
Block Erase
10h
15h
10h
D0h
-
80h
85h
60h
Random Data Input*1
Random Data Output*1
Read Status
85h
05h
E0h
70h
O
NOTE : 1. Random Data Input/Output can be executed in a page.
2. Cache program and Copy-Back program are supported only with 3.3V device.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
9
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
1.8V DEVICE
-0.6 to + 2.45
-0.6 to + 2.45
3.3V DEVICE
VIN/OUT
VCC
-0.6 to + 4.6
V
Voltage on any pin relative to VSS
-0.6 to + 4.6
K9K2G08X0A-XCB0
K9K2G08X0A-XIB0
K9K2G08X0A-XCB0
K9K2G08X0A-XJIB0
-10 to +125
-40 to +125
Temperature Under
Bias
TBIAS
°C
Storage Temperature
TSTG
Ios
-65 to +150
5
°C
Short Circuit Current
mA
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, :TA=0 to 70°C, K9K2G08X0A-XIB0:TA=-40 to 85°C)
K9K2G08R0A(1.8V)
K9K2G08U0A(3.3V)
Parameter
Symbol
Unit
Min
1.65
0
Typ.
1.8
0
Max
1.95
0
Min
2.7
0
Typ.
3.3
0
Max
3.6
0
Supply Voltage
Supply Voltage
VCC
VSS
V
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
K9K2G08R0A(1.8V)
K9K2G08U0A(3.3V)
Parameter
Symbol
Test Conditions
Unit
Min
Typ
Max
Min
Typ
Max
tRC=50ns, (30ns with 3.3V device)
CE=VIL
IOUT=0mA
Page Read with
Serial Access
Operat-
ICC1
-
10
20
-
10
30
ing
Current
mA
Program
Erase
ICC2
ICC3
ISB1
-
-
-
-
10
10
-
20
20
1
-
-
-
10
10
-
30
30
1
-
Stand-by Current(TTL)
CE=VIH, WP=0V/VCC
CE=VCC-0.2,
WP=0V/VCC
Stand-by Current(CMOS)
ISB2
-
20
100
-
20
100
µA
Input Leakage Current
Output Leakage Current
Input High Voltage
ILI
VIN=0 to Vcc(max)
-
-
-
-
±20
±20
-
-
-
-
-
±10
±10
ILO
VIH
VOUT=0 to Vcc(max)
-
-
0.8xVcc
Vcc+0.3 0.8xVcc
Vcc+0.3
Input Low Voltage, All
inputs
VIL
VOH
VOL
-
-0.3
-
-
0.2xVcc
-0.3
2.4
-
-
-
0.2xVcc
Output High Voltage
Level
K9K2G08R0A: IOH=-100µA
K9K2G08U0A: IOH=-400µA
V
Vcc-0.1
-
0.1
-
-
0.4
-
K9K2G08R0A: IOL=100mA
K9K2G08U0A: IOL=2.1mA
Output Low Voltage Level
-
-
-
K9K2G08R0A: VOL=0.1V
K9K2G08U0A: VOL=0.4V
Output Low Current(R/B) IOL(R/B)
3
4
8
10
mA
10
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
2008
-
2048
Blocks
NOTE :
1. The K9K2G08X0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase
or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block and does not require Error Correction up to 1K Program/
Earase cycles..
AC TEST CONDITION
(K9K2G08X0A-XCB0 :TA=0 to 70°C, K9K2G08X0A-XIB0:TA=-40 to 85°C
K9K2G08R0A : Vcc=1.65V~1.95V, K9K2G08U0A : Vcc=2.7V~3.6Vunless otherwise noted)
Parameter
K9K2G08R0A
K9K2G08U0A
Input Pulse Levels
0V to Vcc
0V to Vcc
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
5ns
Vcc/2
5ns
Vcc/2
1 TTL GATE and CL=30pF
1 TTL GATE and CL=50pF
CAPACITANCE(TA=25C, VCC=1.8V/3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
20
Unit
pF
Input/Output Capacitance
Input Capacitance
CI/O
VIL=0V
VIN=0V
-
-
CIN
20
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
WP
Mode
Command Input
X
Read Mode
Write Mode
H
L
H
X
Address Input(5clock)
Command Input
H
L
L
L
H
H
H
L
H
H
Address Input(5clock)
L
L
L
H
H
Data Input
L
L
L
H
X
X
X
X
X
X
Data Output
X
X
X
X
X
X
H
H
X
X
X
X
X
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
X
X
H
X
X
H
L
X(1)
X
X
(2)
X
Stand-by
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
µs
*1
Program Time
-
200
700
700
4
tPROG
*2
Dummy Busy Time for Cache Program
3
-
µs
tCBSY
Main Array
Spare Array
-
-
-
cycles
cycles
ms
Number of Partial Program Cycles
in the Same Page
Nop
-
4
Block Erase Time
tBERS
2
3
NOTE : 1.Typical program time is defined as the time within which more than 50% of whole pages are programmed at Vcc of 3.3V and 25°C
2. Max. time of tCBSY depends on timing between internal program completion and data in
11
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Min
Max
Parameter
Symbol
Unit
K9K2G08R0A
K9K2G08U0A
K9K2G08R0A
K9K2G08U0A
*1
CLE setup Time
25
10
15
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLS
CLE Hold Time
tCLH
*1
CE setup Time
35
20
5
tCS
CE Hold Time
tCH
tWP
10
WE Pulse Width
ALE setup Time
ALE Hold Time
25
15
15
5
*1
25
tALS
tALH
10
*1
Data setup Time
Data Hold Time
20
15
5
tDS
tDH
tWC
tWH
10
Write Cycle Time
WE High Hold Time
Address to Data Loading Time
45
30
10
100*2
15
*2
tADL
100*2
NOTE : 1. The transition of the corresponding control pins must occur only once while WE is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
3. For cache program operation, the whole AC Charcateristics must be same as that of K9K2G08R0A.
AC Characteristics for Operation
Min
Max
Parameter
Symbol
Unit
K9K2G08R0A K9K2G08U0A
K9K2G08R0A
K9K2G08U0A
Data Transfer from Cell to Register
ALE to RE Delay
tR
tAR
-
10
10
20
25
-
-
10
10
20
15
-
25
25
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
-
-
CLE to RE Delay
tCLR
tRR
-
-
Ready to RE Low
-
-
RE Pulse Width
tRP
-
-
WE High to Busy
tWB
tRC
100
100
Read Cycle Time
50
-
30
-
-
-
RE Access Time
tREA
tCEA
tRHZ
tCHZ
tOH
30
20
CE Access Time
-
-
45
35
RE High to Output Hi-Z
CE High to Output Hi-Z
RE or CE High to Output hold
RE High Hold Time
-
-
30
30
-
-
20
20
15
15
0
15
10
0
-
-
tREH
tIR
-
-
Output Hi-Z to RE Low
WE High to RE Low
-
-
tWHR
tRST
60
-
60
-
-
-
Device Resetting Time (Read/Program/Erase)
5/10/500*1
5/10/500*1
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. For cache program operation, the whole AC Charcateristics must be same as that of K9K2G08R0A.
12
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is
placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase
cycles.
Identifying Initial Invalid Block(s)
All device locations are erased except locations where the initial invalid block(s) information is written prior to shipping. The initial
invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial
invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most
cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial
invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow
chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFh" at the column address
2048 of the 1st and 2nd page in the block
*
No
Create (or update)
Initial Invalid Block(s) Table
Check "FFh ?
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table.
13
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block fail-
ure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read
failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be
employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should be
reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those reclaimed
blocks.
Failure Mode
Erase Failure
Detection and Countermeasure sequence
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Verify ECC -> ECC Correction
Write
Read
Program Failure
Single Bit Failure
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
No
I/O 6 = 1 ?
or R/B = 1 ?
Yes
*
No
Program Error
I/O 0 = 0 ?
Yes
P
rogram Completed
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
14
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Write 00h
Start
Write 60h
Write Block Address
Write Address
Write 30h
Write D0h
Read Data
Read Status Register
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
No
Verify ECC
Reclaim the Error
Yes
*
No
Yes
Erase Error
I/O 0 = 0 ?
Page Read Completed
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Block A
1st
{
(n-1)th
1
nth
an error occurs.
(page)
Buffer memory of the controller.
Block B
1st
2
{
(n-1)th
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
15
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-
nificant bit) pages of the block. Random page address programming is prohibited.
(64)
(64)
Page 63
Page 31
Page 63
Page 31
:
:
(1)
:
(32)
:
(3)
(2)
(1)
Page 2
Page 1
Page 0
(3)
(32)
(2)
Page 2
Page 1
Page 0
Data register
Data register
From the LSB page to MSB page
DATA IN: Data (1)
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (64)
Data (64)
16
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of µ-seconds, de-activating CE during the data-loading and serial access
would provide significant savings in power consumption.
Figure 4. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
I/Ox
Address(5Cycles)
80h
Data Input
Data Input
10h
tCH
tCEA
tCS
CE
RE
CE
tREA
tWP
WE
out
I/O0~7
Figure 5. Read Operation with CE don’t-care.
CLE
CE
CE don’t-care
RE
ALE
tR
R/B
WE
I/Ox
Data Output(serial access)
00h
Address(5Cycle)
30h
17
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
NOTE
I/O
I/Ox
DATA
ADDRESS
Device
Data In/Out
~2112byte
Col. Add1
Col. Add2
Row Add1
Row Add2
Row Add3
K9K2G08X0A
I/O 0 ~ I/O 7
A0~A7
A8~A11
A12~A19
A20~A27
A28
Command Latch Cycle
CLE
tCLS
tCS
tCLH
tCH
CE
tWP
WE
tALS
tALH
ALE
I/Ox
tDH
tDS
Command
Address Latch Cycle
tCLS
tCS
CLE
tWC
tWC
tWC
CE
tWP
tWP
tWP
tWP
WE
tWH
tWH
tWH
tALH
tDH
tALH
tALS
tALH
tALH
tALS
tALS
tALS
ALE
I/Ox
tDH
tDH
tDH
tDS
tDS
tDS
tDS
Col. Add2
Row Add1
Col. Add1
Row Add2
18
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tALS
ALE
tWC
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/Ox
DIN final*
DIN 0
DIN 1
NOTES : DIN final means 2112
Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
tCEA
CE
tCHZ*
tOH
tREH
tREA
tREA
tREA
RE
tRHZ*
tRHZ*
tOH
I/Ox
R/B
Dout
Dout
Dout
tRC
tRR
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
19
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Status Read Cycle
tCLR
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCEA
tCHZ*
tOH
tWHR
RE
tRHZ*
tOH
tDH
tREA
tDS
tIR*
I/Ox
Status Output
70h
20
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Read Operation
tCLR
CLE
CE
tWC
WE
ALE
RE
tWB
tAR
tRHZ
tR
tRC
tRR
Col. Add2 Row Add1 Row Add2
00h
Col. Add1
30h
Dout N
Dout N+1
Dout M
Row Add3
I/Ox
R/B
Column Address
Row Address
Busy
Read Operation(Intercepted by CE)
CLE
CE
WE
ALE
RE
tWB
tCHZ
tOH
tAR
tR
tRC
tRR
Row Add2 Row Add3
Dout N+2
00h
Col. Add1 Col. Add2 Row Add1
30h
Dout N+1
Dout N
I/Ox
R/B
Row Address
Column Address
Busy
21
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
22
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Page Program Operation
CLE
CE
tWC
tWC
tWC
WE
ALE
RE
tPROG
tWB
tADL
Din
N
Din
M
Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3
80h
I/Ox
R/B
10h
70h
I/O0
SerialData
Input Command
Program
Command
1 up to m Byte
Serial Input
Read Status
Command
Column Address
Row Address
I/O
0
=0 Successful Program
=1 Error in Program
I/O0
m = 2112byte
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
23
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
≈
≈ ≈
≈
≈ ≈
≈
24
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
≈
≈ ≈
≈
25
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
≈
≈ ≈
≈ ≈
26
≈
≈
≈
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Block Erase Operation
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/Ox
Row Add1 Row Add2 Row Add3
60h
D0h
70h
I/O 0
Row Address
Busy
R/B
Auto Block Erase
Setup Command
Erase Command
I/O
0
=0 Successful Erase
Read Status I/O
Command
0=1 Error in Erase
27
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Read ID Operation
CLE
CE
WE
ALE
RE
tAR
tREA
Device
Code*
I/Ox
4th cyc.*
00h
ECh
XXh
90h
Read ID Command
Maker Code Device Code
Address. 1cycle
Device
Device Code*(2nd Cycle)
4th Cycle*
15h
K9K2G08R0A
K9K2G08U0A
AAh
DAh
15h
ID Defintition Table
90 ID : Access command = 90H
Description
1st Byte
2nd Byte
3rd Byte
4th Byte
Maker Code
Device Code
Don’t care
Page Size, Block Size, Spare Size, Organization
28
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
4th ID Data
Description
1KB
2KB
Reserved
Reserved
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
0
0
1
1
0
1
0
1
Page Size
(w/o redundant area )
64KB
0
0
1
1
0
1
0
1
Blcok Size
(w/o redundant area )
128KB
256KB
Reserved
Redundant Area Size
( byte/512byte)
8
16
0
1
x8
x16
0
1
Organization
50ns
0
1
0
1
0
0
1
1
Reserved
Reserved
Reserved
Serial AccessMinimum
29
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Device Operation
PAGE READ
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data
within the selected page are transferred to the data registers in less than 25µs(tR). The system controller can detect the completion of
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read
out in 50ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the
data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com-
mand. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/Ox
00h
Address(5Cycle)
30h
Data Output(Serial Access)
Col Add1,2 & Row Add1,2,3
Data Field
Spare Field
30
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Figure 7. Random Data Output In a Page
tR
R/B
RE
Address
5Cycles
Address
2Cycles
Data Output
Data Output
30h
E0h
00h
05h
I/Ox
Col Add1,2 & Row Add1,2,3
Data Field
Data Field
Spare Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive
bytes up to 2112, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare array(
1time/16byte). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading
period in which up to 2112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the
loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random
data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial
data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings
necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read
Status Register command may be entered to read the status register. The system controller can detect the completion of a program
cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset com-
mand are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
tPROG
R/B
"0"
Pass
80h
Address & Data Input
I/O0
Fail
I/Ox
10h
70h
Col Add1,2 & Row Add1,2,3
Data
"1"
31
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Figure 9. Random Data Input In a Page
tPROG
R/B
"0"
Pass
80h
Address & Data Input
Address & Data Input
I/O0
Fail
I/Ox
85h
10h
70h
Col Add1,2
Data
Col Add1,2 & Row Add1,2,3
Data
"1"
Cache Program
Cache Program is an extension of Page Program, which is executed with 2112byte data registers, and is available only within a block.
Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed
into memory cell.
After writing the first set of data up to 2112byte into the selected cache registers, Cache Program command (15h) instead of actual
Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache reg-
isters to data registers, the device remains in Busy state for a short period of time(tCBSY) and has its cache registers ready for the
next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may
be issued to find out when cache registers become ready by polling the Cache-Busy status bit(I/O 6). Pass/fail status of only the pre-
viouse page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command,
tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit(I/
O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of
programming only with R/B, the last page of the target programming sequence must be progammed with actual Page Program com-
mand (10h). If the Cache Program command (15h) is used instead, status bit (I/O5) must be polled to find out when the last program-
ming is actually finished before starting other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the
status of the previous page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true
Ready (returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is checked.
Figure 10. Cache Program(available only within a block)
tPROG
tCBSY
tCBSY
tCBSY
R/B
Address &
Data Input
Address &
Data Input
Address &
Data Input*
Address &
Data Input
80h
70h
10h
80h
15h
80h
80h
15h
15h
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
tCBSY
tCBSY
tCBSY
R/B
I/Ox
Status
output
Status
output
Address &
Data Input
Address &
Data Input
Address &
Data Input
80h
80h
80h
15h
70h
15h
70h
15h
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
tCBSY
Address &
Data Input
Status
Status
output
Status
output
80h
70h
70h
15h
output
Col Add1,2 & Row Add1,2,3
Data
Check I/O1 for pass/fail
Check I/O5 for internal ready/busy
Check I/O0,1 for pass/fail
32
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the
previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after comple-
tion of the previous cycle, which can be expressed as the following formula.
tPROG= Program time for the last page+ Program time for the ( last -1 )th page
- (Program command cycle time + Last page data loading time)
Copy-Back Program
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-
efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned
free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-
ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves
the whole 2112byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input command
(85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actu-
ally begin the programming operation. Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-
Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. A27 must be the
same between source and target page. Data input cycle for modifying a portion or multiple distant portions of the source page is
allowed as shown in Figure 11. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status.
But if the soure page has an error bit by charge loss, accumulated copy-back operations could also accumulate bit errors. In
this case, verifying the source page for a bit error is recommended before Copy-back program"
Figure 11. Page Copy-Back program Operation
tR
tPROG
R/B
I/Ox
Add.(5Cycles)
Pass
00h
35h
Add.(5Cycles)
10h
I/O0
Fail
85h
70h
Col. Add1,2 & Row Add1,2,3
Destination Address
Col. Add1,2 & Row Add1,2,3
Source Address
NOTE: It’s prohibited to operate Copy-Back program from an odd address page(source page) to an even address page(target page) or from an even
address page(source page) to an odd address page(target page). Therefore, the Copy-Back program is permitted just between odd address pages or
even address pages.
Figure 12. Page Copy-Back program Operation with Random Data Input
tPROG
tR
R/B
Add.(5Cycles)
Add.(2Cycles)
Col Add1,2
I/Ox
35h
Add.(5Cycles)
70h
00h
85h
Data
85h
Data
10h
Col. Add1,2 & Row Add1,2,3
Source Address
Col. Add1,2 & Row Add1,2,3
Destination Address
There is no limitation for the number of repetition.
33
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A18 to A28 is valid while A12 to A17 is ignored. The Erase Confirm command(D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
tBERS
R/B
"0"
Pass
60h
I/O0
Fail
70h
Address Input(3Cycle)
Row Add. : A12 ~ A28
I/Ox
D0h
"1"
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.
Table2. Read Staus Register Definition
I/O No.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Page Program
Pass/Fail
Block Erase
Pass/Fail
Not use
Cache Prorgam
Pass/Fail(N)
Pass/Fail(N-1)
Not use
Read
Not use
Definition
Pass : "0"
Fail : "1"
Fail : "1"
Not use
Not use
Pass : "0"
Not use
Not use
Not use
Don’t -cared
Don’t -cared
Don’t -cared
Busy : "0"
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Ready/Busy
Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
True Ready/Busy
Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
Ready : "1"
Ready : "1"
Busy : "0"
Protected : "0"
Not Protected
NOTE : 1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.
2. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
34
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, 15h respectively.
The command register remains in Read ID mode until further commands are issued to it. Figure 11 shows the operation sequence.
Figure 14. Read ID Operation
tCLR
CLE
CE
tCEA
WE
ALE
RE
tAR1
tWHR
Device
Code*
tREA
I/OX
90h
00h
Address. 1cycle
ECh
XXh
4th Cyc.*
Maker code
Device code
Device
Device Code*(2nd Cycle)
4th Cycle*
K9K2G08R0A
K9K2G08U0A
AAh
DAh
15h
15h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST after
the Reset command is written. Refer to Figure 12 below.
Figure 15. RESET Operation
tRST
R/B
I/OX
FFh
Table3. Device Status
After Power-up
After Reset
Operation Mode
00h command is latched
Waiting for next command
35
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or ran-
dom read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-
drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current
drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 13). Its value can be deter-
mined by the following guidance.
Rp
ibusy
VCC
VOL : 0.1V, VOH : VCC-0.1V
Ready Vcc
VOL : 0.4V, VOH : 2.4V
R/B
VOH
open drain output
CL
VOL
Busy
tf
tr
GND
Device
Figure 16. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 50pF
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
Ibusy [A]
200
2.4
Ibusy
300n
3m
300n
3m
150
1.2
Ibusy
1.70
200n
100n
2m 200n
100
0.8
2m
1m
120
0.85
60
90
tr
50
1.8
30
0.6
1.8
100n
1m
tr
0.57
1.70
0.43
1.70
1.8
2K
1.8
tf
1.70
1.70
2K
tf
tr,tf [s]
4K
1K
3K
4K
1K
3K
Rp(ohm)
Rp(ohm)
Rp value guidance
VCC(Max.) - VOL(Max.)
1.85V
Rp(min, 1.8V part) =
Rp(min, 3.3V part) =
=
IOL + ΣIL
3mA + ΣIL
VCC(Max.) - VOL(Max.)
3.2V
=
IOL + ΣIL
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
36
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V(1.8V device) and 2V(3.3V device). WP pin provides hardware protection and
is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10µs is required before internal cir-
cuit gets ready for any command sequences as shown in Figure 14. The two step command sequence for program/erase provides
additional software protection.
Figure 17. AC Waveforms for Power Transition
1.8V device: ~ 1.5V
3.3V device: ~ 2.5V
1.8V device: ~ 1.5V
3.3V device: ~ 2.5V
VCC
High
WP
WE
10µs
37
K9K2G08U0A
K9K2G08R0A
FLASH MEMORY
Extended Data Out Mode
For the EDO mode, the device should hold the data on the system memory bus until the beginning of the next cycle, so that controller
could fetch the data at the falling edge. However NAND flash dosen’t support the EDO mode exactly.
The device stops the data input into the I/O bus after RE rising edge. But since the previous data remains in the I/O bus, the flow of I/
O data seems like Figure 18 and the system can access serially the data with EDO mode. tRLOH which is the parameter for fetching
data at RE falling time is necessary. Its appropriate value can be obtained with the reference chart as shown in Figure 19. The tRHOH
value depands on output load(CL) and I/O bus Pull-up resistor (Rp).
Figure 18. Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)
CE
tRC
tRP
tREH
RE
tREA
tCEA
tREA
tRLOH
tRHOH
I/Ox
R/B
Dout
Dout
tRR
tRHOH
NOTES : Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
Figure 19. Rp vs tRHOH vs CL
Rp
VCC
@ Vcc = 3.3V, Ta = 25°C
tRHOH
Rp = 100k
600
600
600n
Rp = 50k
I/O Drive
500n
425
360
400n
CL
300
300n
180
200n
120
60
Rp = 10k
Rp = 5k
85
100n
60
GND
36
50n
42
30
50p
18
Device
CL (F)
100p
30p
70p
tRLOH / tRHOH value guidance
tRHOH = CL * VOL * Rp / Vcc
tRLOH(min, 3.3V part) = tRHOH - tREH
38
相关型号：
K9K2G08U0A-FIB00
Flash, 256MX8, 20ns, PDSO48, 12 X 17 MM, 0.70 MM HEIGHT, LEAD FREE, PLASTIC, WSOP1-48
SAMSUNG
K9K2G08U0A-PCB00
Flash, 256MX8, 18ns, PDSO48, 12 X 20 MM, 0.50 MM PITCH, PLASTIC, LEAD FREE, TSOP1-48
SAMSUNG
K9K2G08U0A-PIB00
Flash, 256MX8, 18ns, PDSO48, 12 X 20 MM, 0.50 MM PITCH, PLASTIC, LEAD FREE, TSOP1-48
SAMSUNG
©2020 ICPDF网 联系我们和版权申明