KFH1G16Q2M-DID_技术文档

OneNAND512/OneNAND1GDDP

FLASH MEMORY

OneNAND SPECIFICATION

Density

Part No.

VCC(core & IO)

1.8V(1.7V~1.95V)

2.65V(2.4V~2.9V)

3.3V(2.7V~3.6V)

1.8V(1.7V~1.95V)

Temperature

PKG

512Mb

KFG1216Q2M-DEB

KFG1216D2M-DEB

KFG1216U2M-DIB

KFH1G16Q2M-DEB

Extended

Industrial

Extended

63FBGA(LF)

N/A

1Gb

Version: Ver. 1.4

Date: June 15th, 2005

1

OneNAND512/OneNAND1GDDP

FLASH MEMORY

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

OneNAND™‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as the property of their

rightful owners.

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OneNAND512/OneNAND1GDDP

FLASH MEMORY

Document Title

OneNAND

Revision History

Revision No. History

Draft Date

Remark

0.0

Initial issue.

Jan. 07, 2004

Preliminary

0.0.1

1. Add the "Invalid block management" and "Error management in read and Jan. 29, 2004

write operation"

Preliminary

2. Add the restriction in addressing for program operation.

3. Add the asynchronous write and latched asynchronous write mode timing

diagram.

4.Define new parameters in asynchronous write mode.

-tCH1 : 10ns, tCH2 : 0ns

0.0.2

0.0.3

0.1

1. Add the dual operation diagram.

2. Add the block replacement diagram

Jan. 30, 2004

Feb. 03, 2004

Feb.11, 2004

Preliminary

1. Edit the block replacement diagram

2. Add the 3.3V product.

1. Excluded Cache Program Operation

2. Added the descriptions for below operations

-. Reset

-. Write Protection

-. Burst Read Latency

-. Dual Operation

-. Invalid block definition and Identification method

-. Error in write or read operation

-. ECC

3. Revised program sequence

4. Some AC parameters are changed.

tACH : 9ns-->7ns, tCES : 7ns-->9ns, tAAVDS : 5ns-->7ns

tDS : 30ns-->10ns, tDH : 0ns-->4ns

5. Define new AC parameter.

tAWES(Address hold time in AVD low case of asynchronous write mode)

Min. 0ns

0.1.1

1. Correct an errata

Mar.9, 2004

Preliminary

Ball pitch of package is corrected.

0.5mm --> 0.8mm

2. Edit the timing diagram of burst read wrap around.(Figure 23,24)

1. The specification of 2.7V device is added.

0.2

0.3

Mar. 22, 2004

Mar. 31, 2004

Preliminary

1. The specification of 3.3V device is deleted.

2. Correct some typos.

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

3

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Document Title

OneNAND

Revision History

Revision No. History

Draft Date

Remark

0.4

1. Corrected the errata

June 22, 2004

Preliminary

2. Added spare assignment information in detail

3. Added NAND array memory map

4. Added manufacturer ID for CS as 00ECh

5. Added stepping ID for CS in version ID register

6. Divided default status of interrupt status register by Warm,Hot reset and

Cold reset

7. Revised Load operation flow chart

8. Revised Program operation flow chart

9. Deleted DBS setting step in Copy-back operation

10. Added OTP description

11. Revised OTP Load and Program flow chart

12. Added INT guidance

13. ECC description is revised

14. Added Data Protection Scheme during Power-down

15. Added DC/AC parameters

1.0

1. Deleted 2.7V product

August 5, 2004

Final

2. Added 2.65V product

3. Added 3.3V product and industrial temperature in 3.3V product

4. Deleted Unlock/Lock BootRAM command

5. Added DBS setting step in Copy-back operation

6. Added 2.65V/3.3V DC parameters

7. Revised tCES from 9ns to 7ns

8. Deleted tOEH in asynchronous read operation

9. Revised NOP from 4 times per each main and spare in a page to 2 times

per sector

10. Revised Write Protection status description

11. Added DDP selection and operation guidance

12. Added 1Gb DDP device ID

13. Added INT bit status in Cold Reset operation

14. Moved Interrupt register setting before inputting command in all flow

charts

15. Revised Dual operation diagrams

16. Added and revised the asynchronous read operation timing diagram

17. Revised the asynchronous write operation timing diagram

18. Added the tREADY parameter in Hot Reset operation

1.1

1.2

1. Revised standby current for DDP

August 26, 2004

October 26, 2004

Final

1. Corrected DDP device ID

2. Excluded Commercial Temperature range

3. Revised Cold Reset timing diagram

4. Added CE and RDY in Warm Reset diagram

5. Excluded Write while Load and Read while Program operation

6. Revised Extended Temperature minimum value from -25 to -30

7. Revised typical tOTP, tLOCK from 300us to 600us

8. Revised max tOTP, tLOCK from 600us to 1000us

9. Revised Icc4, Icc5 test condition

10. Added Endurance and Data Retention

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

4

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Document Title

OneNAND

Revision History

Revision No. History

Draft Date

Remark

1.3

1. Deleted Manufacturer ID for ES

Dec. 16, 2004

Final

2. Excluded bit error case in Load operation

3. Revised tWEA value from max to min

4. Revised tRD1 typical value from 35us to 40us

5. Revised tRD2 typical value from 75us to 85us

6. Added technical note for OneNAND boot sequence

7. Revised Asycnchronous Read timing diagram for CE don’t care mode

8. Revised Asynchronous Write timing diagram for CE don’t care mode

9. Revised Load operation timing diagram for CE don’t care mode

1. Added Copyright Notice in the beginning

2. Corrected Errata

Jun. 15, 2005

1.4

3. Updated Icc2, Icc4, Icc5, Icc6 and I_SB

4. Revised INT pin description

5. Changed default of Manufacturer ID Register with 00ECh

6. Removed "or erase case, refer to the table 3" from descriptions of WB, EB

7. Added OTP erase case NOTE

8. Revised case definitions of Interrupt Status Register

9. Added a NOTE to Command register

10. Added ECClogSector Information table

11. Removed ’data unit based data handling’ from description of Device

Operation

12. Revised description on Warm/Hot/NAND Flash Core Reset

13. Revised Warm Reset Timing

14. Revised description for 4-, 8-, 16-, 32-Word Linear Burst Mode

15. Revised OTP operation description

16. Restored earlier text for OTP Programming

17. Added supplemental explanation for ECC Operation

18. Replaced "read" with "load" in ECC bypass

19. Removed redundant sentance from ECC Bypass Operation

20. Added technical note for INT pin connection guide

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

5

OneNAND512/OneNAND1GDDP

FLASH MEMORY

1. FEATURES

♦ Architecture

• Design Technology: 0.12um

• Voltage Supply

- 1.8V device(KFG1216Q2M) : 1.7V~1.95V

- 2.65V device(KFG1216D2M) : 2.4V~2.9V

- 3.3V device(KFG1216U2M) : 2.7V~3.6V

• Organization

- Host Interface:16bit

• Internal BufferRAM(5K Bytes)

- 1KB for BootRAM, 4KB for DataRAM

• NAND Array

- Page Size : (2K+64)bytes

- Block Size : (128K+4K)bytes

♦ Performance

• Host Interface type

- Synchronous Burst Read

: Clock Frequency: up to 54MHz

: Linear Burst - 4, 8, 16, 32 words with wrap-around

: Continuous Sequential Burst(1K words)

- Asynchronous Random Read

: Access time of 76ns

- Asynchronous Random Write

• Programmable Read latency

• Multiple Sector Read

- Read multiple sectors by Sector Count Register(up to 4 sectors)

• Reset Mode

- Cold Reset / Warm Reset / Hot Reset / NAND Flash Reset

• Power dissipation (typical values)

- Standby current : 10uA@1.8V, 20uA@2.65V/3.3V for single, 20uA@1.8V, 40uA@2.65V/3.3V for DDP

- Synchronous Burst Read current(54MHz) : 12mA@1.8V device, 20mA@2.65V/3.3V device

- Load current : 20mA@1.8V device, 25mA@2.65V/3.3V device

- Program current: 20mA@1.8V device, 25mA@2.65V/3.3V device

- Erase current: 15mA@1.8V device, 20mA@2.65V/3.3V device

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

♦ Hardware Features

• Voltage detector generating internal reset signal from Vcc

• Hardware reset input (RP)

• Data Protection

- Write Protection for BootRAM

- Write Protection mode for NAND Flash Array

- Write protection during power-up

- Write protection during power-down

• User-controlled One Time Programmable(OTP) area

• Internal 2bit EDC / 1bit ECC

• Internal Bootloader supports Booting Solution in system

♦ Software Features

• Handshaking Feature

- INT pin: Indicates Ready / Busy of OneNAND

- Polling method: Provides a software method of detecting the Ready / Busy status of OneNAND

• Detailed chip information by ID register

♦ Packaging

• Package

- 63ball, 9.5mm x 12mm x max 1.0mmt , 0.8mm ball pitch FBGA

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OneNAND512/OneNAND1GDDP

FLASH MEMORY

2. GENERAL DESCRIPTION

OneNAND is a single-die chip with standard NOR Flash interface using NAND Flash Array. This device is comprised of logic and

NAND Flash Array and 5KB internal BufferRAM. 1KB BootRAM is used for reserving bootcode, and 4KB DataRAM is used for buff-

ering data. The operating clock frequency is up to 54MHz. This device is X16 interface with Host, and has the speed of ~76ns random

access time. Actually, it is accessible with minimum 4clock latency(host-driven clock for synchronous read), but this device adopts the

appropriate wait cycles by programmable read latency. OneNAND provides the multiple sector read operation by assigning the num-

ber of sectors to be read in the sector counter register. The device includes one block sized OTP(One Time Programmable), which

can be used to increase system security or to provide identification capabilities.

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OneNAND512/OneNAND1GDDP

FLASH MEMORY

3. PIN DESCRIPTION

Pin Name

Type

Nameand Description

Host Interface

Address Inputs

A15~A0

I

- Inputs for addresses during read operation, which are for addressing

BufferRAM & Register.

Data Inputs/Outputs

- Inputs data during program and commands during all operations, outputs data during memory array/

register read cycles.

DQ15~DQ0

I/O

Data pins float to high-impedance when the chip is deselected or outputs are disabled.

Interrupt

Notifying Host when a command has completed. It is open drain output with internal resistor(~50kohms).

After power-up, it is at hi-z condition. Once IOBE is set to 1, it does not float to hi-z condition even when

the chip is deselected or when outputs are disabled.

INT

O

Ready

RDY

CLK

WE

O

I

Indicates data valid in synchronous read modes and is activated while CE is low

Clock

CLK synchronizes the device to the system bus frequency in synchronous read mode.

The first rising edge of CLK in conjunction with AVD low latches address input.

Write Enable

I

WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge

Address Valid Detect

Indicates valid address presence on address inputs. During asynchronous read operation, all addresses

are latched on AVD’s rising edge, and during synchronous read operation, all addresses are latched on

CLK’s rising edge while AVD is held low for one clock cycle.

AVD

I

> Low : for asynchronous mode, indicates valid address ;for burst mode,

causes starting address to be latched on rising edge on CLK

> High : device ignores address inputs

Reset Pin

RP

CE

When low, RP resets internal operation of OneNAND. RP status is don’t care during power-up

and bootloading.

Chip Enable

I

CE-low activates internal control logic, and CE-high deselects the device, places it in standby state,

and places A/DQ in Hi-Z

Output Enable

OE

OE-low enables the device’s output data buffers during a read cycle.

Power Supply

VCC-Core/Vcc

Power for OneNAND Core

This is the power supply for OneNAND Core.

Power for OneNAND I/O

VCC-IO/Vccq

This is the power supply for OneNAND I/O

Vcc-IO is internally connected to Vcc-Core, thus should be connected to the same power supply.

VSS

Ground for OneNAND

etc.

Do Not Use

DNU

NC

Leave it disconnected. These pins are used for testing.

No Connection

Lead is not internally connected.

NOTE:

Do not leave power supply(VCC, VSS) disconnected.

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OneNAND512/OneNAND1GDDP

FLASH MEMORY

4. PIN CONFIGURATION

NC

VSS

OE

VSS

DQ9

DQ3

DQ5

NC

WE

RP

DQ14

DQ1

DQ11

DQ0

DQ2

AVD

A1

DQ13

VCC

Core

DQ12

DQ7

DQ8

DQ4

A12

VCC

IO

DQ10

A15

DQ15

DQ6

A9

CLK

A14

CE

NC

A7

NC

A2

A13

A11

A10

A3

A8

INT

A0

A4

A6

A5

NC

RDY

NC

(TOP VIEW, Balls Facing Down)

63ball FBGA OneNAND Chip

63ball, 9.5mm x 12mm x max 1.0mmt , 0.8mm ball pitch FBGA

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OneNAND512/OneNAND1GDDP

FLASH MEMORY

DEFINITIONS

B (capital letter)

W (capital letter)

b (lower-case letter)

ECC

Byte, 8bits

Word, 16bits

Bit

Error Correction Code

Calculated ECC

Written ECC

BufferRAM

BootRAM

ECC which has been calculated during load or program access

ECC which has been stored as data in the NAND Flash Array or in the BufferRAM

On-chip Internal Buffer consisting of BootRAM and DataRAM

A 1KB portion of the BufferRAM reserved for Bootcode buffering

A 4KB portion of the BufferRAM reserved for Data buffering

DataRAM

Memory

NAND Flash array which is embedded on OneNAND

Partial unit of page, of which size is 512B for main area and 16B for spare area data.

It is the minimum Load/Program/Copy-Back program unit while one~four sector opera-

tion is available

Sector

Possible data unit to be read from memory to BufferRAM or to be programmed to mem-

ory.

-

528B of which 512B is in main area and 16B in spare area

Data unit

- 1056B of which 1024B is in main area and 32B in spare area

- 1584B of which 1536B is in main area and 48B in spare area

- 2112B of which 2048B is in main area and 64B in spare area

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OneNAND512/OneNAND1GDDP

FLASH MEMORY

5. BLOCK DIAGRAM

DQ15~DQ0

BufferRAM

Bootloader

A15~A0

CLK

BootRAM

StateMachine

CE

OE

DataRAM

NAND Flash

Array

WE

RP

Error

Correction

Logic

AVD

INT

Internal Registers

(Address/Command/Configuration

/Status Registers)

RDY

OTP

(One Block)

- Host Interface

- BufferRAM(BootRAM, DataRAM)

- Command and status registers

- State Machine (Bootloader is included)

- Error Correction Logic

- Memory(NAND Flash Array, OTP)

NOTE:

1) At cold reset, bootloader copies boot code(1K byte size) from NAND Flash Array to BootRAM.

Figure 1. Internal Block Diagram

11

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Main area data

(512B)

Spare area data

(16B)

Page:2KB+64B

BootRAM 0

BootRAM 1

Sector

BootRAM

Sector(main area):512B

DataRAM 0_0

DataRAM 0_1

DataRAM 0_2

DataRAM 0_3

Block:

64pages

128KB+4KB

DataRAM 0

Sector(spare area):16B

Main area data

(512B)

Spare area data

(16B)

DataRAM 1_0

DataRAM 1_1

DataRAM 1_2

DataRAM 1_3

DataRAM 1

(BufferRAM)

(NAND array)

Figure 2. BufferRAM and NAND array structure

Spare Spare Spare Spare

Main area Main area Main area Main area area area area area

256W

8W

ECCm ECCm ECCm ECCs ECCs

FFh

2nd

(Note3)

Note1 Note1 Note2 Note2 Note2 Note3 Note3 Note3

Note4 Note4

1st

2nd

3rd

1st

LSB

LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB

1^stW 2^nd3^rdW 4^thW 5^thW 6^thW 7^thW 8^thW

MSB

W

NOTE:

1) The 1st word of spare area in 1st and 2nd page of every invalid block is reserved for the invalid block information by manufacturer.

Please refer to page 64 about the details.

2) These words are managed by internal ECC logic. So it is recommended that the important data like LSN(Logical Sector Number)

are written.

3) These words are reserved for the future purpose by manufacturer. These words will be dedicated to internal logic.

4) These words are for free usage.

5) The 5th, 6th and 7th words are dedicated to internal ECC logic. So these words are only readable. The other words are program-

mable by command.

6) ECCm 1st, ECCm 2nd, ECCm 3rd: ECC code for Main area data

7) ECCs 1st, ECCs 2nd: ECC code for 2nd and 3rd word of spare area.

Figure 3. Spare area of NAND array assignment

12

OneNAND512/OneNAND1GDDP

FLASH MEMORY

6.1 ADDRESS MAP For OneNAND

Address

(word order)

Address

(byte order)

Size

(total 128KB)

Division

Usage

Description

Main area

(64KB)

0000h~00FFh

0100h~01FFh

0200h~02FFh

0300h~03FFh

0400h~04FFh

0500h~05FFh

0600h~06FFh

0700h~07FFh

0800h~08FFh

0900h~09FFh

0A00h~7FFFh

8000h~8007h

8008h~800Fh

8010h~8017h

8018h~801Fh

8020h~8027h

8028h~802Fh

8030h~8037h

8038h~803Fh

8040h~8047h

8048h~804Fh

8050h~8FFFh

00000h~001FEh

00200h~003FEh

00400h~005FEh

00600h~007FEh

00800h~009FEh

00A00h~00BFEh

00C00h~00DFEh

00E00h~00FFEh

01000h~011FEh

01200h~013FEh

01400h~0FFFEh

10000h~1000Eh

10010h~1001Eh

10020h~1002Eh

10030h~1003Eh

10040h~1004Eh

10050h~1005Eh

10060h~1006Eh

10070h~1007Eh

10080h~1008Eh

10090h~1009Eh

100A0h~11FFEh

512B

BootM 0

BootM 1

BootRAM Main sector0

BootRAM Main sector1

1KB

512B

59KB

16B

DataM 0_0

DataM 0_1

DataM 0_2

DataM 0_3

DataM 1_0

DataM 1_1

DataM 1_2

DataM 1_3

Reserved

BootS 0

DataRAM Main page0/sector0

DataRAM Main page0/sector1

DataRAM Main page0/sector2

DataRAM Main page0/sector3

DataRAM Main page1/sector0

DataRAM Main page1/sector1

DataRAM Main page1/sector2

DataRAM Main page1/sector3

Reserved

4KB

59KB

32B

Spare area

(8KB)

BootRAM Spare sector0

16B

BootS 1

BootRAM Spare sector1

16B

DataS 0_0

DataS 0_1

DataS 0_2

DataS 0_3

DataS 1_0

DataS 1_1

DataS 1_2

DataS 1_3

Reserved

DataRAM Spare page0/sector0

DataRAM Spare page0/sector1

DataRAM Spare page0/sector2

DataRAM Spare page0/sector3

DataRAM Spare page1/sector0

DataRAM Spare page1/sector1

DataRAM Spare page1/sector2

DataRAM Spare page1/sector3

Reserved

16B

128B

16B

8032B

24KB

Reserved

(24KB)

9000h~BFFFh

C000h~CFFFh

D000h~EFFFh

F000h~FFFFh

12000h~17FFEh

18000h~19FFEh

1A000h~1DFFEh

1E000h~1FFFEh

24KB

8KB

Reserved

Registers

Reserved

Registers

Reserved

(8KB)

8KB

16KB

8KB

Reserved

(16KB)

16KB

8KB

Registers

(8KB)

NOTE 1) Data output is unknown while host reads a register bit of reserved area

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OneNAND512/OneNAND1GDDP

FLASH MEMORY

6.2 ADDRESS MAP For OneNAND NAND Array (word order)

Page and Sector

Size

Block

Block Address

Size

Block

Block Address

Address

Block0

Block1

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

0000h~00FFh

128KB

Block32

Block33

Block34

Block35

Block36

Block37

Block38

Block39

Block40

Block41

Block42

Block43

Block44

Block45

Block46

Block47

Block48

Block49

Block50

Block51

Block52

Block53

Block54

Block55

Block56

Block57

Block58

Block59

Block60

Block61

Block62

Block63

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

0000h~00FFh

128KB

Block2

Block3

Block4

Block5

Block6

Block7

Block8

Block9

Block10

Block11

Block12

Block13

Block14

Block15

Block16

Block17

Block18

Block19

Block20

Block21

Block22

Block23

Block24

Block25

Block26

Block27

Block28

Block29

Block30

Block31

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OneNAND512/OneNAND1GDDP

FLASH MEMORY

Page and Sector

Size

Block

Block Address

Size

Block

Block Address

Address

Block64

Block65

Block66

Block67

Block68

Block69

Block70

Block71

Block72

Block73

Block74

Block75

Block76

Block77

Block78

Block79

Block80

Block81

Block82

Block83

Block84

Block85

Block86

Block87

Block88

Block89

Block90

Block91

Block92

Block93

Block94

Block95

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0000h~00FFh

128KB

Block96

Block97

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

0071h

0072h

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

0000h~00FFh

128KB

Block98

Block99

Block100

Block101

Block102

Block103

Block104

Block105

Block106

Block107

Block108

Block109

Block110

Block111

Block112

Block113

Block114

Block115

Block116

Block117

Block118

Block119

Block120

Block121

Block122

Block123

Block124

Block125

Block126

Block127

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OneNAND512/OneNAND1GDDP

FLASH MEMORY

Page and Sector

Size

Block

Block Address

Size

Block

Block Address

Address

Block128

Block129

Block130

Block131

Block132

Block133

Block134

Block135

Block136

Block137

Block138

Block139

Block140

Block141

Block142

Block143

Block144

Block145

Block146

Block147

Block148

Block149

Block150

Block151

Block152

Block153

Block154

Block155

Block156

Block157

Block158

Block159

0080h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

0088h

0089h

008Ah

008Bh

008Ch

008Dh

008Eh

008Fh

0090h

0091h

0092h

0093h

0094h

0095h

0096h

0097h

0098h

0099h

009Ah

009Bh

009Ch

009Dh

009Eh

009Fh

0000h~00FFh

128KB

Block160

Block161

Block162

Block163

Block164

Block165

Block166

Block167

Block168

Block169

Block170

Block171

Block172

Block173

Block174

Block175

Block176

Block177

Block178

Block179

Block180

Block181

Block182

Block183

Block184

Block185

Block186

Block187

Block188

Block189

Block190

Block191

00A0h

00A1h

00A2h

00A3h

00A4h

00A5h

00A6h

00A7h

00A8h

00A9h

00AAh

00ABh

00ACh

00ADh

00AEh

00AFh

00B0h

00B1h

00B2h

00B3h

00B4h

00B5h

00B6h

00B7h

00B8h

00B9h

00BAh

00BBh

00BCh

00BDh

00BEh

00BFh

0000h~00FFh

128KB

16

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Page and Sector

Size

Block

Block Address

Size

Block

Block Address

Address

Block192

Block193

Block194

Block195

Block196

Block197

Block198

Block199

Block200

Block201

Block202

Block203

Block204

Block205

Block206

Block207

Block208

Block209

Block210

Block211

Block212

Block213

Block214

Block215

Block216

Block217

Block218

Block219

Block220

Block221

Block222

Block223

00C0h

00C1h

00C2h

00C3h

00C4h

00C5h

00C6h

00C7h

00C8h

00C9h

00CAh

00CBh

00CCh

00CDh

00CEh

00CFh

00D0h

00D1h

00D2h

00D3h

00D4h

00D5h

00D6h

00D7h

00D8h

00D9h

00DAh

00DBh

00DCh

00DDh

00DEh

00DFh

0000h~00FFh

128KB

Block224

Block225

Block226

Block227

Block228

Block229

Block230

Block231

Block232

Block233

Block234

Block235

Block236

Block237

Block238

Block239

Block240

Block241

Block242

Block243

Block244

Block245

Block246

Block247

Block248

Block249

Block250

Block251

Block252

Block253

Block254

Block255

00E0h

00E1h

00E2h

00E3h

00E4h

00E5h

00E6h

00E7h

00E8h

00E9h

00EAh

00EBh

00ECh

00EDh

00EEh

00EFh

00F0h

00F1h

00F2h

00F3h

00F4h

00F5h

00F6h

00F7h

00F8h

00F9h

00FAh

00FBh

00FCh

00FDh

00FEh

00FFh

0000h~00FFh

128KB

17

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Page and Sector

Size

Block

Block Address

Size

Block

Block Address

Address

Block256

Block257

Block258

Block259

Block260

Block261

Block262

Block263

Block264

Block265

Block266

Block267

Block268

Block269

Block270

Block271

Block272

Block273

Block274

Block275

Block276

Block277

Block278

Block279

Block280

Block281

Block282

Block283

Block284

Block285

Block286

Block287

0100h

0101h

0102h

0103h

0104h

0105h

0106h

0107h

0108h

0109h

010Ah

010Bh

010Ch

010Dh

010Eh

010Fh

0110h

0111h

0112h

0113h

0114h

0115h

0116h

0117h

0118h

0119h

011Ah

011Bh

011Ch

011Dh

011Eh

011Fh

0000h~00FFh

128KB

Block288

Block289

Block290

Block291

Block292

Block293

Block294

Block295

Block296

Block297

Block298

Block299

Block300

Block301

Block302

Block303

Block304

Block305

Block306

Block307

Block308

Block309

Block310

Block311

Block312

Block313

Block314

Block315

Block316

Block317

Block318

Block319

0120h

0121h

0122h

0123h

0124h

0125h

0126h

0127h

0128h

0129h

012Ah

012Bh

012Ch

012Dh

012Eh

012Fh

0130h

0131h

0132h

0133h

0134h

0135h

0136h

0137h

0138h

0139h

013Ah

013Bh

013Ch

013Dh

013Eh

013Fh

0000h~00FFh

128KB

18

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Page and Sector

Size

Block

Block Address

Size

Block

Block Address

Address

Block320

Block321

Block322

Block323

Block324

Block325

Block326

Block327

Block328

Block329

Block330

Block331

Block332

Block333

Block334

Block335

Block336

Block337

Block338

Block339

Block340

Block341

Block342

Block343

Block344

Block345

Block346

Block347

Block348

Block349

Block350

Block351

0140h

0141h

0142h

0143h

0144h

0145h

0146h

0147h

0148h

0149h

014Ah

014Bh

014Ch

014Dh

014Eh

014Fh

0150h

0151h

0152h

0153h

0154h

0155h

0156h

0157h

0158h

0159h

015Ah

015Bh

015Ch

015Dh

015Eh

015Fh

0000h~00FFh

128KB

Block352

Block353

Block354

Block355

Block356

Block357

Block358

Block359

Block360

Block361

Block362

Block363

Block364

Block365

Block366

Block367

Block368

Block369

Block370

Block371

Block372

Block373

Block374

Block375

Block376

Block377

Block378

Block379

Block380

Block381

Block382

Block383

0160h

0161h

0162h

0163h

0164h

0165h

0166h

0167h

0168h

0169h

016Ah

016Bh

016Ch

016Dh

016Eh

016Fh

0170h

0171h

0172h

0173h

0174h

0175h

0176h

0177h

0178h

0179h

017Ah

017Bh

017Ch

017Dh

017Eh

017Fh

0000h~00FFh

128KB

19

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Page and Sector

Size

Block

Block Address

Size

Block

Block Address

Address

Block384

Block385

Block386

Block387

Block388

Block389

Block390

Block391

Block392

Block393

Block394

Block395

Block396

Block397

Block398

Block399

Block400

Block401

Block402

Block403

Block404

Block405

Block406

Block407

Block408

Block409

Block410

Block411

Block412

Block413

Block414

Block415

0180h

0181h

0182h

0183h

0184h

0185h

0186h

0187h

0188h

0189h

018Ah

018Bh

018Ch

018Dh

018Eh

018Fh

0190h

0191h

0192h

0193h

0194h

0195h

0196h

0197h

0198h

0199h

019Ah

019Bh

019Ch

019Dh

019Eh

019Fh

0000h~00FFh

128KB

Block416

Block417

Block418

Block419

Block420

Block421

Block422

Block423

Block424

Block425

Block426

Block427

Block428

Block429

Block430

Block431

Block432

Block433

Block434

Block435

Block436

Block437

Block438

Block439

Block440

Block441

Block442

Block443

Block444

Block445

Block446

Block447

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

01B0h

01B1h

01B2h

01B3h

01B4h

01B5h

01B6h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

0000h~00FFh

128KB

20

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Page and Sector

Size

Block

Block Address

Size

Block

Block Address

Address

Block448

Block449

Block450

Block451

Block452

Block453

Block454

Block455

Block456

Block457

Block458

Block459

Block460

Block461

Block462

Block463

Block464

Block465

Block466

Block467

Block468

Block469

Block470

Block471

Block472

Block473

Block474

Block475

Block476

Block477

Block478

Block479

01C0h

01C1h

01C2h

01C3h

01C4h

01C5h

01C6h

01C7h

01C8h

01C9h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h

01D1h

01D2h

01D3h

01D4h

01D5h

01D6h

01D7h

01D8h

01D9h

01DAh

01DBh

01DCh

01DDh

01DEh

01DFh

0000h~00FFh

128KB

Block480

Block481

Block482

Block483

Block484

Block485

Block486

Block487

Block488

Block489

Block490

Block491

Block492

Block493

Block494

Block495

Block496

Block497

Block498

Block499

Block500

Block501

Block502

Block503

Block504

Block505

Block506

Block507

Block508

Block509

Block510

Block511

01E0h

01E1h

01E2h

01E3h

01E4h

01E5h

01E6h

01E7h

01E8h

01E9h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h

01F1h

01F2h

01F3h

01F4h

01F5h

01F6h

01F7h

01F8h

01F9h

01FAh

01FBh

01FCh

01FDh

01FEh

01FFh

0000h~00FFh

128KB

21

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Detailed information of Address Map (word order)

• BootRAM(Main area)

-0000h~01FFh: 2(sector) x 512byte(NAND main area) = 1KB

0000h~00FFh(512B)

BootM 0

0100h~01FFh(512B)

BootM 1

(sector 0 of page 0)

(sector 1 of page 0)

• DataRAM(Main area)

-0200h~09FFh: 8(sector) x 512byte(NAND main area) = 4KB

0200h~02FFh(512B)

DataM 0_0

0300h~03FFh(512B)

DataM 0_1

0400h~04FFh(512B)

0500h~05FFh(512B)

DataM 0_3

DataM 0_2

(sector 0 of page 0)

(sector 1 of page 0)

(sector 2 of page 0)

(sector 3 of page 0)

0600h~06FFh(512B)

DataM 1_0

0700h~07FFh(512B)

DataM 1_1

0800h~08FFh(512B)

DataM 1_2

0900h~09FFh(512B)

DataM 1_3

(sector 0 of page 1)

(sector 1 of page 1)

(sector 2 of page 1)

(sector 3 of page 1)

• BootRAM(Spare area)

-8000h~800Fh: 2(sector) x 16byte(NAND spare area) = 32B

8000h~8007h(16B)

BootS 0

8008h~800Fh(16B)

BootS 1

(sector 0 of page 0)

(sector 1 of page 0)

• DataRAM(Spare area)

-8010h~804Fh: 8(sector) x 16byte(NAND spare area) = 128B

8010h~8017h(16B)

DataS 0_0

8018h~801Fh(16B)

DataS 0_1

8020h~8027h(16B)

8028h~802Fh(16B)

DataS 0_3

DataS 0_2

(sector 0 of page 0)

(sector 1 of page 0)

(sector 2 of page 0)

(sector 3 of page 0)

8030h~8037h(16B)

DataS 1_0

8038h~803Fh(16B)

DataS 1_1

8040h~8047h(16B)

DataS 1_2

8048h~804Fh(16B)

DataS 1_3

(sector 0 of page 1)

(sector 1 of page 1)

(sector 2 of page 1)

(sector 3 of page 1)

*NAND Flash array consists of 2KB page size and 128KB block size.

22

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Spare area assignment

Equivalent to 1word of NAND Flash

Word

Address Address

Byte

Buf.

F

E

D

C

B

A

9

8

7

6

5

4

3

2

1

0

BootS 0

8000h

8001h

8002h

8003h

8004h

8005h

8006h

8007h

8008h

8009h

800Ah

800Bh

800Ch

800Dh

800Eh

800Fh

8010h

8011h

8012h

8013h

8014h

8015h

8016h

8017h

8018h

8019h

801Ah

801Bh

801Ch

801Dh

801Eh

801Fh

10000h

10002h

10004h

10006h

10008h

1000Ah

1000Ch

1000Eh

10010h

10012h

10014h

10016h

10018h

1001Ah

1001Ch

1001Eh

10020h

10022h

10024h

10026h

10028h

1002Ah

1002Ch

1002Eh

10030h

10032h

10034h

10036h

10038h

1003Ah

1003Ch

1003Eh

BI

Managed by Internal ECC logic

Reserved for the future use

Managed by Internal ECC logic

Reserved for the current and future use

ECC Code for Main area data (2^nd)

ECC Code for Spare area data (1^st)

FFh(Reserved for the future use)

ECC Code for Main area data (1^st)

ECC Code for Main area data (3^rd)

ECC Code for Spare area data (2^nd)

Free Usage

BI

BootS 1

Managed by Internal ECC logic

Reserved for the future use Managed by Internal ECC logic

Reserved for the current and future use

ECC Code for Main area data (2^nd)

ECC Code for Main area data (1^st)

ECC Code for Main area data (3^rd)

ECC Code for Spare area data (2^nd)

ECC Code for Spare area data (1^st)

FFh(Reserved for the future use)

Free Usage

BI

DataS

0_0

Managed by Internal ECC logic

Reserved for the future use Managed by Internal ECC logic

Reserved for the current and future use

ECC Code for Main area data (2^nd)

ECC Code for Main area data (1^st)

ECC Code for Main area data (3^rd)

ECC Code for Spare area data (2^nd)

ECC Code for Spare area data (1^st)

FFh(Reserved for the future use)

Free Usage

BI

DataS

0_1

Managed by Internal ECC logic

Reserved for the future use Managed by Internal ECC logic

Reserved for the current and future use

ECC Code for Main area data (2^nd)

ECC Code for Main area data (1^st)

ECC Code for Main area data (3^rd)

ECC Code for Spare area data (2^nd)

ECC Code for Spare area data (1^st)

FFh(Reserved for the future use)

Free Usage

23

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Equivalent to 1word of NAND Flash

Word

Address Address

Byte

Buf.

F

E

D

C

B

A

9

8

7

6

5

4

3

2

1

0

DataS 0_2

8020h

8021h

8022h

8023h

8024h

8025h

8026h

8027h

8028h

8029h

802Ah

802Bh

802Ch

802Dh

802Eh

802Fh

8030h

8031h

8032h

8033h

8034h

8035h

8036h

8037h

8038h

8039h

803Ah

803Bh

803Ch

803Dh

803Eh

803Fh

8040h

8041h

8042h

8043h

8044h

8045h

8046h

8047h

10040h

10042h

10044h

10046h

10048h

1004Ah

1004Ch

1004Eh

10050h

10052h

10054h

10056h

10058h

1005Ah

1005Ch

1005Eh

10060h

10062h

10064h

10066h

10068h

1006Ah

1006Ch

1006Eh

10070h

10072h

10074h

10076h

10078h

1007Ah

1007Ch

1007Eh

10080h

10082h

10084h

10086h

10088h

1008Ah

1008Ch

1008Eh

BI

Managed by Internal ECC logic

Reserved for the future use

Managed by Internal ECC logic

Reserved for the current and future use

ECC Code for Main area data (2^nd)

ECC Code for Spare area data (1^st)

FFh(Reserved for the future use)

ECC Code for Main area data (1^st)

ECC Code for Main area data (3^rd)

ECC Code for Spare area data (2^nd)

Free Usage

BI

DataS 0_3

DataS 1_0

DataS 1_1

DataS 1_2

Managed by Internal ECC logic

Reserved for the future use Managed by Internal ECC logic

Reserved for the current and future use

ECC Code for Main area data (2^nd)

ECC Code for Main area data (1^st)

ECC Code for Main area data (3^rd)

ECC Code for Spare area data (2^nd)

ECC Code for Spare area data (1^st)

FFh(Reserved for the future use)

Free Usage

BI

Managed by Internal ECC logic

Reserved for the future use Managed by Internal ECC logic

Reserved for the current and future use

ECC Code for Main area data (2^nd)

ECC Code for Main area data (1^st)

ECC Code for Main area data (3^rd)

ECC Code for Spare area data (2^nd)

ECC Code for Spare area data (1^st)

FFh(Reserved for the future use)

Free Usage

BI

Managed by Internal ECC logic

Reserved for the future use Managed by Internal ECC logic

Reserved for the current and future use

ECC Code for Main area data (2^nd)

ECC Code for Main area data (1^st)

ECC Code for Main area data (3^rd)

ECC Code for Spare area data (2^nd)

ECC Code for Spare area data (1^st)

FFh(Reserved for the future use)

Free Usage

BI

Managed by Internal ECC logic

Reserved for the future use Managed by Internal ECC logic

Reserved for the current and future use

ECC Code for Main area data (2^nd)

ECC Code for Main area data (1^st)

ECC Code for Main area data (3^rd)

ECC Code for Spare area data (2^nd)

ECC Code for Spare area data (1^st)

FFh(Reserved for the future use)

Free Usage

24

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Equivalent to 1word of NAND Flash

Word

Address Address

Byte

Buf.

F

E

D

C

B

A

9

8

7

6

5

4

3

2

1

0

DataS 1_3 8048h

8049h

10090h

10092h

10094h

10096h

10098h

1009Ah

1009Ch

1009Eh

BI

Managed by Internal ECC logic

804Ah

Reserved for the future use

Managed by Internal ECC logic

804Bh

Reserved for the current and future use

804Ch

ECC Code for Main area data (2^nd)

ECC Code for Spare area data (1^st)

FFh(Reserved for the future use)

ECC Code for Main area data (1^st)

ECC Code for Main area data (3^rd)

ECC Code for Spare area data (2^nd)

804Dh

804Eh

804Fh

Free Usage

NOTE:

- BI: Bad block Information

>Host can use complete spare area except BI and ECC code area. For example,

Host can write data to Spare area buffer except for the area controlled by ECC logic at program operation.

>In case of ’with ECC’ mode, OneNAND automatically generates ECC code for both main and spare data of memory during program operation

but does not update ECC code to spare bufferRAM during load operation.

>When loading/programming spare area, spare area BufferRAM address(BSA) and BufferRAM sector count(BSC) is chosen via Start buffer register

as it is.

25

OneNAND512/OneNAND1GDDP

FLASH MEMORY

7. Detailed address map for registers

Address

(word order)

Address

(byte order)

Host

Access

Name

Description

F000h

F001h

F002h

F003h

F004h

1E000h

1E002h

1E004h

1E006h

1E008h

Manufacturer ID

Device ID

R

Manufacturer identification

Device identification

Version identification

Data buffer size

Version ID

Data Buffer size

Boot Buffer size

Boot buffer size

Amount of

buffers

F005h

1E00Ah

R

Amount of data/boot buffers

F006h

1E00Ch

Technology

Reserved

R

-

Info about technology used for OneNAND

Reserved for user

F007h~F0FFh

1E00Eh~1E1FEh

Chip address for selection of NAND

Core in DDP & Block address

F100h

1E200h

Start address 1

R/W

F101h

F102h

1E202h

1E204h

Start address 2

Start address 3

R/W

Chip address for selection of BufferRAM in DDP

Destination Block address for Copy back program

Destination Page & Sector address for Copy

back program

F103h

1E206h

Start address 4

R/W

F104h

F105h

1E208h

1E20Ah

Start address 5

Start address 6

Start address 7

Start address 8

Reserved

-

N/A

-

N/A

F106h

1E20Ch

-

R/W

-

N/A

F107h

1E20Eh

NAND Flash Page & Sector address

Reserved for user

F108h~F1FFh

1E210h~1E3FEh

Buffer Number for the page data transfer to/from the

OneNAND and the start Buffer Address

The meaning is with which buffer to start and how many

buffers to use for the data transfer

F200h

1E400h

Start Buffer

R/W

F201h~F207h

F208h~F21Fh

F220h

1E402h~1E40Eh

1E410h~1E43Eh

1E440h

Reserved

Command

-

Reserved for user

Reserved for vendor specific purposes

Host control and OneNAND operation commands

R/W

System

Configuration 1

F221h

F222h

1E442h

1E444h

R, R/W OneNAND and Host Interface Configuration

System

Configuration 2

-

N/A

F223h~F22Fh

F230h~F23Fh

F240h

1E446h~1E45Eh

1E460h~1E47Eh

1E480h

Reserved

-

Reserved for user

-

R

Reserved for vendor specific purposes

Controller Status and result of OneNAND operation

OneNAND Command Completion Interrupt Status

Reserved for user

Controller Status

Interrupt

F241h

1E482h

R/W

-

F242h~F24Bh

1E484h~1E496h

Reserved

Start

Block Address

Start OneNAND block address to unlock in Write

Protection mode

F24Ch

F24Dh

1E498h

1E49Ah

R/W

End

Block Address

End OneNAND block address to unlock in Write

Protection mode

Write Protection

Status

Current OneNAND Write Protection status

(unlocked/locked/tight-locked)

F24Eh

1E49Ch

R

-

F24Fh~FEFFh

1E49Eh~1FDFEh

Reserved

Reserved for user

26

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Address

(word order)

Address

(byte order)

Host

Access

Name

Description

ECC Status

Register

FF00h

FF01h

FF02h

FF03h

FF04h

FF05h

FF06h

FF07h

1FE00h

1FE02h

1FE04h

1FE06h

1FE08h

1FE0Ah

1FE0Ch

1FE0Eh

R

ECC status of sector

ECC Result of

main area data

ECC error position of Main area data error for first

selected Sector

ECC Result of

spare area data

ECC error position of Spare area data error for first

selected Sector

ECC Result of

main area data

ECC error position of Main area data error for second

selected Sector

ECC Result of

spare area data

ECC error position of Spare area data error for second

selected Sector

ECC Result of

main area data

ECC error position of Main area data error for third

selected Sector

ECC Result of

spare area data

ECC error position of Spare area data error for third

selected Sector

ECC Result of

main area data

ECC error position of Main area data error for fourth

selected Sector

ECC Result of

spare area data

ECC error position of Spare area data error for fourth

selected Sector

FF08h

1FE10h

R

-

FF09h~FFFFh

1FE12h~1FFFEh

Reserved

Reserved for vendor specific purposes

27

OneNAND512/OneNAND1GDDP

FLASH MEMORY

7.1 Manufacturer ID Register (R): F000h, default=00ECh

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ManufID

ManufID (Manufacturer ID): manufacturer identification, 00ECh for Samsung Electronics Corp.

7.2 Device ID Register (R): F001h, default=refer to Table1

15

14

13

12

11

10

9

8

7

6

3

2

1

0

DeviceID

DeviceID (Device ID): Device Identification,

Table 1.

Device

DeviceID[15:0]

0024h

KFG1216Q2M

KFG1216D2M

KFG1216U2M

KFH1G16Q2M

KFH1G16D2M

KFH1G16U2M

0025h

0024h

0025h

7.3 Version ID Register (R): F002h

: N/A

28

OneNAND512/OneNAND1GDDP

FLASH MEMORY

7.4 Data Buffer size Register(R): F003h, default=0800h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DataBufSize

DataBufSize: total data buffer size in words in the memory interface

Equals two buffers of 1024 words each(2x1024=2^N, N=11)

7.5 Boot Buffer size Register (R): F004h, default=0200h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

BootBufSize

BootBufSize: total boot buffer size in words in the memory interface

(512 words=2⁹, N=9)

7.6 Amount of Buffers Register (R): F005h, default=0201h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DataBufAmount

BootBufAmount

DataBufAmount: the amount of data buffer=2(2^N, N=1)

BootBufAmount: the amount of boot buffer=1(2^N, N=0)

7.7 Technology Register (R): F006h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Tech

Tech: technology information, what technology is used for the memory

Tech

0000h

Technology

NAND SLC

NAND MLC

Reserved

0001h

0002h-FFFFh

29

OneNAND512/OneNAND1GDDP

FLASH MEMORY

7.8 Start Address1 Register (R/W): F100h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DFS

Reserved(000000)

FBA

DFS (Device Flash Core Select): it selects Flash Core in two Flash Core of DDP

FBA (NAND Flash Block Address): NAND Flash block address which will be loaded or programmed or erased.

Device

1Gb DDP

512Mb

Number of Block

FBA

1024

512

DFS[15] & FBA[8:0]

FBA[8:0]

7.9 Start Address2 Register (R/W): F101h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DBS

Reserved(000000000000000)

DBS (Device BufferRAM Select): it selects BufferRAM in two BufferRAM of DDP

CHIP 1

Comp

DBS

SRAM

BUFFER

Comp

DFS

FLASH

CORE

CE

DDP_OPT

GND

INT

CE

INT

CHIP 2

VDD

DDP_OPT

INT

CE

SRAM

DBS

BUFFER

Comp

DFS

FLASH

CORE

Figure 4. Chip selection method in DDP

7.10 Start Address3 Register (R/W): F102h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved(0000000)

FCBA

FCBA (NAND Flash Copy Back Block Address): NAND Flash destination block address which will be copy back programmed.

7.11 Start Address4 Register (R/W): F103h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

Reserved(00000000)

FCPA

FCSA

FCPA (NAND Flash Copy Back Page Address): NAND Flash destination page address in a block for copy back program operation.

FCPA(default value) = 000000

FCPA range : 000000~111111, 6bits for 64 pages

FCSA (NAND Flash Copy Back Sector Address): NAND Flash destination sector address in a page for copy back program operation.

FCSA(default value) = 00

FCSA range : 00~11, 2bits for 4 sectors

30

OneNAND512/OneNAND1GDDP

FLASH MEMORY

7.12 Start Address5 Register: F104h

: N/A

7.13 Start Address6 Register: F105h

: N/A

7.14 Start Address7 Register: F106h

: N/A

7.15 Start Address8 Register (R/W): F107h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved (00000000)

FPA

FSA

FPA (NAND Flash Page Address): NAND Flash start page address in a block for page load or copy back program or program operation.

FPA(default value)=000000

FPA range: 000000~111111 , 6bits for 64 pages

FSA (Flash Sector Address): NAND Flash start sector address in a page for read or copy back program or program operation.

FSA(default value) = 00

FSA range : 00~11, 2bits for 4 sectors

7.16 Start Buffer Register (R/W): F200h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved(0000)

BSA

Reserved(000000)

BSC

BSC (BufferRAM Sector Count): this field specifies the number of sectors to be read or programmed or copy back programmed.

Its maximum count is 4 sectors at 00(default value)value. For a single sector access, it should be programmed as value 01.

However internal RAM buffer reached to 11vaule(max value), it count up to 00 value to satisfy BSC value.

For example1) If BSA=1010, BSC=11, then selected BufferRAM are ’1010 ->1011 ->1000’

There is restriction in BootRAM case.

For example2) If BSA=0000, BSC should be 01 or 10.

If BSA=0001, BSC should be 01.

BSA (BufferRAM Sector Address): It is the place where data is placed and specifies the sector 0~3 in the internal BootRAM and DataRAM

BSA[3] is the selection bit between BootRAM and DataRAM

BSA[2] is the selection bit between DataRAM0 and DataRAM1

BSA[1:0] are the selection bits for sectors in a BufferRAM

While one of BootRAM or DataRAM0 interfaces with memory, the other RAM is inaccessible.

Main area data

Spare area data

BSA

0000

0001

BootRAM 0

BootRAM 1

Sector: (512 + 16)byte

BootRAM

DataRAM 0_0

DataRAM 0_1

DataRAM 0_2

DataRAM 0_3

1000

1001

1010

1011

DataRAM0

BSC

01

Number of Sectors

1 sector

DataRAM 1_0

DataRAM 1_1

DataRAM 1_2

DataRAM 1_3

1100

1101

1110

1111

10

2 sector

DataRAM1

11

3 sector

00

4 sector

31

OneNAND512/OneNAND1GDDP

FLASH MEMORY

7.17 Command Register (R/W): F220h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Command

Command: operation of the memory interface

Acceptable

command

CMD

Operation

during busy

0000h

0013h

Load single/multiple sector data unit into buffer

Load single/multiple spare sector into buffer

00F0h, 00F3h

0080h

Program single/multiple sector data unit from buffer

Program single/multiple spare area sector from buffer

Copy back program

00F0h, 00F3h

001Ah

00F0h, 00F3h

001Bh

00F0h, 00F3h

0023h

Unlock NAND array block(s) from start block address to end block address

Lock all NAND array block(s)

-

002Ah

-

002Ch

Lock-tight all locked block(s)

-

0094h

Block Erase

00F0h, 00F3h

00F0h

Reset NAND Flash Core

-

Reset OneNAND ¹⁾

OTP Access

00F3h

-

0075h - 0065h

00F0h, 00F3h

NOTE:

1)’Reset OneNAND’(=Hot reset) command makes the registers(except RDYpol, INTpol, IOBE bits) and NAND Flash core into default state as the warm

reset(=reset by RP pin).

This R/W register describes the operation of the OneNAND interface.

Note that all commands should be issued right after INT is turned from ready state to busy state. (i.e. right after 0 is written to INT register.) After any

command is issued and the corresponding operation is completed, INT goes back to ready state. (00F0h and 00F3h may be accepted during busy state

of some operations. Refer to the rightmost column of the command register table above.)

32

OneNAND512/OneNAND1GDDP

FLASH MEMORY

7.18 System Configuration 1 Register (R, R/W): F221h, default=40C0h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

R

RDY

pol

INT

pol

IOB

E

BW

PS

RM

BRL

BL

ECC

Reserved(0000)

RM (Read Mode): this field specifies the selection between asynchronous read mode and synchronous read mode

RM

0

Read Mode

Asynchronous read(default)

Synchronous read

1

BRL (Burst Read Latency): this field specifies the initial access latency in the burst read transfer.

BRL

000

001

010

011

100

101

110

111

Latency Cycles

8(N/A)

9(N/A)

10(N/A)

3(N/A)

4(default, min.)

5

6

7

BL (Burst Length): this field specifies the size of burst length during Sync. burst read. Wrap around and linear burst.

BL

000

Burst Length(Main)

Burst Length(Spare)

Continuous(default)

4 words

001

010

8 words

011

16 words

100

32 words

N/A

101~111

Reserved

ECC: Error Correction Operation,

0=with correction(default), 1=without correction(by-passed)

RDYpol: RDY signal polarity

0=low for ready, 1=high for ready((default)

INTpol: INT pin polarity

0=low for Interrupt pending , 1=high for Interrupt pending (default)

INTpol

INT bit of Interrupt Status Register

INT Pin output

0

1

0

1

0

IOBE: I/O buffer enable for INT and RDY signals, INT and RDY outputs are HighZ at power-up, bit 7 and 6 become valid after IOBE is set to1.

IOBE can be reset only by Cold reset or by writing 0 to bit 5 of System Configuration 1 register.

0=disable(default), 1=enable

BWPS: boot buffer write protect status,

0=locked(default)

33

OneNAND512/OneNAND1GDDP

FLASH MEMORY

7.19 System Configuration 2 Register : F222h

: N/A

7.22 Controller Status Register (R): F240h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserv Reserv

ed(0) ed(0)

TO

(0)

CB

FC

RB

WB

EB

WRc

RSTB

Reserved(000000)

CB(Controller Busy) : this bit shows the overall internal status of OneNAND

0=ready, 1=busy

FC (Fault Check): this bit shows whether host loads data from NAND Flash array into locked BootRAM or programs/erases locked block of

NAND Flash array or put invalid command into the device.

FC

0

Fault Check Result

No fault

1

Fault

WRc (Current Sector/Page Write Result): this bit shows current sector/page Program/Copy Back Program/Erase result of flash memory.

Current Sector/Page Program/CopyBack.

WRc

Program/Erase Result

0

1

Pass

Fail

TO (Time Out): time out for load/program/copy back program/erase

0=no time out(fixed)

RB(Read Busy) : this bit shows the Load operation status

0=ready(default), 1=busy

WB(Write Busy) : this bit shows the Program operation status

0=ready(default), 1=busy

EB(Erase Busy) : this bit shows the Erase operation status

0=ready(default), 1=busy

RSTB(Reset Busy) : this bit shows the Reset operation status

0=ready(default), 1=busy

34

OneNAND512/OneNAND1GDDP

FLASH MEMORY

table 2. Controller Status Register output for modes.

Controller Status Register [15:0]

WRc Reserved(0) PRp RSTB Reserved(0)

Mode

CB

1

0

FC

0

1

RB

1

0

WB

0

EB

0

1

0

TO

0

Load Ongoing

Program Ongoing

Erase Ongoing

Reset Ongoing

Load OK

0

1

0

1

0

000000

1

0

Program OK

Erase OK

0

Load Fail¹⁾

Program Fail

Erase Fail

0

Load Reset²⁾

Program Reset

Erase Reset

0

Program Lock

0

Erase Lock

0

Load Lock(Buffer Lock)

0

OTP Program

Fail(Lock)

0

1

0

000000

0

OTP Program Fail

Invalid Command

0

1

0

1

0

000000

0

NOTE: 1. ERm and/or ERs bits in ECC status register at Load Fail case is 10. (2bits error - uncorrectable)

2. ERm and ERs bits in ECC status register at Load Reset case are 00. (No error)

3. OTP Erase does not update the register and the previous value is kept.

35

OneNAND512/OneNAND1GDDP

FLASH MEMORY

7.23 Interrupt Status Register (R/W): F241h, default=8080h(after Cold reset),8010h(after Warm/Hot reset)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

INT

Reserved(0000000)

RI

WI

EI

RSTI

Reserved(0000)

Bit

Address

Bit Name

Default State

Cold Warm/Hot

Valid

States

Function

15

INT(interrupt): the master interrupt bit

- Set to ’1’ of itself when one or more of RI, WI, EI and

1

0

Interrupt Off

0->1

Interrupt Pending

RSTI is set to ’1’, or Unlock(0023h), Lock(002Ah), Lock-

tight(002Ch) or OTP access(0075h - 0065h) operation is

completed.

- Cleared to ’0’ when by writing ’0’ to this bit or by

reset(Cold/Warm/Hot reset).

’0’ in this bit means that INT pin is low status.

(This INT bit is directly wired to the INT pin on the chip.

INT pin goes low upon writing ’0’ to this bit when

INTpol is high and goes high upon writing ’0’ to this

bit when INTpol is low. )

7

6

5

4

RI(Read Interrupt):

1

0

1

0

Interrupt Off

- Set to ’1’ of itself at the completion of Load Operation

(0000h, 0013h, or boot is done.)

- Cleared to ’0’ when by writing ’0’ to this bit or by reset

(Cold/Warm/Hot reset).

0->1

Interrupt Pending

WI(Write Interrupt):

0

Interrupt Off

- Set to ’1’ of itself at the completion of Program Operation

(0080h, 001Ah, or 001Bh)

- Cleared to ’0’ when by writing ’0’ to this bit or by reset

(Cold/Warm/Hot reset).

0->1

Interrupt Pending

EI(Erase Interrupt):

0

Interrupt Off

- Set to ’1’ of itself at the completion of Erase Operation

(0094h)

- Cleared to ’0’ when by writing ’0’ to this bit or by reset

(Cold/Warm/Hot reset).

0->1

Interrupt Pending

RSTI(Reset Interrupt):

0

Interrupt Off

- Set to ’1’ of itself at the completion of Reset Operation

(00F0h, 00F3h, or warm reset is released.)

0->1

Interrupt Pending

- Cleared to ’0’ when by writing ’0’ to this bit.

7.24 Start Block Address (R/W): F24Ch, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved(0000000)

SBA

SBA (Start Block Address): Start NAND Flash block address to unlock in Write Protection mode, which preceeds ’Unlock block command’.

7.25 End Block Address (R/W): F24Dh, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Reserved(0000000)

EBA

EBA (End Block Address): End NAND Flash block address to unlock in Write Protection mode, which preceeds ’Unlock block command’. EBA should be

equal to or larger than SBA.

Device

Number of Block

SBA/EBA

512Mb

512

[8:0]

36

OneNAND512/OneNAND1GDDP

FLASH MEMORY

7.26 NAND Flash Write Protection Status (R): F24Eh, default=0002h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved(0000000000000)

US

LS

LTS

US (Unlocked Status): ’1’ value of this bit specifies that there is unlocked block in NAND Flash.

LS (Locked Status): ’1’ value of this bit specifies that there is locked block in NAND Flash.

LTS (Lock-tighten Status): ’1’ value of this bit specifies that ’Locked block(s)’ is lock-tighten.

7.27 ECC Status Register(R): FF00h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ERm3

ERs3

ERm2

ERs2

ERm1

ERs1

ERm0

ERs0

ERm (ECC Error for Main area data) & ERs (ECC Error for Spare area data)

ERm0/1/2/3 is for first/second/third/fourth selected sector main of BufferRAM, ERs0/1/2/3 is for first/second/third/fourth selected sector spare of BufferRAM.

ERm and ERs show the number of error in a sector as a result of ECC check at the load operation.

ERm and ERs bits are updated in boot loading operation, too.

ERm, ERs

ECC Status

No Error

00

01

10

11

1-bit error(correctable)

2-bit error(uncorrectable)¹⁾

Reserved

NOTE:

1. 3bits or more error detection is not supported.

7.28 ECC Result of first selected Sector Main area data Register (R): FF01h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved(0000)

ECCposWord0

ECCposIO0

7.29 ECC Result of first selected Sector Spare area data Register (R): FF02h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved(0000000000)

ECClogSector0

ECCposIO0

7.30 ECC Result of second selected Sector Main area data Register (R): FF03h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved(0000)

ECCposWord1

ECCposIO1

7.31 ECC Result of second selected Sector Spare area data Register (R): FF04h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved(0000000000)

ECClogSector1

ECCposIO1

7.32 ECC Result of third selected Sector Main area data Register (R): FF05h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved(0000)

ECCposWord2

ECCposIO2

37

OneNAND512/OneNAND1GDDP

FLASH MEMORY

7.33 ECC Result of third selected Sector Spare area data Register (R): FF06h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved(0000000000)

ECClogSector2

ECCposIO2

7.34 ECC Result of fourth selected Sector Main area data Register (R): FF07h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved(0000)

ECCposWord3

ECCposIO3

7.35 ECC Result of fourth selected Sector Spare area data Register (R): FF08h, default=0000h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved(0000000000)

ECClogSector3

ECCposIO3

NOTE:

1. ECCposWord: ECC error position address that selects one of Main area data(256words)

2. ECCposIO: ECC error position address which selects one of sixteen DQs (DQ 0~DQ 15).

3. ECClogSector: ECC error position address that selects one of the 2nd word and LSB of the 3rd word of spare area. Refer to the below table.

ECClogSector Information [5:4]

ECClogSector

Error Position

2nd word

00

01

3rd word

10, 11

Reserved

38

OneNAND512/OneNAND1GDDP

FLASH MEMORY

8 Device Operation

The device supports both a limited command based and a register based interface for performing operations on the device, reading

device ID, writing data to buffer etc. The command based interface is active in the boot partition, i.e. commands can only be written

with a boot area address. Boot area data is only returned if no command has been issued prior to the read.

8.1 Command based operation

The entire address range, except for the boot area, can be used for the data buffer. All commands are written to the boot partition. Writes outside the

boot partition are treated as normal writes to the buffers or registers. The command consists of one or more cycles depending on the command. After

completion of the command the device starts its execution. Writing incorrect information which include address and data or writing an improper command

will terminate the previous command sequence and make the device go to the ready status. The defined valid command sequences are stated in Table3.

Table 3. Command Sequences

Command Definition

Cycles

1st cycle

2nd cycle

DP¹⁾

Data

DP

Add

Data

Add

Read Data from Buffer

1

Write Data to Buffer

Reset OneNAND

1

2

Data

Add

Data

BP²⁾

Data

Add

00F0h

BP

Load Data into Buffer³⁾

Read Identification Data ⁶⁾

0000h⁴⁾

XXXXh⁵⁾

Data

Add

00E0h

BP

Data

0090h

NOTE:

1) DP(Data Partition) : DataRAM Area

2) BP(Boot Partition) : BootRAM Area [0000h ~ 01FFh, 8000h ~ 800Fh). It is locked after power-up.

3) Load Data into Buffer operation is available within a block(128KB)

4) Load 2KB unit into DataRAM0. Current Start address(FPA) is automatically incremented by 2KB unit after the load.

5) 0000h -> Data is Manufacturer ID

0001h -> Data is Device ID

6) WE toggling can terminate ’Read Identification Data’ operation.

8.1.1 Read Data from Buffer

Buffer can be read by addressing a read to a wanted buffer area

8.1.2 Write Data to Buffer

Buffer can be written by addressing a write to a wanted buffer area

8.1.3 Reset OneNAND

Reset command is given by writing 00F0h to the boot partition address. Reset will return all default values into the device.

8.1.4 Load Data into Buffer

Load Data into Buffer command is a two-cycle command. Two sequential designated command activates this operation. Sequentially writing 00E0h and

0000h to the boot partition [0000h~01FFh, 8000h~800Fh] will load one page to DataRAM0. This operation refers to FBA and FPA. FSA, BSA, and BSC

are not considered. At the end of this operation, FPA will be automatically increased by 1. So continuous issue of this command will sequentially load

data in next page to DataRAM0. This page address increment is restricted within a block. The default value of FBA and FPA is 0. Therefore, initial issue

of this command after power on will load the first page of memory, which is usually boot code.

8.1.5 Read Identification Data

Read Identification Data command consists of two cycles. It gives out the devices identification data according to the given address. The first cycle is

0090h to the boot partition address and second cycle is read from the addresses specified in Table5.

39

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Table 4. Identification data description

Address

Data Out

0000h

0001h

Manufacturer ID

Device ID

00ECh

refer to table 1

Device Bus Operations

Operation

Standby

CE

H

OE

X

WE

ADD0~15 DQ0~15

RP

CLK

X

AVD

X

High-Z

H

L

Warm Reset

X

Asynchronous Write

Asynchronous Read

Load Initial Burst Address

Burst Read

L

H

L

H

X

Add. In

Data In

Data Out

X

H

L

Add. In

L

H

L

Add. In

Burst Data

Out

L

X

Terminate Burst Read

Cycle

H

X

High-Z

X

Terminate Burst Read

Cycle via RP

Terminate Current Burst

Read Cycle and Start

New Burst Read Cycle

H

Add. In

High-Z

H

Note : L=VIL (Low), H=VIH (High), X=Don’t Care.

40

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Reset Mode

Cold Reset

At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases internal power-up reset signal

which triggers bootcode loading. Bootcode loading means that the boot loader in the device copies designated sized data(1KB) from

the beginning of memory to the BootRAM.

POR triggering level

System Power

1)

Bootcode - copy done

OneNAND

Operation

Sleep

Bootcode copy

2)

Idle

RP

High-Z

INT

3)

INT bit

0 (default)

1

IOBE bit

0 (default)

1 (default)

1

INTpol bit

Note: 1) Bootcode copy operation starts 400us later than POR activation.

The system power should reach Vcc after POR triggering level(typ. 1.5V) within 400us for valid boot code data.

2) 1K bytes Bootcode copy takes 70us(estimated) from sector0 and sector1/page0/block0 of NAND Flash array to BootRAM.

Host can read Bootcode in BootRAM(1K bytes) after Bootcode copy completion.

3) INT register goes ‘Low’ to ‘High’ on the condition of ‘Bootcode-copy done’ and RP rising edge.

If RP goes ‘Low’ to ‘High’ before ‘Bootcode-copy done’, INT register goes to ‘Low’ to ‘High’ as soon as ‘Bootcode-copy done’

Figure 5. Cold Reset Timings

41

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Warm Reset

Warm reset means that the host resets the device by RP pin, and then the device logic stops all current operation and executes inter-

nal reset operation(Note 1) synchronized with the falling edge of RP and resets current NAND Flash core operation synchronized with

the rising edge of RP. The device logic will not be reset in case RP pulses shorter than 200ns, but the device guarantees the logic

reset operation in case RP pulse is longer than 200ns. NAND Flash core reset will abort current NAND Flash Core operation. The

contents of memory cells being altered are no longer valid as the data will be partially programmed or erased. Warm reset has no

effect on contents of BootRAM and DataRAM.

CE, OE

RP

initiated by RP low

Operation or Idle internal reset operation NAND Flash core reset Idle Operation Operation or Idle

initiated by RP high

OneNAND

Operation

INT

High-Z

RDY

Figure 6. Warm Reset Timings

42

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Hot Reset

Hot reset means that the host resets the device by reset command(Note 2), and then the device logic stops all current operation and

executes internal reset operation(Note 1) , and resets current NAND Flash core operation. Hot reset has no effect on contents of

BootRAM and DataRAM.

AVD

BP(Note 3)

or F220h

A0~A15

00F0h

or 00F3h

DQ0~DQ15

CE

WE

INT

High-Z

RDY

OneNAND

Operation

Idle

Operation or Idle

OneNAND reset

Figure 7. Hot Reset Timings

NOTE:

1. Internal reset operation means that the device initializes internal registers and makes output signals go to default status and bufferRAM data are kept

unchanged after Warm/Hot reset operations.

2. Reset command : Command based reset or Register based reset

3. BP(Boot Partition) : BootRAM area[0000h~01FFh, 8000h~800Fh]

43

OneNAND512/OneNAND1GDDP

FLASH MEMORY

NAND Flash Core Reset

Host can reset NAND Flash Core operation by NAND Flash Core reset command. NAND Flash Core Reset will abort the current

NAND Flash core operation. During a NAND Flash Core Reset, the content of memory cellls being altered is no longer valid as the

data will be partially programmed or erased. NAND Flash Core Reset has an effect on neither contents of BootRAM and DataRAM

nor register values.

AVD

F220h

A0~A15

DQ0~DQ15

CE

00F0h

WE

INT

High-Z

RDY

OneNAND

Operation

Idle

Operation or Idle

NAND Flash Core reset

Figure 8. NAND Flash Core Reset Timings

44

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Table 7. Internal Register reset

Hot

Reset

(00F3h) (BP-F0)

Hot

Reset

Warn Reset

(RP)

NAND Flash

Reset(00F0h)

Internal Registers

Default Cold Reset

F000h Manufacturer ID Register (R)

00ECh

N/A

F001h Device ID Register (R)

N/A

Note3

001Eh

0800h

0200h

0201h

0000h

40C0h

0000h

-

F002h Version ID Register (rR): 54MHz

F003h Data Buffer size Register (R)

N/A

F004h Boot Buffer size Register (R)

N/A

F005h Amount of Buffers Register (R)

F006h Technology Register (R)

N/A

F100h Start Address1 Register (R/W): DFS, FBA

F101h Start Address2 Register (R/W): DBS

F102h Start Address3 Register (R/W): FCBA

F103h Start Address4 Register (R/W): FCPA, FCSA

F107h Start Address5 Register (R/W): FPA, FSA

F200h Start Buffer Register (R/W): BSA, BSC

F220h Command Register (R/W)

0000h

40C0h

0000h

8080h

0000h

0002h

0000h

O (Note1)

0000h

8010h

0000h

0002h

0000h

O (Note1)

0000h

8010h

N/A

F221h System Configuration 1 Register (R/W)

F240h Controller Status Register (R)

F241h Interrupt Status Register (R/W)

F24Ch Start Block Address (R/W)

0000h

0002h

0000h

F24Dh End Block Address (R/W)

N/A

F24Eh NAND Flash Write Protection Status (R)

FF00h ECC Status Register (R) (Note2)

FF01h ECC Result of Sector 0 Main area data Register(R)

N/A

0000h

ECC Result of Sector 0 Spare area data Register (R)

ECC Result of Sector 1 Main area data Register(R)

ECC Result of Sector 1 Spare area data Register (R)

ECC Result of Sector 2 Main area data Register(R)

ECC Result of Sector 2 Spare area data Register (R)

ECC Result of Sector 3 Main area data Register(R)

ECC Result of Sector 3 Spare area data Register (R)

FF02h

FF03h

FF04h

FF05h

FF06h

FF07h

FF08h

NOTE: 1) RDYpol, INTpol, and IOBE are reset by Cold reset. The other bits are reset by Cold/Warm/Hot reset.

2) ECC Status Register & ECC Result Registers are reset when any command is issued.

3) Refer to table 1

45

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Write Protection

Write Protection for BootRAM

At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases the internal power-up reset signal

which triggers bootcode loading. And the designated size data(1KB) is copied from the beginning of the memory to the BootRAM.

After the bootcode loading is completed, the BootRAM is always locked to protect the significant boot code from the accidental write.

Write Protection for NAND Flash array

Write Protection Modes

The device offers both hardware and software write protection features for NAND Flash array. The software write protection feature is

used by writing Lock command or Lock-tight command to command register;The 002Ah or 002Ch command is written into F220h

register. And the hardware write protection feature is used by executing cold or warm reset. The default state is locked, and all NAND

Flash array goes to locked state after cold or warm reset.

Write Protection Commands

The instant secured block protects code and data by allowing blocks to be locked or lock-tighten. The write protection scheme offers

two levels of protection. The first allows software-only control of write protection(useful for frequently changed data blocks), while the

second requires hardware interaction before locking can be changed(protects infrequently changed code blocks).

The followings summarize the locking functionality

> All blocks power-up in a locked state. Unlock commands can unlock these blocks.

>The lock-tight command makes locked block(s) lock-tighten block(s). And lock-tight state can be returned to lock state only

when cold or warm reset is asserted.

> Lock-tighten blocks offer the user an additional level of write protection beyond that of a regular locked block.

Lock-tighten block can’t have it’s state changed by software, it can be changed by warm reset or cold reset.

> Unlock start and end block address are reflected immediately to the device only when the unlock command is issued, and

NAND Flash write protection status register is also updated at that time.

> Unlocked blocks can be programmed or erased.

> Only one consecutive area can be released to unlock state from lock state, i.e unlocking multi area is not available.

> Partial block lock (a range) is not available, i.e lock operation is only available for all blocks.

Write Protection Status

The device current Write Protection status can be read in NAND Flash Write Protection Status Register(F24Eh). There are three bits

- US, LS, LTS -, which are not cleared by hot reset. These Write Protection status registers are updated when Write Protection com-

mand is entered.

The followings summarize locking status.

example1)

In default, [2:0] values are 010.

-> If host executes unlock block operation, then [2:0] values turn to 110.

-> If host executes lock-tight block operation, then [2:0] values turn to 101.

example2)

If host executes lock block operation, then [2:0] values turn to 010.

-> If host executes lock-tight block operation, then [2:0] values turn to 001.

-> If cold or warm reset is entered, then [2:0] values turn to 010.

46

OneNAND512/OneNAND1GDDP

FLASH MEMORY

RP pin: High

&

Start block address End block address

+Unlock block Command (Note 1)

Lock

unlock

RP pin: High

&

RP pin: High

&

Lock

Start block address End block address

+Unlock block Command

Lock block Command

or

Cold reset or

Warm reset

Lock

Power On

RP pin: High

&

Cold reset or

Warm reset

Lock-tight block Command

Lock

unlock

Lock

RP pin: High

&

Lock-tight

unlock

Lock-tight block Command

Lock-tight

NOTE:

1. Unlock range(from Start block address to End block address) can be modified by unlock command sequence(Start block address+End block address).

Figure 9. State diagram of NAND Flash Write Protection

47

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Locked

> Command Sequence : Lock block command(002Ah)

> All blocks default to locked after Cold reset or Warm reset

> Partial block lock (a range) is not available ; Lock block operation

is only available for all blocks

> Unlocked blocks can be locked by using the Lock block

command and a lock block’s status can be changed to

unlock or lock-tight using the appropriate software commands

Unlocked

> Command Sequence :

Start block address+End block address+Unlock block command

(0023h)

> Unlocked block can be programmed or erased

> An unlocked block’s status can be changed to the locked or

lock-tighten state using the appropriate software command

> Only one sequential area can be released to unlock state from

lock state ; Unlocking multi area is not available

Lock-tighten

> Command Sequence : Lock-tight block command(002Ch)

> Lock-tighten blocks offer the user an additional level of write

protection beyond that of a regular lock block. A block that

is lock-tighten cannot have it’s state change by software,

only by Cold or Warm reset.

> Only locked blocks can be lock-tighten by Lock-tight command.

> Lock-tighten blocks revert to the locked state at Cold or Warm

reset

> Lock-tighten area does not change with any command;

when new unlock command is issued including the lock-tighten

area, new unlocked command is ignored.

Figure 10. Operations of NAND Flash Write Protection

48

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Load Operation

The load operation is initiated by setting up the start address from which the data is to be loaded. The load command is issued in

order to initiate the load. The device transfers the data from NAND Flash array into the BufferRAM. The ECC is checked and any

detected and corrected error is reported in the status response as well as any unrecoverable error. When the BufferRAM has been

filled an interrupt is issued to the host in order to read the contents of the BufferRAM. The read from the BufferRAM consist of asyn-

chronous read mode or synchronous read mode. The status information related to the BufferRAM fill operation can be checked by

the host if required.

The device provides dual data buffer memory architecture. The device is capable of data-read operation from one data buffer and

data-load operation to the other data buffer simultaneously. Refer to the information for more details in "Read while Load operation".

Start

Write ’DFS*, FBA’ of Flash

Add: F100h DQ=FBA

Write ’FPA, FSA’ of Flash

Add: F107h DQ=FPA, FSA

Write ’BSA, BSC’ of DataRAM

Add: F200h DQ=BSA, BSC

Select DataRAM for DDP

Add: F101h DQ=DBS

Write 0 to interrupt register

Add: F241h DQ=0000h

Write ’Load’ Command

Add: F220h

DQ=0000h or 0013h

Wait for INT register

low to high transition

Add: F241h DQ[15]=INT

Host reads data from

DataRAM

Read completed

* DBS, DFS is for DDP

Figure 11. Load operation flow-chart

49

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Read Operation

The device has two read configurations ; Asynchronous read and Synchronous burst read.

The initial state machine makes the device to be automatically entered into asynchronous read mode to prevent the memory content

from spurious altering upon device power up or after a hardware reset. No commands are required to retrieve data in asynchronous

mode. The synchronous mode will be enabled by setting RM bit of System configuration1 register to Synchronous read mode.

Asynchronous Read Mode (RM = 0)

For the asynchronous read mode a valid address should be asserted on ADD0-ADD15, while driving AVD and CE to VIL. WE

should remain at VIH . The data will appear on ADD15-ADD0. Address access time (tAA) is equal to the delay from valid addresses to

valid output data. The chip enable access time(tCE) is the delay from the falling edge of CE to valid data at the outputs. The output

enable access time(tOE) is the delay from the falling edge of OE to valid data at the output.

Synchronous (Burst) Read Mode (RM = 1)

The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the host

should determine how many clock cycles are desired for the initial word(tIAA) of each burst access using BRL bit of System configura-

tion 1 register. The registers also can be read during burst read mode by using AVD signal with a address. To initiate the synchro-

nous read again, a new address during CE low toggle is needed after the host has completed status reads or the device has

completed the program or erase operation.

Continuous Linear Burst Read

The initial word is output tIAA after the rising edge of the first CLK cycle. Subsequent words are output tBA after the rising edge of each

successive clock cycle, which automatically increments the internal address counter. The RDY output indicates this condition to the

system by pulsing low. The device will continue to output sequential burst data, wrapping around after it reaches the designated loca-

tion(See Figure 12 for address map information) until the system asserts CE high, RP low or AVD low in conjunction with a new

address. The cold/warm/hot reset or asserting CE high or WE low pulse terminate the burst read operation.

If the device is accessed synchronously while it is set to asynchronous read mode, it is possible to read out the first data

without problems.

Division

Add.map(word order)

0000h~01FFh

0200h~05FFh

0600h~09FFh

0A00h~7FFFh

8000H~800Fh

8010h~802Fh

8030h~804Fh

8050h~8FFFh

9000h~EFFFh

F000h~FFFFh

BootM(0.5Kw)

BufM 0(1Kw)

BufM 1(1Kw)

Reserved Main

BootS(16w)

Buffer0

Not Support

Buffer1

N/A Reg.

Not Support

Buffer0

Buffer1

N/A Reg.

Reg.

BufS 0(32w)

BufS 1(32w)

Reserved Spare

Reserved Reg.

Register(4Kw)

* Reserved area is not available on Synchronous read

Figure 12. The boundary of synchronous read

50

OneNAND512/OneNAND1GDDP

FLASH MEMORY

4-, 8-,16-, 32- Word Linear Burst Read

As well as the Continuous Linear Burst Mode, there are four(4 & 8 & 16 & 32 word) (Note1) linear wrap-around mode, in which a fixed

number of words are read from consecutive addresses. When the last word in the burst mode is reached, assert /CE and /OE high to

terminate the operation. In these modes, the start address for burst read can be any address of address map.

(Note 1) 32 word linear burst read isn’t available on spare area BufferRAM

Table 6. Burst Address Sequences

Burst Address Sequence(Decimal)

Start

Addr.

Continuous Burst

0-1-2-3-4-5-6...

1-2-3-4-5-6-7...

2-3-4-5-6-7-8...

4-word Burst

0-1-2-3-0...

1-2-3-0-1...

2-3-0-1-2...

8-word Burst

16-word Burst

32-word Burst

0

1

2

0-1-2-3-4-5-6-7-0...

1-2-3-4-5-6-7-0-1...

2-3-4-5-6-7-0-1-2...

0-1-2-3-4-....-13-14-15-0... 0-1-2-3-4-....-29-30-31-0...

1-2-3-4-5-....-14-15-0-1...

2-3-4-5-6-....-15-0-1-2...

1-2-3-4-5-....-30-31-0-1...

2-3-4-5-6-....-31-0-1-2...

Wrap

around

.

Programmable Burst Read Latency

The programmable burst read latency feature indicates to the device the number of additional clock cycles that must elapse after

AVD is driven active before data will be available. Upon power up, the number of total initial access cycles defaults to four clocks. The

number of total initial access cycles is programmable from four to seven cycles.

Rising edge of the clock cycle following last read latency

triggers next burst data

CE

CLK

-1

5

6

0

1

2

3

4

AVD

tBA

Valid

A0:

A15

Address

DQ0:

DQ15

D6

D7

D0

D1

D2

D3

D7

D0

tIAA

tRDYS

OE

Hi-Z

tRDYA

RDY

Figure 13. Example of 4clock Burst Read Latency

Handshaking

The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word

of burst data is ready to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable

burst read latency configuration.(See "System Configuration1 Register" for details.) The rising edge of RDY which is derived from 1

clock ahead of data fetch clock indicates the initial word of valid burst data.

Output Disable Mode

When the CE or OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state.

51

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Program Operation

The device can be programmed in data unit. Programming is writing 0's into the memory array by executing the internal program rou-

tine. In order to perform the Internal Program Routine, command sequence is necessary. First, host sets the address of the Buffer-

RAM and the memory location and loads the data to be programmed into the BufferRAM. Second, program command initiates the

internal program routine. During the execution of the Routine, the host is not required to provide further controls or timings. During the

Internal Program Routine, commands except reset command written to the device will be ignored.

Note that a reset during a program operation will cause data corruption at the corresponding location.

The device provides dual data buffer memory architecture. The device is capable of data-write operation from host to one of data buff-

ers during program operation from anther data buffer to Flash simultaneously. Refer to the information for more details in "Read while

Load operation".

Write 0 to interrupt register

Start

Add: F241h DQ=0000h

Select DataRAM for DDP¹⁾

Write ’Program’ Command

Add: F101h DQ=DBS*

Add: F220h

DQ=0080h or 001Ah

Write Data into DataRAM²⁾

ADD: DP DQ=Data-in

Wait for INT register

low to high transition

NO

Data Input

Add: F241h DQ[15]=INT

Completed?

Read Controller

Status Register

YES

Write ’DFS*, FBA’ of Flash

Add: F100h DQ=DFS*’, FBA

Add: F240h DQ[10]=WRC

Write ’FPA, FSA’ of Flash

Add: F107h DQ=FPA, FSA

DQ[10]=0?

YES

NO

Program completed

Program Error

Write ’BSA, BSC’ of DataRAM

Add: F200h DQ=BSA, BSC

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

*

* DBS, DFS is for DDP

Note 1) This must happen before data input

2) Data input could be done anywhere between "Start" and "Write Program Command".

Figure 14. Program operation flow-chart

52

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-

nificant bit) pages of the block. Random page address programming is prohibited.

(64)

Page 63

Page 31

Page 63

Page 31

:

(1)

:

(32)

:

(3)

(2)

(1)

Page 2

Page 1

Page 0

(3)

(32)

(2)

Page 2

Page 1

Page 0

Data register

From the LSB page to MSB page

DATA IN: Data (1)

Data (64)

Ex.) Random page program (Prohibition)

DATA IN: Data (1)

Data (64)

53

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Copy-back Program Operation

The copy-back program is configured to quickly and efficiently rewrite data stored in one page by sector unit(1/2/3/4 sector) without

utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system perfor-

mance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be

copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read

without serial access and copying-program with the address of destination page.

Write ’Copy-back Program’

command

Start

Add: F220h DQ=001Bh

Write ’DFS*, FBA’ of Flash

Add: F100h DQ=DFS*, FBA

Wait for INT register

low to high transition

Write ’FPA, FSA’ of Flash

Add: F107h DQ=FPA, FSA

Add: F241h DQ[15]=INT

Read Controller

Status Register

Write ’FCBA’ of Flash

Add: F102h DQ=FCBA

Add: F240h DQ[10]=WRc

Write ’FCPA, FCSA’ of Flash

Add: F103h DQ=FCPA, FCSA

DQ[10]=0?

YES

NO

Select DataRAM for DDP

Add: F101h DQ=DBS*

Copy back completed

Copy back Error

Write ’BSA, BSC’ of DataRAM

Add: F200h DQ=BSA, BSC ¹⁾

Write 0 to interrupt register

Add: F241h DQ=0000h

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

*

* DBS, DFS is for DDP

Note 1) Selected DataRAM by BSA & BSC is used for Copy back operation, so previous data is overwritten.

Figure 15. Copy back program operation flow-chart

54

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Copy-Back Program Operation with Random Data Input

The Copy-Back Program Operation with Random Data Input in OneNAND consists of 2 phase, Load data into DataRAM, Modify data

and program into designated page. Data from the source page is saved in one of the on-chip DataRAM buffers and modified by the

host, then programmed into the destination page.

As shown in the flow chart, data modification is possible upon completion of load operation. ECC is also available at the end of load

operation. Therefore, using hardware ECC of OneNAND, accumulation of 1 bit error can be avoided.

Copy-Back Program Operation with Random Data Input will be effectively utilized at modifying certain bit, byte, word, or sector of

source page to destination page while it is being copied.

Start

NO

DQ[10]=0?

YES

Map Out

Write ’FBA’ of Flash

Add: F100h DQ=FBA

Random Data Input

Write ’FPA, FSA’ of Flash

Add: F107h DQ=FPA, FSA

Add: Random Address in

Selected DataRAM

DQ=Data

Write ’BSA, BSC’ of DataRAM

Add: F200h DQ=BSA, BSC

Write ’FBA’ of Flash

Add: F100h DQ=FBA

Write 0 to interrupt register

Add: F241h DQ=0000h

Write ’FPA, FSA’ of Flash

Add: F107h DQ=FPA, FSA

Write ’Load’ Command

Write 0 to interrupt register

Add: F241h DQ=0000h

Add: F220h

DQ=0000h or 0013h

Write ’Program’ Command

Wait for INT register

low to high transition

Add: F220h

DQ=0080h or 001Ah

Add: F241h DQ[15]=INT

Wait for INT register

low to high transition

Read Controller

Status Register

Add: F241h DQ[15]=INT

Add: F240h DQ[10]=Error

Read Controller

Status Register

Add: F240h DQ[10]=Error

DQ[10]=0?

YES

NO

Copy back Error

Copy back completed

Figure 16. Copy-Back Program Operation with Random Data Input Flow Chart

55

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Erase Operation

The device can be erased in block unit. To erase a block is to write 1′s into the desired memory block by executing the Internal Erase

Routine. In order to perform the Internal Erase Routine, command sequence is necessary. First, host sets the block address of the

memory location. Second, erase command initiates the internal erase routine. During the execution of the Routine, the host is not

required to provide further controls or timings. During the Internal erase routine, commands except reset command written to the

device will be ignored.

Note that a reset during a erase operation will cause data corruption at the corresponding location.

Start

Write ’DFS*, FBA’ of Flash

Add: F100h DQ=DFS*, FBA

Write 0 to interrupt register

Add: F241h DQ=0000h

Write ’Erase’ Command

Add: F220h DQ=0094h

Wait for INT register

low to high transition

Add: F241h DQ=[15]=INT

Read Controller

Status Register

: If erase operation results in an error, map out

the failing block and replace it with another block.

Add: F240h DQ[10]=WRc

*

DQ[10]=0?

YES

NO

Erase completed

Erase Error

* DFS is for DDP

Figure 17. Erase operation flow-chart

56

OneNAND512/OneNAND1GDDP

FLASH MEMORY

OTP Operation

The device supports one block sized OTP area, which can be read and programmed with the same sequence as normal operation.

But this OTP block could not be erased. This block is separated from NAND Flash Array, so it could be accessed by OTP Access

command instead of FBA. If user wants to exit from OTP access mode, Cold, Warm and Hot Reset operation should be done.

OTP area is one block size(128KB, 64pages) and is divided by two areas. The first area from page 0 to page 9, total 10pages, is

assigned for user and the second area from page 10 to page 63, total 54pages, are occupied for the device manufacturer. The man-

ufacturer area is programmed prior to shipping, so this area could not be used by user.

This block is fully guaranteed to be a valid block.

OTP Block Page Allocation Information

Area

User

Page

Use

0 ~ 9 (10 pages)

10 ~ 63 (54 pages)

Designated as user area

Used by the device manufacturer

Manufacturer

Page:2KB+64B

Sector(main area):512B

Sector(spare area):16B

One Block:

64pages

128KB+4KB

Reserved Area :

54pages

page 10 to page 63

User Area :

10pages

page 0 to page 9

Figure 18. OTP area structure and assignment

57

OneNAND512/OneNAND1GDDP

FLASH MEMORY

OTP Load(OTP Access+Load NAND)

OTP area is separated from NAND Flash Array, so it is accessed by OTP Access command instead of FBA. The content of OTP

could be loaded with the same sequence as normal load operation after being accessed by the command. If user wants to exit from

OTP access mode, Cold, Warm, Hot or NAND Flash Core Reset operation should be done.

Start

Write 0 to interrupt register

Add: F241h DQ=0000h

Write ’DFS*, FBA’ of Flash¹⁾

Add: F100h DQ=DFS*’, FBA

Write ’Load’ Command

Add: F220h

DQ=0000h or 0013h

Write 0 to interrupt register

Add: F241h DQ=0000h

Wait for INT register

low to high transition

Write ’OTP Access’ Command

Add: F220h DQ=0075h

Add: F241h DQ[15]=INT

Write ’OTP Access’ Command

Add: F220h DQ=0065h

Host reads data from

DataRAM

Wait for INT register

low to high transition

OTP Load completed

Add: F241h DQ[15]=INT

Do Cold/Warm/Hot

/NAND Flash Core Reset

Write ’FPA, FSA’ of Flash¹⁾

Add: F107h DQ=FPA, FSA

OTP Exit

Write ’BSA, BSC’ of DataRAM

Add: F200h DQ=BSA, BSC

Select DataRAM for DDP

Add: F101h DQ=DBS

* DBS, DFS is for DDP

Note 1) FBA(NAND Flash Block Address) could be omitted or any address.

Figure 19. OTP load operation flow-chart

58

OneNAND512/OneNAND1GDDP

FLASH MEMORY

OTP Programming(OTP Access+Program NAND)

OTP area could be programmed with the same sequence as normal program operation after being accessed by the command. But in

case of OTP area program, OTP area is not a real OTP area but can be programmed more than once. And 2 command sequence is

used to avoid the accidental write. To avoid the accidental write, FBA should point the unlocked area address among NAND Flash

Array address map even though OTP area is separated from NAND Flash Array.

Write ’FBA’ of Flash

Start

Add: F100h DQ=FBA³⁾

Write ’DFS*, FBA’ of Flash²⁾

Add: F100h DQ=DFS*’, FBA

Write ’FPA, FSA’ of Flash

Add: F107h DQ=FPA, FSA

Write 0 to interrupt register

Add: F241h DQ=0000h

Write ’BSA, BSC’ of DataRAM

Add: F200h DQ=BSA, BSC

Write ’OTP Access’ Command

Add: F220h DQ=0075h

Write 0 to interrupt register

Add: F241h DQ=0000h

Write ’OTP Access’ Command

Add: F220h DQ=0065h

Write Program command

Add: F220h

DQ=0080h or 001Ah

Wait for INT register

low to high transition

Wait for INT register

low to high transition

Add: F241h DQ[15]=INT

Select DataRAM for DDP

Add: F101h DQ=DBS*

OTP Programming completed

Write Data into DataRAM¹⁾

Add: DP DQ=Data-in

Do Cold/Warm/Hot

/NAND Flash Core reset

NO

Data Input

Completed?

OTP Exit

* DBS, DFS is for DDP

Note 1) FBA(NAND Flash Block Address) could be any address.

2) Data input could be done anywhere between "Start" and "Write Program Command".

3) FBA should point the unlocked area address among NADND Flash Array address map.

Figure 20. OTP program operation flow-chart

59

OneNAND512/OneNAND1GDDP

FLASH MEMORY

60

OneNAND512/OneNAND1GDDP

FLASH MEMORY

61

OneNAND512/OneNAND1GDDP

FLASH MEMORY

ECC Operation

While the device transfers data from BufferRAM to NAND Flash Array Page Buffer for Program Operation, the device hiddenly gener-

ates ECC(24bits for main area data and 10bits for 2nd and 3rd word data of each sector spare area) and while Load operation, hid-

denly generates ECC and detects error number and position and corrects 1bit error. ECC is updated by the device automatically.

After Load Operation, host can know whether there is error or not by reading ’ECC Status Register’(refer to ECC Status Register

Table). In addition, OneNAND supports 2bit EDC even though it is little probable that 2bit error occurs. Hence, it is not recommeded

that Host reads ’ECC Status Register’ for checking ECC error because the built-in Error Correction Logic of OneNAND finds out and

corrects ECC error.

When the device loads NAND Flash Array main and sprea area data with ECC operation, the device does not place the newly gener-

ated ECC for main and spare area into the buffer but places ECC which was generated and written in program operation into the

buffer.

Ecc operation is done during the boot loading operation.

ECC Bypass Operation

ECC bypass operation is set by 9th bit of System Configuration 1 register. In ECC Bypass operation, the device neither generates

ECC result which indicates error position nor updates ECC code to NAND Flash arrary spare area in program operation(refer to ECC

Result Register Tables). During Load operation, the on-chip ECC engine does not generate a new ECC internally and the values of

ECC Status and Result Registers are invalid. Hence, in ECC Bypass operation, the error cannot be detected and corrected by Mux-

OneNAND itself. ECC Bypass operation is not recommended to host.

Table 7. ECC Code & Result Status by ECC operation mode

Program operation

Load operation

Operation

ECC Code Update to NAND ECC Code at BufferRAM Spare ECC Status & Result Update

1bit Error

Flash Array Spare Area

Area

to Registers

Pre-written ECC code⁽¹⁾loaded

Pre-written code loaded

ECC operation

ECC bypass

Update

Correct

Not update

Invalid

Not correct

NOTE:

1. Pre-written ECC code : ECC code which is previously written to NAND Flash Spare Area in program operation.

62

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Data Protection during Power Down

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector

disables all functions whenever Vcc is below about 1.3V. RP pin provides hardware protection and is recommended to be kept at VIL

before power-down.

VCC

typ. 1.3V

0V

RP

INT

NAND Flash Core

Write Protected

OneNAND

Operation

Idle

OneNAND Reset

Figure 21. Data Protection during Power Down

63

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Technical Notes

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-

mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality

level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-

mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design

must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guar-

anteed to be a valid block.

Identifying Invalid Block(s)

All device locations are erased(FFFFh) except locations where the invalid block(s) information is written prior to shipping. The invalid

block(s) status is defined by the 1st word in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid

block has non-FFFFh data at the 1st word of sector0 spare area. Since the invalid block information is also erasable in most cases, it

is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid

block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart. Any

intentional erasure of the original invalid block information is prohibited.

Start

Set Block Address = 0

Increment Block Address

Check "FFFFh" at the 1st word

of sector0 spare area at the 1st

*

and 2nd page in the block

No

Check "

Create (or update)

Invalid Block(s) Table

FFFFh" ?

Yes

Last Block ?

Yes

End

Figure 22. Flow chart to create invalid block table.

64

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Technical Notes (Continued)

Error in write or load operation

Within its life time, additional invalid blocks may develop with the device. Refer to the qualification report for the actual data.The fol-

lowing possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after

erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of

the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and

reprogramming the current target data and copying the rest of the replaced block.

Failure Mode

Erase Failure

Detection and Countermeasure sequence

Status Read after Erase --> Block Replacement

Status Read after Program --> Block Replacement

Error Correction by ECC mode of the device

Write

Load

Program Failure

Single Bit Failure

Block Replacement

Block A

1st

1

{

(n-1)th

nth

an error occurs.

Data Buffer0 of the device

(page)

1

Data Buffer1 of the device

Block B

(assuming maintain the nth page data)

1st

2

{

(n-1)th

nth

(page)

When an error happens in the nth page of the Block ’A’ during program operation.

* Step1

Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’ via data buffer0.

* Step2

Copy the nth page data of the Block ’A’ in the data buffer1 to the nth page of another free block. (Block ’B’)

Do not further erase or program Block ’A’ but create an ’invalid Block’ table or other appropriate scheme.

65

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Technical Notes (Continued)

OneNAND DDP Technical Note

DDP Chip Selection Register

OneNAND DDP configuration does not require additional pins. NAND Flash Block Address is consecutive between LSB and MSB

chips. As seen in the figure below, the LSB Block Address ends at 01FFh(Block 511) and the MSB Block Address begins at

1000h(Block 512). The Device Flash Core Select (DFS) of Start Address 1 Register and the Device BufferRAM Select (DBS) of Start

Address 2 Register are used to select the desired LSB or MSB Flash Core and BufferRAM in the DDP.

Start Address Register1

LSB Chip

Block 0

0000h

Block 1

Block 510

Block 511

01FFh

MSB Chip

Block 512

1000h

Block 513

Block 1022

Block 1023

11FFh

Figure 23. Flash Block Address Map in DDP

Start Address1 Register (R/W): F100h, default=0000h

This Read/Write register is used to select the Flash Core of the LSB or MSB device (DFS).

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DFS

Reserved(000000)

FBA

DFS (Device Flash Core Select): it selects Flash Core in two Flash Core of DDP

FBA (NAND Flash Block Address): NAND Flash block address which will be read or programmed or erased.

Chip

Start Address1 Register

0000h ~ 01FFh

Block Number

LSB Chip

MSB Chip

Block0 ~ Block511

1000h ~ 11FFh

Block512 ~ Block1023

Start Address2 Register (R/W): F101h, default=0000h

This Read/Write register is used to select the BufferRAM of the LSB or MSB device (DBS).

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DBS

Reserved(000000000000000)

DBS (Device BufferRAM Select): it selects BufferRAM in two BufferRAM of DDP

66

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Technical Notes (Continued)

DDP Chip Selection Operation

Flash Core Array Selection for Unlock Operation

The LSB and MSB Flash Cores in a OneNAND DDP configuration power-up in a locked state and must be unlocked before opera-

tion. Set DFS and DBS = "0" to select the LSB Chip or "1" to select the MSB chip, then issue Unlock Command Sequence: Start block

address+End block address+Unlock block command (0023h).

Note that the LSB and MSB chips must each be unlocked. The default state for Device BufferRAM Select (DBS) and Device Flash

Core Select (DFS) = "0", which selects the LSB chip. For more information on lock operations.

. LSB Chip Case

Unlock

Flash Array is locked at Power up

Set DBS=0 to select BufferRAM of LSB chip

Set DBS=1 to select BufferRAM of MSB chip

Set DFS=0 to select BufferRAM of LSB chip

Set DFS=1 to select BufferRAM of MSB chip

. MSB Chip Case

Flash Array is locked at Power up

BufferRAM Selection for Read/Write Operation

The LSB and MSB chip BufferRAMs operate independently. Select the desired LSB or MSB chip and then execute a BufferRAM

Read/Write operation. The default state for Device BufferRAM Select (DBS) and Device Flash Core Select (DFS) = "0", which selects

the LSB chip.

For more information on read/write operations.

. LSB Chip Case

Set DBS=0 to select BufferRAM of LSB chip

BufferRAM Read/Write

. MSB Chip Case

Set DBS=1 to select BufferRAM of MSB chip

BufferRAM and Flash Core Selection for Load/Program/Erase/Copy-back/Cache Program/Write Protect Operation

The LSB and MSB chip BufferRAMs operate independently. Select the desired LSB or MSB chip and then execute a BufferRAM

Read/Write operation. The default state for Device BufferRAM Select (DBS) and Device Flash Core Select (DFS) = "0", which selects

the LSB chip.

For more information on read/write operations.

. LSB Chip Case

Load/Program/Erase/Copy-back

Cache Program/Write Protection Commands

Set DFS=0 to select BufferRAM of LSB chip

Set DFS=1 to select BufferRAM of MSB chip

Set DBS=0 to select BufferRAM of LSB chip

. MSB Chip Case

Load/Program/Erase/Copy-back

Cache Program/Write Protection Commands

Set DBS=1 to select BufferRAM of MSB chip

67

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Technical Notes (Continued)

Boot Sequence

One of the best features OneNAND has is that it can be a booting device itself since it contains an internally built-in boot loader

despite the fact that its core architecture is based on NAND Flash. Thus, OneNAND does not make any additional booting device

necessary for a system, which imposes extra cost or area overhead on the overall system.

As the system power is turned on, the boot code originally stored in NAND Flash Arrary is moved to BootRAM automatically and then

fetched by CPU through the same interface as SRAM’s or NOR Flash’s if the size of the boot code is less than 1KB. If its size is larger

than 1KB and less than or equal to 3KB, only 1KB of it can be moved to BootRAM automatically and fetched by CPU, and the rest of

it can be loaded into one of the DataRAMs whose size is 2KB by Load Command and CPU can take it from the DataRAM after finish-

ing the code-fetching job for BootRAM. If its size is larger than 3KB, the 1KB portion of it can be moved to BootRAM automatically

and fetched by CPU, and its remaining part can be moved to DRAM through two DataRAMs using dual buffering and taken by CPU

to reduce CPU fetch time.

A typical boot scheme usually used to boot the system with OneNAND is explained at Figure 24 and Figure 25. In this boot scheme,

boot code is comprised of BL1, where BL stands for Boot Loader, BL2, and BL3. Moreover, the size of the boot code is larger than

3KB (the 3rd case above). BL1 is called primary boot loader in other words. Here is the table of detailed explanations about the func-

tion of each boot loader in this specific boot scheme.

Boot Loaders in OneNAND

Boot Loader

BL1

Description

Moves BL2 from NAND Flash Array to DRAM through two DataRAMs using dual buffering

Moves OS image (or BL3 optionally) from NAND Flash Array to DRAM through two DataRams using dual buffering

Moves or writes the image through USB interface

BL2

BL3 (Optional)

NAND Flash Array of OneNAND is divided into the partitions as described at Figure 24 to show where each component of code is

located and how much portion of the overall NAND Flash Array each one occupies. In addition, the boot sequence is listed below and

depicted at Figure 25.

Boot Sequence :

1. Power is on

BL1 is loaded into BootRAM

2. BL1 is executed in BootRAM

BL2 is loaded into DRAM through two DataRams using dual buffering by BL1

3. BL2 is executed in DRAM

OS image is loaded into DRAM through two DataRams using dual buffering by BL2

4. OS is running

68

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Technical Notes (Continued)

Block 511

Reservoir

Partition 6

Partition 5

Sector 0 Sector 1 Sector 2 Sector 3

File System

Page 63

Page 62

Block 162

:

Os Image

NBBLL33

Partition 4

Partition 3

Block 2

Block 1

Block 0

Page 2

Page 1

Page 0

NBBLL11

NBBLL22

BL1

Figure 24. Partition of NAND Flash array

Reservoir

File System

Os Image

3

Data Ram 1

Data Ram 0

Os Image

BL 2

Boot Ram(BL 1)

BL1

BL2

2

1

NAND Flash Array

Internal BufferRAM

OneNAND

DRAM

NOTE:

and

can be copied into DRAM through two DataRAMs using dual buffering

3

2

Figure 25. OneNAND Boot Sequence

69

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Technical Notes (Continued)

Methods of Determining Interrupt Status

There are two methods of determining Interrupt Status on the OneNAND. Using the INT pin or monitoring the Interrupt Status Regis-

ter Bit.

The OneNAND INT pin is an output pin function used to notify the Host when a command has been completed. This provides a hard-

ware method of signaling the completion of a program, erase, or load operation.

In its normal state, the INT pin is high if the INT polarity bit is default. Before a command is written to the command register, the INT

bit must be written to '0' so the INT pin transitions to a low state indicating start of the operation. Upon completion of the command

operation by the OneNAND’s internal controller, INT returns to a high state.

INT is an open drain output allowing multiple INT outputs to be Or-tied together. INT does not float to a hi-Z condition when the chip is

deselected or when outputs are disabled. Refer to section 2.8 for additional information about INT.

INT can be implemented by tying INT to a host GPIO or by continuous polling of the Interrupt status register.

The INT Pin to a Host General Purpose I/O

INT can be tied to a Host GPIO to detect the rising edge of INT, signaling the end of a command operation.

COMMAND

INT

This can be configured to operate either synchronously or asynchronously as shown in the diagrams below.

70

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Technical Notes (Continued)

Synchronous Mode Using the INT Pin

When operating synchronously, INT is tied directly to a Host GPIO.

Host

OneNAND

CE

AVD

CLK

RDY

OE

CE

AVD

CLK

RDY

OE

GPIO

INT

Asynchronous Mode Using the INT Pin

When configured to operate in an asynchronous mode, /CE and /AVD of the OneNAND are tied to /CE of the Host. CLK is tied to the

Host Vss (Ground). /RDY is tied to a no-connect. /OE of the OneNAND and Host are tied together and INT is tied to a GPIO.

Host

CE

OneNAND

CE

AVD

CLK

RDY

OE

Vss

N.C

OE

GPIO

INT

Polling the Interrupt Register Status Bit

An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of

using the INT pin.

Command

INT

This can be configured in either a synchronous mode or an asynchronous mode.

71

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Technical Notes (Continued)

Synchronous Mode Using Interrupt Status Register Bit Polling

When operating synchronously, /CE, /AVD, CLK, /RDY, /OE, and DQ pins on the host and OneNAND are tied together.

Host

CE

OneNAND

CE

AVD

CLK

RDY

OE

AVD

CLK

RDY

OE

DQ

Asynchronous Mode Using Interrupt Status Register Bit Polling

When configured to operate in an asynchronous mode, /CE and /AVD of the OneNAND are tied to /CE of the Host. CLK is tied to the

Host Vss (Ground). /RDY is tied to a no-connect. /OE and DQ of the OneNAND and Host are tied together.

Host

CE

OneNAND

CE

AVD

CLK

RDY

OE

Vss

N.C

OE

DQ

72

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Technical Notes (Continued)

Determing Rp Value

Because the pull-up resistor value is related to tr(INT), an appropriate value can be obtained by the following reference charts.

INT pol = ’High’

Internal Vcc

Rp

~50k ohm

INT

Ready Vcc

VOH

VOL

Vss

Busy State

tf

tr

@ Vcc = 1.8V, Ta = 25°C , C_L= 30pF

5.420

2.431

1.75

2.142

0.045

Ibusy

0.18

1.788

0.06

0.09

0.7727

1.345

0.089

0.036

3.77

tr[us]

0.000

3.77

1K

3.77

10K

3.77

20K

3.77

40K

tf[ns]

30K

Open(100K)

50K

Rp(ohm)

73

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Technical Notes (Continued)

INT pol = ’Low’

Internal Vcc

INT

Rp

~50k ohm

tf

tr

Ready

Vcc

VOH

Busy State

Vss

VOL

@ Vcc = 1.8V, Ta = 25°C , C_L= 30pF

4.05

1.84

1.75

1.623

0.045

Ibusy

0.18

1.356

0.06

0.09

1.02

0.586

0.067

0.036

6.49

tf[us]

0.000

6.49

1K

6.49

10K

6.49

20K

6.49

40K

tr[ns]

30K

Open(100K)

50K

Rp(ohm)

74

OneNAND512/OneNAND1GDDP

FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

KFG1216Q2M

KFH1G16Q2M

KFG1216D2M

KFH1G16D2M

KFG1216U2M

KFH1G16U2M

Vcc

VIN

-0.5 to + 2.45

-0.6 to + 4.6

-30 to +125

-40 to +125

-65 to +150

5

Voltage on any pin relative

to VSS

V

All Pins

Extended

Industrial

-0.5 to + 2.45

-0.6 to + 4.6

-30 to +125

Temperature Under Bias

Tbias

°C

-

Storage Temperature

Tstg

IOS

-65 to +150

°C

Short Circuit Output Current

5

mA

TA (Extended Temp.)

TA (Industrial Temp.)

-30 to + 85

-

-30 to + 85

-

Operating Temperature

°C

-40 to + 85

NOTES:

1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level should not fall to POR level(typ. 1.5V) .

Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )

1.8V Device

2.65V Device

3.3V Device

Typ.

Parameter

Symbol

Unit

Min

1.7

0

Typ.

Max

1.95

0

Min

2.4

0

Typ.

Max

2.9

0

Min

2.7

0

Max

3.6

0

VCC-Core/

VCC-IO

Supply Voltage

1.8

0

2.65

0

3.3

0

V

Supply Voltage

VSS

NOTES:

1. The system power should reach 1.7V after POR triggering level(typ. 1.5V) within 400us.

2. Vcc-Core should reach the operating voltage level prior to Vcc-IO.

75

OneNAND512/OneNAND1GDDP

FLASH MEMORY

DC CHARACTERISTICS

1.8V device

2.65V device

3.3V device

Sym-

bol

Parameter

Test Conditions

Unit

Min Typ Max Min Typ Max Min Typ Max

Input Leakage Current

ILI

VIN=VSS to VCC, VCC=VCCmax - 1.0

-

+ 1.0 - 1.0

-

+ 1.0 - 1.0

-

+ 1.0 µA

Output Leakage Cur-

rent

VOUT=VSS to VCC, VCC=VCCmax

- 1.0

ILO

, CE or OE=VIH(Note 1)

Active Asynchronous

Read Current (Note 2)

ICC1 CE=VIL, OE=VIH

ICC2 CE=VIL, OE=VIH

ICC3 CE=VIL, OE=VIH

-

8

15

-

10

20

-

10

20

mA

54MHz

1MHz

-

12

3

20

4

-

20

4

30

6

-

20

4

30

6

mA

Active Burst Read

Current (Note 2)

Active Write Current

(Note 2)

-

8

15

25

20

-

10

25

20

30

25

-

10

25

20

30

25

mA

Active Load Current

(Note 3)

CE=VIL, OE=VIH, WE=VIH,

VIN=VIH or VIL

ICC4

ICC5

I_CC6

20

15

Active Program Cur-

rent (Note 3)

CE=VIL, OE=VIH, WE=VIH,

VIN=VIH or VIL

Active Erase Current

(Note3)

CE=VIL, OE=VIH, WE=VIH,

VIN=VIH or VIL

Single

DDP

-

10

20

-

50

100

0.4

-

20

40

-

50

100

0.4

-

20

40

-

50

100

0.8

Standby Current

ISB CE= RP=VCC ± 0.2V

µA

Input Low Voltage

Input High Voltage

VIL

VIH

-

-0.5

0

V

VCCIO

-0.4

VCCIO VCCIO

+0.4 -0.4

VCCIO 0.7*

+0.4 VCCIO

0.7*

VCCIO

-

IOL = 100 µA , VCC=VCCmin ,

0.22*

VCCIO

Output Low Voltage

VOL

VOH

-

0.2

-

0.2

-

V

VCCq=VCCqmin

IOH = -100 µA , VCC=VCCmin , VCCIO

VCCq=VCCqmin -0.1

VCCIO

-0.4

0.8*V

CCIO

Output High Voltage

-

NOTES:

1. CE should be VIH for RDY. IOBE should be ’0’ for INT

2. ICC active for Host access

3. ICC active while Internal operation is in progress

76

OneNAND512/OneNAND1GDDP

FLASH MEMORY

VALID BLOCK

Parameter

Symbol

Min

Typ.

Max

Unit

Valid Block Number

NVB

502

-

512

Blocks

Note :

1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-

sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program

factory-marked bad blocks.

2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block.

CAPACITANCE(TA = 25 °C, VCC = 1.8V/2.65V/3.3V, f = 1.0MHz)

Single

DDP

Unit

Item

Symbol

Test Condition

Min

Max

10

Min

Max

20

Input Capacitance

CIN1

CIN2

VIN=0V

-

pF

Control Pin Capacitance

Output Capacitance

10

20

COUT

VOUT=0V

10

20

NOTE : Capacitance is periodically sampled and not 100% tested.

AC TEST CONDITION(VCC = 1.8V/2.65V/3.3V)

Parameter

Value

0V to VCC

3ns

Input Pulse Levels

CLK

Input Rise and Fall Times

other inputs

5ns

Input and Output Timing Levels

Output Load

VCC/2

CL = 30pF

Device

Under

Test

VCC

Input & Output

VCC/2

Test Point

* CL = 30pF including scope

and Jig capacitance

0V

Input Pulse and Test Point

Output Load

77

OneNAND512/OneNAND1GDDP

FLASH MEMORY

AC CHARACTERISTICS

Synchronous Burst Read

KFG1216X2M/KFH1G16X2M

Parameter

Symbol

Unit

Min

Max

Clock

CLK

tCLK

tIAA

1

54

MHz

ns

Clock Cycle

18.5

-

Initial Access Time(at 54MHz)

Burst Access Time Valid Clock to Output Delay

AVD Setup Time to CLK

AVD Hold Time from CLK

Address Setup Time to CLK

Address Hold Time from CLK

Data Hold Time from Next Clock Cycle

Output Enable to Data

-

88.5

tBA

14.5

tAVDS

tAVDH

tACS

tACH

tBDH

tOE

7

4

-

20

1)

CE Disable to Output High Z

-

tCEZ

1)

OE Disable to Output High Z

CE Setup Time to CLK

CLK High or Low Time

-

17

-

ns

tOEZ

tCES

7

tCLKH/L

tCLK/3

-

CLK ²⁾to RDY valid

CLK to RDY Setup Time

RDY Setup Time to CLK

CE low to RDY valid

Note

tRDYO

-

14.5

-

tRDYA

tRDYS

tCER

4

-

15

1. If OE is disabled before CE is disabled, the output will go to high-z by tOEZ(max. 17ns).

If CE is disabled before OE is disabled, the output will go to high-z by tCEZ(max. 20ns).

If CE and OE are disabled at the same time, the output will go to high-z by tOEZ(max. 17ns).

2. It is the following clock of address fetch clock.

78

OneNAND512/OneNAND1GDDP

FLASH MEMORY

SWITCHING WAVEFORMS

5 cycles for initial access shown.

BRL=4

tCLK

tCES

tCLKL

tCLKH

CE

tCER

tCEZ

CLK

tAVDS

tRDYO

AVD

tAVDH

tBDH

tACS

tACH

A0-A15

tBA

D0

DQ0-DQ15

D6

D7

D0

D1

D2

D3

D7

tOEZ

tIAA

tOE

OE

tRDYS

tRDYA

Hi-Z

RDY

Figure 26. 8 Word Linear Burst Mode with Wrap Around

5 cycles for initial access shown.

BRL=4

tCLK

tCES

CE

tCER

tCEZ

CLK

AVD

tAVDS

tRDYO

tAVDH

tBDH

tACS

A0-A15

tBA

tACH

Da+n+1

tOEZ

DQ0-DQ15

Da

Da+1 Da+2 Da+3 Da+4 Da+5

Da+n

tIAA

tOE

OE

tRDYS

Hi-Z

tRDYA

RDY

Figure 27. Continuous Linear Burst Mode with Wrap Around

NOTE: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

79

OneNAND512/OneNAND1GDDP

FLASH MEMORY

AC CHARACTERISTICS

Asynchronous Read

KFG1216X2M/KFH1G16X2M

Parameter

Symbol

Unit

Min

-

Max

76

-

Access Time from CE Low

tCE

tAA

ns

Asynchronous Access Time from AVD Low

Asynchronous Access Time from address valid

Read Cycle Time

-

tACC

tRC

-

76

12

7

AVD Low Time

tAVDP

tAAVDS

tAAVDH

tOE

-

Address Setup to rising edge of AVD

Address Hold from rising edge of AVD

Output Enable to Output Valid

WE Disable to AVD Enable

-

7

-

20

-

tWEA

tCA

15

0

CE Setup to AVD falling edge

-

CE Disable to Output & RDY High Z¹⁾

tCEZ

tOEZ

-

20

OE Disable to Output & RDY High Z¹⁾

-

17

ns

NOTE:

1. If OE is disabled before CE is disabled, the output will go to high-z by tOEZ(max. 17ns).

If CE is disabled before OE is disabled, the output will go to high-z by tCEZ(max. 20ns).

If CE and OE are disabled at the same time, the output will go to high-z by tOEZ(max. 17ns).

These parameters are not tested 100%.

SWITCHING WAVEFORMS

Case 1 : Valid Address and AVD Transition occur before CE is driven to Low

VIL

CLK

CE

tCEZ

tAVDP

AVD

tOE

OE

WE

tCE

tOEZ

DQ0-DQ15

Valid RD

tAAVDH

A0-A15

VA

Hi-Z

RDY

Hi-Z

NOTE: VA=Valid Read Address, RD=Read Data.

Figure 28 . Asynchronous Read Mode(AVD toggling)

80

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Case 2 : AVD Transition occurs after CE is driven to Low and Valid Address Transition occurs before AVD is driven to Low

VIL

CLK

CE

tCEZ

tAA

tAVDP

AVD

OE

tOE

tWEA

WE

tOEZ

DQ0-DQ15

Valid RD

tAAVDH

A0-A15

VA

RDY

Hi-Z

NOTE: VA=Valid Read Address, RD=Read Data.

Figure 29. Asynchronous Read Mode(AVD toggling)

Case 3 : AVD Transition occur after CE is driven to Low and Valid Address Transition occurs after AVD is driven to Low

VIL

CLK

CE

tCEZ

tAVDP

AVD

tAAVDS

tOE

OE

tWEA

WE

tOEZ

DQ0-DQ15

Valid RD

tAAVDH

tACC

A0-A15

VA

Hi-Z

RDY

Hi-Z

NOTE: VA=Valid Read Address, RD=Read Data.

Figure 30. Asynchronous Read Mode(AVD toggling)

81

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Case 4 : AVD is tied to CE

VIL

CLK

tRC

CE

OE

tCEZ

tOE

WE

tCE

tOEZ

Valid RD

DQ0-DQ15

tACC

A0-A15

VA

Hi-Z

RDY

NOTE: VA=Valid Read Address, RD=Read Data.

Figure 31. Asynchronous Read Mode(AVD tied to CE)

82

OneNAND512/OneNAND1GDDP

FLASH MEMORY

AC CHARACTERISTICS

Asynchronous write operation

KFG1216X2M/KFH1G16X2M

Parameter

Symbol

Unit

Min

70

12

7

Typ

Max

WE Cycle Time

tWC

tAVDP

tAAVDS

tAWES

tAAVDH

tAH

-

ns

AVD low pulse width

Address Setup to rising edge of AVD

Address Setup to falling edge of WE

Address Hold to rising edge of AVD

Address Hold to falling edge of WE

Data Setup to rising edge of WE

Data Hold from rising edge of WE

CE Setup to falling edge of WE

CE Hold from rising edge of WE

WE Pulse Width

0

7

-

ns

10

4

tDS

-

tDH

t^CS

0

AVD toggled

tCH1

0

AVD tied to CE

tCH2

10

40

30

15

tWPL

tWPH

tVLWH

tWEA

WE Pulse Width High

AVD Disable to WE Disable

WE Disable to AVD Enable

83

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Case 1 : AVD is toggled every write cycle

VIL

CLK

tCS

tCH1

CE

tCS

tCH1

tAVDP

AVD

tWEA

tVLWH

tWPL

tWPH

WE

OE

tWC

tAAVDS

tAAVDH

VA

A0-A15

VA

tDS

tDH

DQ0-DQ15

RDY

Valid WD

Hi-Z

NOTE: VA=Valid Read Address, WD=Write Data.

Figure 32. Latched Asynchronous Write Mode(AVD toggling)

84

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Case 2 : AVD is synchronized with CE

VIL

CLK

tCS

tCH2

tCS

CE

tCH2

AVD

tWPL

tWPH

WE

tWC

OE

tAH

tAWES

A0-A15

VA

tDS

tDH

DQ0-DQ15

RDY

Valid WD

Hi-Z

NOTE: VA=Valid Read Address, WD=Write Data.

Figure 33. Asynchronous Write Mode(AVD toggling)

85

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Case 3 : AVD is tied to CE

VIL

CLK

tCS

tCH2

tCS

CE or AVD

tCH2

tWPL

tWPH

WE

OE

tWC

tAH

tAWES

A0-A15

VA

tDS

tDH

DQ0-DQ15

RDY

Valid WD

Hi-Z

NOTE: VA=Valid Read Address, WD=Write Data.

Figure 34. Asynchronous Write Mode(AVD tied to CE)

86

OneNAND512/OneNAND1GDDP

FLASH MEMORY

AC CHARACTERISTICS

Reset

KFG1216U2M/

KFH1G16X2M

Parameter

Symbol

Unit

Min Max

RP & Reset Command Latch(During Load Routines) to INT High (Note)

RP & Reset Command Latch(During Program Routines) to INT High (Note)

RP & Reset Command Latch(During Erase Routines) to INT High (Note)

RP & Reset Command Latch(NOT During Internal Routines) to Read Mode (Note)

INT High to Read Mode (Note)

tRST

t^Ready

tRP

µs

ns

-

10

20

500

10

-

200

RP Pulse Width

-

NOTE: These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and

pull-down resistor value. Please refer to page 73 and 74.

SWITCHING WAVEFORMS

Warm Reset

CE, OE

RP

tRP

tRST

tReady

INT bit

Hot Reset

AVD

Ai

BP or F220h

00F0h

or 00F3h

DQi

CE

OE

WE

tReady

tRST

INT bit

Figure 35. Reset Timing

87

OneNAND512/OneNAND1GDDP

FLASH MEMORY

Performance

Parameter

Symbol

tRD1

Min

Typ

40

Max

45

Unit

µs

Sector Load time (Note 1)

-

Page Load time (Note 1)

t^RD2

µs

85

100

720

750

1000

Sector Program time (Note 1)

Page Program time (Note 1)

OTP Access time(Note 1)

t^PGM1

t^PGM2

t^OTP

µs

320

350

600

µs

ns

Lock/Unlock/Lock-tight time (Note 1)

t^LOCK

ns

Number of Partial Program Cycles in the sector

(Including main and spare area)

NOP

-

2

3

cycles

ms

Block Erase time (Note 1)

1 Block

tBERS1

2

NOTES: These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and

pull-down resistor value. Please refer to page 73 and 74.

88

OneNAND512/OneNAND1GDDP

FLASH MEMORY

SWITCHING WAVEFORMS

Load Operations

Read Command Sequence

Read Data

tVLWH

tAVDP

AVD

tWEA

tAAVDH

tAAVDS

A0:A15

AA

CA

SA

BA

DQ0-DQ15

Complete

Da

RMA

RCD

tDS

tDH

CE

OE

WE

tCH1

tWPL

tWPH

tRD

tCS

tWC

VIL

CLK

INT

bit

Figure 36. Load Operation Timing

NOTES:

1. AA = Address of address register

CA = Address of command register

RCD = Read Command

RMA = Address of memory to be read

BA = Address of BufferRAM to load the data

BD = Program Data

SA = Address of status register

2. “In progress” and “complete” refer to status register

3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

89

OneNAND512/OneNAND1GDDP

FLASH MEMORY

SWITCHING WAVEFORMS

Program Operations

Program Command Sequence (last two cycles)

Read Status Data

tVLWH

tAVDP

tWEA

AVD

tAAVDS

tAAVDH

A0:A15

AA

BA

CA

SA

In

DQ0-DQ15

Complete

Progress

PMA

BD

PCD

tDH

tDS

CE

OE

WE

tCH

tWPL

tWPH

tCS

tPGM

tWC

VIL

CLK

INT

bit

Figure 37 . Program Operation Timing

NOTES:

1. AA = Address of address register

CA = Address of command register

PCD = Program Command

PMA = Address of memory to be programmed

BA = Address of BufferRAM to load the data

BD = Program Data

SA = Address of status register

2. “In progress” and “complete” refer to status register

3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

90

OneNAND512/OneNAND1GDDP

FLASH MEMORY

SWITCHING WAVEFORMS

Erase Operation

Erase Command Sequence (last two cycles)

Read Status Data

tVLWH

tWEA

tAVDP

tAAVDS

AA

AVD

tAAVDH

A0:A15

CA

SA

In

Complete

Progress

DQ0-DQ15

CE

EMA

ECD

tDS

tDH

tCH

OE

tWPL

WE

tWPH

tBERS

tCS

tWC

VIL

CLK

INT

bit

Figure 38. Block Erase Operations

NOTES:

1. AA = Address of address register

CA = Address of command register

ECD = Erase Command

EMA = Address of memory to be erased

SA = Address of status register

2. “In progress” and “complete” refer to status register

3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

91

OneNAND512/OneNAND1GDDP

FLASH MEMORY

OneNAND512 PACKAGE DIMENSIONS

63-FBGA-9.50x12.00

Units:millimeters

#A1 INDEX

9.50±0.10

A

0.10 MAX

9.50±0.10

0.80x9=7.20

(Datum A)

B

6

5

4

3

2

1

#A1

A

(Datum B)

B

0.80

C

D

E

F

G

H

3.60

0.32±0.05

0.9±0.10

BOTTOM VIEW

TOP VIEW

63-

∅ 0.45±0.05

∅

0.20

M A B

92

OneNAND512/OneNAND1GDDP

FLASH MEMORY

ORDERING INFORMATION

K F X XX 1 6 X 2 M - X X B

Product Line desinator

Samsung

B : Include Bad Block

D : Daisy Sample

OneNAND Memory

Device Type

G : Single Chip

H : Die Stack

Operating Temperature Range

E = Extended Temp. (-30 °C to 85 °C)

I = Industrial Temp. (-40 °C to 85 °C)

Density

12 : 512Mb

1G : 1Gb

Package

D : FBGA(Lead Free)

Organization

x16 Organization

Version

1st Generation

Operating Voltage Range

Q : 1.8V(1.7 V to 1.95V)

D : 2.65V(2.4 V to 2.9V)

U : 3.3V(2.7V to 3.6V)

Page Architecture

2 : 2KB Page

93


型号：	KFH1G16Q2M-DID
厂家：	SAMSUNG
描述：	FLASH MEMORY FL灰内存
文件：	总93页 (文件大小：1219K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KFH1G16Q2M-DID [SAMSUNG]

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