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KM23V32005BET-12 [SAMSUNG]

MASK ROM, 2MX16, 120ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;
KM23V32005BET-12
型号： KM23V32005BET-12
厂家： SAMSUNG    SAMSUNG
描述：

MASK ROM, 2MX16, 120ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44

有原始数据的样本ROM 光电二极管
文件： 总5页 (文件大小：87K)
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KM23V32005B(E)T  
CMOS MASK ROM  
32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· Switchable organization  
4,194,304 x 8(byte mode)  
2,097,152 x 16(word mode)  
· Fast access time  
The KM23V32005B(E)T is a fully static mask programmable  
ROM fabricated using silicon gate CMOS process technology,  
and is organized either as 4,194,304x8 bit(byte mode) or as  
2,097,152x16 bit(word mode) depending on BHE voltage  
level.(See mode selection table)  
Random Access Time : 100ns(Max.)  
Page Access Time  
: 30ns(Max.)  
This device includes page read mode function, page read mode  
allows 8 words(or 16 bytes) of data to read fast in the same  
page, CE and A3 ~ A20 should not be changed.  
· 8 words/ 16 bytes page access  
· Supply voltage : single +3.3V  
· Current consumption  
This device operates with a 3.3V power supply, and all inputs  
and outputs are TTL compatible.  
Operating : 60mA(Max.)  
Standby : 30mA(Max.)  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
· Package  
-. KM23V32005B(E)T : 44-TSOP2-400  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
The KM23V32005B(E)T is packaged in a 44-TSOP2.  
PRODUCT INFORMATION  
FUNCTIONAL BLOCK DIAGRAM  
Operating  
Temp Range  
Vcc Range  
(Typical)  
Speed  
(ns)  
Product  
A20  
X
MEMORY CELL  
MATRIX  
(2,097,152x16/  
4,194,304x8)  
BUFFERS  
AND  
DECODER  
.
.
.
.
.
.
.
.
KM23V32005BT  
KM23V32005BET  
0°C~70°C  
3.3V  
100/30  
-20°C~85°C  
Y
SENSE AMP.  
PIN CONFIGURATION  
BUFFERS  
AND  
DECODER  
DATA OUT  
BUFFERS  
A3  
N.C  
A18  
A20  
A19  
A8  
1
2
44  
43  
42  
41  
40  
39  
A0~A2  
A-1  
A17  
A7  
3
.
.
.
4
A9  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
A10  
A11  
5
CE  
6
Q0/Q8  
Q7/Q15  
CONTROL  
LOGIC  
OE  
38 A12  
37 A13  
7
8
BHE  
A14  
36  
9
A15  
35  
10  
11  
A16  
34  
33  
32  
31  
30  
TSOP2  
Pin Name  
A0 - A2  
Pin Function  
Page Address Inputs  
BHE  
VSS  
CE 12  
VSS  
13  
OE 14  
Q15/A-1  
Q7  
A3 - A20  
Q0 - Q14  
Address Inputs  
Data Outputs  
Q0  
Q8  
15  
16  
17  
18  
29 Q14  
Output 15(Word mode)/  
LSB Address(Byte mode)  
Q1  
Q9  
Q6  
28  
27  
26  
25  
24  
23  
Q15 /A-1  
Q13  
Q5  
Q2 19  
BHE  
CE  
Word/Byte selection  
Chip Enable  
Q10 20  
Q12  
Q4  
Q3  
21  
22  
Q11  
VCC  
OE  
Output Enable  
Power (3.3V)  
Ground  
VCC  
VSS  
N.C  
KM23V32005B(E)T  
No Connection  
KM23V32005B(E)T  
CMOS MASK ROM  
ABSOLUTE MAXIMUM RATINGS  
Item  
Symbol  
VIN  
Rating  
-0.3 to +4.5  
-10 to +85  
-55 to +150  
0 to +70  
Unit  
Remark  
Voltage on Any Pin Relative to VSS  
Temperature Under Bias  
Storage Temperature  
V
-
TBIAS  
TSTG  
°C  
°C  
°C  
°C  
-
-
KM23V32005BT  
KM23V32005BET  
Operating Temperature  
TA  
-20 to +85  
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the  
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may  
affect device reliability.  
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS)  
Item  
Min  
3.0  
0
Symbol  
VCC  
Typ  
3.3  
0
Max  
3.6  
0
Unit  
V
Supply Voltage  
Supply Voltage  
VSS  
V
DC CHARACTERISTICS  
Parameter  
Symbol  
ICC  
Test Conditions  
CE=OE=VIL, all outputs open  
CE=VIH, all outputs open  
CE=VCC, all outputs open  
VIN=0 to VCC  
Min  
Max  
60  
Unit  
Operating Current  
-
mA  
mA  
mA  
mA  
mA  
V
Standby Current(TTL)  
ISB1  
ISB2  
ILI  
500  
30  
Standby Current(CMOS)  
Input Leakage Current  
Output Leakage Current  
Input High Voltage, All Inputs  
Input Low Voltage, All Inputs  
Output High Voltage Level  
Output Low Voltage Level  
-
-
10  
ILO  
VOUT=0 to VCC  
10  
VIH  
2.0  
-0.3  
2.4  
-
VCC+0.3  
0.6  
VIL  
V
VOH  
VOL  
IOH=-400mA  
-
V
IOL=2.1mA  
0.4  
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.  
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.  
MODE SELECTION  
CE  
H
OE  
X
BHE  
X
Q15/A-1  
Mode  
Data  
High-Z  
Power  
X
X
Standby  
Operating  
Operating  
Standby  
Active  
L
H
X
High-Z  
H
Output  
Q0~Q15 : Dout  
Active  
L
L
Q0~Q7 : Dout  
Q8~Q14 : Hi-Z  
L
Input  
Operting  
Active  
CAPACITANCE(TA=25°C, f=1.0MHz)  
Item  
Symbol  
COUT  
CIN  
Test Conditions  
VOUT=0V  
Min  
Max  
12  
Unit  
pF  
Output Capacitance  
Input Capacitance  
-
-
VIN=0V  
12  
pF  
NOTE : Capacitance is periodically sampled and not 100% tested.  
KM23V32005B(E)T  
CMOS MASK ROM  
AC CHARACTERISTICS(VCC=3.3V±0.3V, unless otherwise noted.)  
TEST CONDITIONS  
Item  
Value  
Input Pulse Levels  
0.45V to 2.4V  
10ns  
Input Rise and Fall Times  
Input and Output timing Levels  
1.5V  
Output Loads  
1 TTL Gate and CL=100pF  
READ CYCLE  
KM23V32005B(E)T-10 KM23V32005B(E)T-12 KM23V32005B(E)T-15  
Item  
Symbol  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Read Cycle Time  
tRC  
tACE  
tAA  
100  
120  
150  
ns  
ns  
ns  
ns  
ns  
Chip Enable Access Time  
Address Access Time  
100  
100  
30  
120  
120  
50  
150  
150  
70  
Page Address Access Time  
Output Enable Access Time  
tPA  
tOE  
30  
50  
70  
Output or Chip Disable to  
Output High-Z  
tDF  
tOH  
20  
20  
30  
ns  
ns  
Output Hold from Address Change  
0
0
0
NOTE : Page Address is determined as below.  
Word mode(BHE=VIH) ; A0, A1, A2  
Byte mode(BHE=VIL) ; A -1, A0, A1, A2  
KM23V32005B(E)T  
CMOS MASK ROM  
TIMING DIAGRAM  
READ  
ADD  
ADD1  
ADD2  
A0~A20  
A-1(*1)  
tRC  
tDF(*3)  
tACE  
CE  
OE  
tOE  
tAA  
tOH  
DOUT  
D0~D7  
VALID DATA  
VALID DATA  
D8~D15(*2)  
PAGE READ  
CE  
OE  
tDF(*3)  
ADD  
A3~A20  
ADD  
1 st  
2 nd  
3 rd  
A0,A1,A2  
A -1(*1)  
tAA  
tPA  
DOUT  
VALID DATA  
VALID DATA  
VALID DATA  
VALID DATA  
D0~D7  
D8~D15(*2)  
NOTES :  
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)  
*2. Word Mode only.(BHE = VIH)  
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.  
KM23V32005B(E)T  
CMOS MASK ROM  
PACKAGE DIMENSIONS  
(Unit : mm/inch)  
44-TSOP2-400  
0~8°  
0.25  
0.010  
(
)
#44  
#23  
0.45 ~0.75  
0.018 ~ 0.030  
11.76±0.20  
0.463±0.008  
0.50  
)
(
0.020  
#1  
#22  
0.15 + 0.10  
1.00±0.10  
0.039±0.004  
1.20  
- 0.05  
+ 0.004  
18.81  
0.741  
0.006  
- 0.002  
MAX.  
MAX.  
0.047  
18.41±0.10  
0.725±0.004  
0.10  
MAX  
0.004  
0.80  
0.0315  
0.805  
0.032  
0.35±0.10  
0.014±0.004  
(
)

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