KM62U256DLG-10L0 [SAMSUNG]
Standard SRAM, 32KX8, 100ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, SOP-28;型号: | KM62U256DLG-10L0 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 32KX8, 100ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, SOP-28 静态存储器 光电二极管 内存集成电路 |
文件: | 总9页 (文件大小:159K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
KM62V256D, KM62U256D Family
CMOS SRAM
Document Title
32Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
History
Draft Data
Remark
0.0
Initial draft
April 1, 1997
Preliminary
1.0
Finalize
November 12, 1997
Final
- Add 70ns part in KM62U256D Family
- Show ICC read only, and increased value
ICC = 2mA ® ICC Read = 5mA
- Seperate ICC1 read and write
ICC1 = 5mA® ICC1 Read = 5mA, ICC1 Write = 10mA
- Improved standby current(ISB1)
Commercial part : 10mA® 5mA
Extended and Industrial part : 20mA® 5mA
- Improved VIL(Min.) : 0.4V® 0.6V
- Improved power dissipation : 0.7W® 1W
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO, LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 1.0
1
November 1997
KM62V256D, KM62U256D Family
CMOS SRAM
32Kx8 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
FEATURES
• Process Technology : TFT
• Organization : 32Kx8
The KM62V256D and KM62U256D families are fabricated
by SAMSUNG¢s advanced CMOS process technology. The
families support various operating temperature range and
have various package types for user flexibility of system
design. The families also support low data retention voltage
for battery back-up operation with low data retention current.
• Power Supply Voltage
KM62V256D family : 2.7~3.3V
KM62U256D family : 3.0~3.6V
• Low Data Retention Voltage : 2V(Min)
• Three state output and TTL Compatible
• Package Type : 28-SOP-450
28-TSOP1-0813.4F/R
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Speed
(ns)
VCC Range
PKG Type
Standby
Operating
(Icc2)
(ISB1, Max)
701)/100
701)/85/100
701)/100
KM62V256DL-L
KM62U256DL-L
KM62V256DLE-L
KM62U256DLE-L
KM62V256DLI-L
KM62U256DLI-L
3.0V ~3.6V
2.7V ~ 3.3V
3.0V ~3.6V
2.7V ~ 3.3V
3.0V ~3.6V
2.7V ~ 3.3V
Commercial(0~70°C)
Extended(-25~85°C)
Industrial(-40~85°C)
28-SOP2)
28-TSOP1-F/R
5mA
35mA
701)/85/100
701)/100
701)/85/100
1. The parameter is measured with 30pF test load.
2. KM62V256D Family support SOP package without 100ns speed bin.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
OE
A11
A9
Clk gen.
Precharge circuit.
2
3
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
4
A8
A13
A8
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
5
A13
WE
VCC
A14
A12
A7
6
2
28-TSOP
Type1 - Forward
7
A12
A14
A4
8
3
Memory array
256 rows
128´ 8 columns
9
Row
select
4
A6
10
11
12
13
14
A6
5
A5
A9
A5
A5
A6
A7
A1
A4
6
A11
OE
A4
A2
A3
7
A3
28-SOP
8
14
13
12
11
10
9
A3
A4
A10
CS
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A2
A2
A1
9
I/O Circuit
A1
I/O1
I/O8
Data
cont
A5
A0
A6
Column select
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS
10
11
12
13
14
I/O8
I/O7
I/O6
I/O5
I/O4
A0
A7
A12
A14
VCC
WE
A13
A8
I/O1
I/O2
I/O3
VSS
8
28-TSOP
Type1 - Reverse
Data
cont
7
6
5
4
A10 A3 A0 A1 A2 A9 A11
A9
3
A11
2
1
A10
OE
CS
Control
logic
Pin Name
CS
Function
Pin Name
Function
WE
OE
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
I/O1~I/O8 Data Inputs/Outputs
OE
Vcc
Vss
NC
Power
WE
Ground
A0~A14
No connect
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 1.0
November 1997
2
KM62V256D, KM62U256D Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products
Extended Temperature Products
(-25~85°C)
Industrial Temperature Products
(0~70°C)
(-40~85°C)
Part Name
Function
Part Name
KM62V256DLGE-7L
Function
Part Name
Function
KM62V256DLG-7L
28-SOP, 70ns, 3.3V
28-SOP, 70ns, 3.3V
KM62V256DLGI-7L
28-SOP, 70ns, 3.3V
KM62V256DLTG-7L 28-TSOP F, 70ns, 3.3V KM62V256DLTGE-7L
28-TSOP F, 70ns, 3.3V KM62V256DLTGI-7L 28-TSOP F, 70ns, 3.3V
KM62V256DLTG-10L 28-TSOP F, 100ns, 3.3V KM62V256DLTGE-10L 28-TSOP F, 100ns, 3.3V KM62V256DLTGI-10L 28-TSOP F, 100ns, 3.3V
KM62V256DLRG-7L 28-TSOP R, 70ns, 3.3V KM62V256DLRGE-7L 28-TSOP R, 70ns, 3.3V KM62V256DLRGI-7L 28-TSOP R, 70ns, 3.3V
KM62V256DLRG-10L 28-TSOP R, 100ns, 3.3V KM62V256DLRGE-10L 28-TSOP R, 100ns, 3.3V KM62V256DLRGI-10L 28-TSOP R, 100ns, 3.3V
KM62U256DLG-7L
KM62U256DLG-8L
28-SOP, 70ns, 3.0V
28-SOP, 85ns, 3.0V
KM62U256DLGE-7L
KM62U256DLGE-8L
28-SOP, 70ns, 3.0V
28-SOP, 85ns, 3.0V
KM62U256DLGI-7L
KM62U256DLGI-8L
28-SOP, 70ns, 3.0V
28-SOP, 85ns, 3.0V
KM62U256DLG-10L 28-SOP, 100ns, 3.0V
KM62U256DLTG-7L 28-TSOP F, 70ns, 3.0V KM62U256DLTGE-7L 28-TSOP F, 70ns, 3.0V KM62U256DLTGI-7L 28-TSOP F, 70ns, 3.0V
KM62U256DLTG-8L 28-TSOP F, 85ns, 3.0V KM62U256DLTGE-8L 28-TSOP F, 85ns, 3.0V KM62U256DLTGI-8L 28-TSOP F, 85ns, 3.0V
KM62U256DLGE-10L 28-SOP, 100ns, 3.0V
KM62U256DLGI-10L 28-SOP, 100ns, 3.0V
KM62U256DLTG-10L 28-TSOP F, 100ns, 3.0V KM62U256DLTGE-10L 28-TSOP F, 100ns, 3.0V KM62U256DLTGI-10L 28-TSOP F, 100ns, 3.0V
KM62U256DLRG-7L 28-TSOP R, 70ns, 3.0V KM62U256DLRGE-7L 28-TSOP R, 70ns, 3.0V KM62U256DLRGI-7L 28-TSOP R, 70ns, 3.0V
KM62U256DLRG-8L 28-TSOP R, 85ns, 3.0V KM62U256DLRGE-8L 28-TSOP R, 85ns, 3.0V KM62U256DLRGI-8L 28-TSOP R, 85ns, 3.0V
KM62U256DLRG-10L 28-TSOP R, 100ns, 3.0V KM62U256DLRGE-10L 28-TSOP R, 100ns, 3.0V KM62U256DLRGI-10L 28-TSOP R, 100ns, 3.0V
FUNCTIONAL DESCRIPTION
CS
H
L
OE
X1)
H
WE
X1)
H
I/O
High-Z
High-Z
Dout
Mode
Deselected
Output Disabled
Read
Power
Standby
Active
L
L
H
Active
X1)
L
L
Din
Write
Active
1. X means don¢t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
VIN,VOUT
VCC
Ratings
-0.5 to VCC+0.5
-0.5 to 4.6
Unit
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
V
V
-
-
-
-
PD
1.0
W
°C
°C
°C
°C
-
Storage temperature
TSTG
-65 to 150
0 to 70
KM62V256DL, KM62U256DL
KM62V256DLE, KM62U256DLE
KM62V256DLI, KM62U256DLI
-
Operating Temperature
TA
-25 to 85
-40 to 85
Soldering temperature and time
TSOLDER
260°C, 10sec (Lead Only)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 1.0
3
November 1997
KM62V256D, KM62U256D Family
CMOS SRAM
1)
RECOMMENDED DC OPERATING CONDITIONS
Item
Symbol
Product
Min
3.0
2.7
0
Typ
3.3
3.0
0
Max
3.6
Unit
KM62V256D Family
KM62U256D Family
Supply voltage
Vcc
V
3.3
Ground
Vss
VIH
VIL
ALL
0
V
V
V
Input high voltage
Input low voltage
KM62V256D, KM62U256D Family
KM62V256D, KM62U256D Family
2.2
-0.33)
-
Vcc+0.3
0.6
-
Note:
1. Commercial Product : TA=0 to 70°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : VCC+3.0V in case of pulse width£30ns
3. Undershoot : -3.0V in case of pulse width£30ns
4. Overshoot and undershoot are sampled, not 100% tested
1)
CAPACITANCE (f=1MHz, TA=25°C)
Item
Symbol
CIN
Test Condition
VIN=0V
Min
Max
Unit
pF
Input capacitance
-
-
8
Input/Output capacitance
CIO
VIO=0V
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
VIN=Vss to Vcc
-1
-1
-
-
-
1
1
mA
mA
Output leakage current
Operating power supply current
ILO
CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc
IIO=0mA, CS=VIL, VIN=VIH or VIL, Read
ICC
2
5
mA
Read
Write
-
1.5
6
5
Cycle time=1ms, 100% duty, IIO=0mA
CS£0.2V, VIN£0.2V, VIN³ Vcc -0.2V
ICC1
mA
Average operating current
10
35
0.4
-
ICC2
VOL
VOH
ISB
Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
IOL=2.1mA
-
23
-
mA
V
Output low voltage
-
2.4
-
Output high voltage
Standby Current(TTL)
Standby Current (CMOS)
IOH=-1.0mA
-
V
CS=VIH, Other inputs=VIH or VIL
CS³ Vcc-0.2V, Other inputs=0~Vcc
-
0.3
5
mA
mA
ISB1
-
0.1
Revision 1.0
November 1997
4
KM62V256D, KM62U256D Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.4V
Input rising and falling time : 5ns
1)
CL
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
1)
1. Including scope and jig capacitance
CL =30pF+1TTL
1. Refer to AC CHARACTERISTICS
AC CHARACTERISTICS(KM62V256D Family:Vcc=3.0~3.6V, KM62U256D Family:Vcc=2.7~3.3V
Commercial product :TA=0 to 70°C, Extended product :TA=-25 to 85°C, Industrial product :TA=-40 to 85°C)
Speed Bins
85ns
701)ns
Parameter List
Symbol
Units
100ns
Min
Max
Min
Max
Min
100
-
Max
Read cycle time
tRC
tAA
70
-
-
70
70
35
-
85
-
-
85
85
40
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
100
Chip select to output
tCO
tOE
-
-
-
100
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address
Write cycle time
-
-
-
50
-
Read
tLZ
10
5
10
5
10
5
tOLZ
tHZ
-
-
-
0
30
30
-
0
30
30
-
0
35
35
-
tOHZ
tOH
tWC
tCW
tAS
0
0
0
5
10
85
70
0
15
100
80
0
70
60
0
-
-
-
Chip select to end of write
Address set-up time
-
-
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
60
50
0
-
70
60
0
-
80
70
0
-
-
-
-
Write
Write recovery time
-
-
-
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
0
25
-
0
25
-
0
35
-
30
0
35
0
40
0
-
-
-
tOW
5
-
10
-
10
-
1. The parameter is measured with 30pF test load
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
Test Condition
CS³ Vcc-0.2V
Vcc=3.0V, CS³ Vcc-0.2V
Min
2.0
-
Typ
Max
Unit
V
-
3.6
IDR
5
-
mA
tSDR
0
-
-
See data retention waveform
ms
tRDR
5
-
Revision 1.0
5
November 1997
KM62V256D, KM62U256D Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 1.0
November 1997
6
KM62V256D, KM62U256D Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS
tAW
tWP(1)
WE
tDW
tDH
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0/2.7V
2.2V
VDR
CS³ VCC - 0.2V
CS
GND
Revision 1.0
7
November 1997
KM62V256D, KM62U256D Family
CMOS SRAM
PACKAGE DIMENSIONS
Units :millimeter(inch)
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
0~8°
#28
#15
8.38±0.20
0.330±0.008
11.81±0.30
0.465±0.012
#1
#14
1.02±0.20
0.040±0.008
+0.10
-0.05
+0.004
0.006
-0.002
0.15
2.59±0.20
0.102±0.008
18.69
0.736
MAX
3.00
0.118
MAX
18.29±0.20
0.720±0.008
0.10 MAX
0.004 MAX
0.89
0.035
1.27
0.050
0.41±0.10
0.016±0.004
(
)
0.05
0.002
MIN
Revision 1.0
8
November 1997
KM62V256D, KM62U256D Family
CMOS SRAM
PACKAGE DIMENSIONS
Units :millimeter(inch)
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F)
13.40±0.20
0.528±0.008
+0.10
0.20
-0.05
+0.004
0.008
-0.002
#1
#28
0.425
0.017
(
)
0.55
0.0217
#14
#15
0.25
0.010
11.80±0.10
0.465±0.004
+0.10
-0.05
TYP
0.15
0.006+0.004
-0.002
1.00±0.10
0.039±0.004
0.05
0.002
MIN
0~8°
1.20
MAX
0.047
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R)
13.40±0.20
0.528±0.008
+0.10
-0.05
0.20
0.008+0.004
-0.002
#14
#15
0.425
0.017
(
)
0.55
0.0217
#1
#28
1.00±0.10
0.05
0.002
MIN
0.25
0.010
11.80±0.10
0.465±0.004
0.039±0.004
+0.10
-0.05
TYP
0.15
0.006+0.004
1.20
MAX
0.047
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
Revision 1.0
9
November 1997
相关型号:
©2020 ICPDF网 联系我们和版权申明