KM62U256DLG-7L [SAMSUNG]

32Kx8 bit Low Power and Low Voltage CMOS Static RAM; 32Kx8位低功耗和低电压CMOS静态RAM


型号：	KM62U256DLG-7L
厂家：	SAMSUNG
描述：	32Kx8 bit Low Power and Low Voltage CMOS Static RAM 32Kx8位低功耗和低电压CMOS静态RAM
文件：	总9页 (文件大小：162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KM62V256D, KM62U256D Family

CMOS SRAM

Document Title

32Kx8 bit Low Power and Low Voltage CMOS Static RAM

Revision History

Revision No.

History

Draft Data

Remark

0.0

Initial draft

April 1, 1997

Preliminary

1.0

Finalize

November 12, 1997

Final

- Add 70ns part in KM62U256D Family

- Show ICC read only, and increased value

ICC = 2mA ® ICC Read = 5mA

- Seperate ICC1 read and write

ICC1 = 5mA® ICC1 Read = 5mA, ICC1 Write = 10mA

- Improved standby current(ISB1)

Commercial part : 10mA® 5mA

Extended and Industrial part : 20mA® 5mA

- Improved VIL(Min.) : 0.4V® 0.6V

- Improved power dissipation : 0.7W® 1W

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO, LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 1.0

November 1997

KM62V256D, KM62U256D Family

CMOS SRAM

32Kx8 bit Low Power and Low Voltage CMOS Static RAM

GENERAL DESCRIPTION

FEATURES

• Process Technology : TFT

• Organization : 32Kx8

The KM62V256D and KM62U256D families are fabricated

by SAMSUNG¢s advanced CMOS process technology. The

families support various operating temperature range and

have various package types for user flexibility of system

design. The families also support low data retention voltage

for battery back-up operation with low data retention current.

• Power Supply Voltage

KM62V256D family : 2.7~3.3V

KM62U256D family : 3.0~3.6V

• Low Data Retention Voltage : 2V(Min)

• Three state output and TTL Compatible

• Package Type : 28-SOP-450

28-TSOP1-0813.4F/R

PRODUCT FAMILY

Power Dissipation

Product

Family

Operating

Temperature

Speed

(ns)

VCC Range

PKG Type

Standby

Operating

(Icc2)

(ISB1, Max)

70¹⁾/100

70¹⁾/85/100

70¹⁾/100

KM62V256DL-L

KM62U256DL-L

KM62V256DLE-L

KM62U256DLE-L

KM62V256DLI-L

KM62U256DLI-L

3.0V ~3.6V

2.7V ~ 3.3V

3.0V ~3.6V

2.7V ~ 3.3V

3.0V ~3.6V

2.7V ~ 3.3V

Commercial(0~70°C)

Extended(-25~85°C)

Industrial(-40~85°C)

28-SOP²⁾

28-TSOP1-F/R

5mA

35mA

70¹⁾/85/100

70¹⁾/100

70¹⁾/85/100

1. The parameter is measured with 30pF test load.

2. KM62V256D Family support SOP package without 100ns speed bin.

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

A10

A11

Clk gen.

Precharge circuit.

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

A13

A14

A12

VCC

A13

VCC

A14

A12

28-TSOP

Type1 - Forward

A12

A14

Memory array

256 rows

128´ 8 columns

Row

select

A11

28-SOP

A10

I/O Circuit

I/O1

I/O8

Data

cont

Column select

I/O1

I/O2

I/O3

VSS

I/O4

I/O5

I/O6

I/O7

I/O8

I/O7

I/O6

I/O5

I/O4

A12

A14

VCC

A13

I/O1

I/O2

I/O3

VSS

28-TSOP

Type1 - Reverse

Data

cont

A10 A3 A0 A1 A2 A9 A11

A11

A10

Control

logic

Pin Name

Function

Pin Name

Function

Chip Select Input

Output Enable Input

Write Enable Input

Address Inputs

I/O1~I/O8 Data Inputs/Outputs

Vcc

Vss

Power

Ground

A0~A14

No connect

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 1.0

November 1997

KM62V256D, KM62U256D Family

CMOS SRAM

PRODUCT LIST

Commercial Temperature Products

Extended Temperature Products

(-25~85°C)

Industrial Temperature Products

(0~70°C)

(-40~85°C)

Part Name

Function

Part Name

KM62V256DLGE-7L

Function

Part Name

Function

KM62V256DLG-7L

28-SOP, 70ns, 3.3V

KM62V256DLGI-7L

28-SOP, 70ns, 3.3V

KM62V256DLTG-7L 28-TSOP F, 70ns, 3.3V KM62V256DLTGE-7L

28-TSOP F, 70ns, 3.3V KM62V256DLTGI-7L 28-TSOP F, 70ns, 3.3V

KM62V256DLTG-10L 28-TSOP F, 100ns, 3.3V KM62V256DLTGE-10L 28-TSOP F, 100ns, 3.3V KM62V256DLTGI-10L 28-TSOP F, 100ns, 3.3V

KM62V256DLRG-7L 28-TSOP R, 70ns, 3.3V KM62V256DLRGE-7L 28-TSOP R, 70ns, 3.3V KM62V256DLRGI-7L 28-TSOP R, 70ns, 3.3V

KM62V256DLRG-10L 28-TSOP R, 100ns, 3.3V KM62V256DLRGE-10L 28-TSOP R, 100ns, 3.3V KM62V256DLRGI-10L 28-TSOP R, 100ns, 3.3V

KM62U256DLG-7L

KM62U256DLG-8L

28-SOP, 70ns, 3.0V

28-SOP, 85ns, 3.0V

KM62U256DLGE-7L

KM62U256DLGE-8L

28-SOP, 70ns, 3.0V

28-SOP, 85ns, 3.0V

KM62U256DLGI-7L

KM62U256DLGI-8L

28-SOP, 70ns, 3.0V

28-SOP, 85ns, 3.0V

KM62U256DLG-10L 28-SOP, 100ns, 3.0V

KM62U256DLTG-7L 28-TSOP F, 70ns, 3.0V KM62U256DLTGE-7L 28-TSOP F, 70ns, 3.0V KM62U256DLTGI-7L 28-TSOP F, 70ns, 3.0V

KM62U256DLTG-8L 28-TSOP F, 85ns, 3.0V KM62U256DLTGE-8L 28-TSOP F, 85ns, 3.0V KM62U256DLTGI-8L 28-TSOP F, 85ns, 3.0V

KM62U256DLGE-10L 28-SOP, 100ns, 3.0V

KM62U256DLGI-10L 28-SOP, 100ns, 3.0V

KM62U256DLTG-10L 28-TSOP F, 100ns, 3.0V KM62U256DLTGE-10L 28-TSOP F, 100ns, 3.0V KM62U256DLTGI-10L 28-TSOP F, 100ns, 3.0V

KM62U256DLRG-7L 28-TSOP R, 70ns, 3.0V KM62U256DLRGE-7L 28-TSOP R, 70ns, 3.0V KM62U256DLRGI-7L 28-TSOP R, 70ns, 3.0V

KM62U256DLRG-8L 28-TSOP R, 85ns, 3.0V KM62U256DLRGE-8L 28-TSOP R, 85ns, 3.0V KM62U256DLRGI-8L 28-TSOP R, 85ns, 3.0V

KM62U256DLRG-10L 28-TSOP R, 100ns, 3.0V KM62U256DLRGE-10L 28-TSOP R, 100ns, 3.0V KM62U256DLRGI-10L 28-TSOP R, 100ns, 3.0V

FUNCTIONAL DESCRIPTION

X¹⁾

I/O

High-Z

Dout

Mode

Deselected

Output Disabled

Read

Power

Standby

Active

X¹⁾

Din

Write

Active

1. X means don¢t care (Must be in high or low states)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

VIN,VOUT

VCC

Ratings

-0.5 to VCC+0.5

-0.5 to 4.6

Unit

Remark

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

1.0

°C

Storage temperature

TSTG

-65 to 150

0 to 70

KM62V256DL, KM62U256DL

KM62V256DLE, KM62U256DLE

KM62V256DLI, KM62U256DLI

Operating Temperature

-25 to 85

-40 to 85

Soldering temperature and time

TSOLDER

260°C, 10sec (Lead Only)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 1.0

November 1997

KM62V256D, KM62U256D Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS

Item

Symbol

Product

Min

3.0

2.7

Typ

3.3

3.0

Max

3.6

Unit

KM62V256D Family

KM62U256D Family

Supply voltage

Vcc

3.3

Ground

Vss

VIH

VIL

ALL

Input high voltage

Input low voltage

KM62V256D, KM62U256D Family

2.2

-0.3³⁾

Vcc+0.3

0.6

Note:

1. Commercial Product : TA=0 to 70°C, otherwise specified

Industrial Product : TA=-40 to 85°C, otherwise specified

2. Overshoot : V_CC+3.0V in case of pulse width£30ns

3. Undershoot : -3.0V in case of pulse width£30ns

4. Overshoot and undershoot are sampled, not 100% tested

CAPACITANCE (f=1MHz, TA=25°C)

Item

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input capacitance

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Test Conditions

Min Typ Max Unit

Input leakage current

VIN=Vss to Vcc

-1

Output leakage current

Operating power supply current

ILO

CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc

IIO=0mA, CS=VIL, VIN=VIH or VIL, Read

ICC

Read

Write

1.5

Cycle time=1ms, 100% duty, IIO=0mA

CS£0.2V, VIN£0.2V, VIN³ Vcc -0.2V

ICC1

Average operating current

0.4

ICC2

VOL

VOH

ISB

Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL

IOL=2.1mA

Output low voltage

2.4

Output high voltage

Standby Current(TTL)

Standby Current (CMOS)

IOH=-1.0mA

CS=VIH, Other inputs=VIH or VIL

CS³ Vcc-0.2V, Other inputs=0~Vcc

0.3

ISB1

0.1

Revision 1.0

November 1997

KM62V256D, KM62U256D Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level : 0.4 to 2.4V

Input rising and falling time : 5ns

Input and output reference voltage : 1.5V

Output load (See right) :CL=100pF+1TTL

1. Including scope and jig capacitance

CL =30pF+1TTL

1. Refer to AC CHARACTERISTICS

AC CHARACTERISTICS(KM62V256D Family:Vcc=3.0~3.6V, KM62U256D Family:Vcc=2.7~3.3V

Commercial product :TA=0 to 70°C, Extended product :TA=-25 to 85°C, Industrial product :TA=-40 to 85°C)

Speed Bins

85ns

70¹⁾ns

Parameter List

Symbol

Units

100ns

Min

Max

Min

Max

Min

100

Max

Read cycle time

tRC

tAA

Address access time

100

Chip select to output

tCO

tOE

100

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

Output disable to high-Z output

Output hold from address

Write cycle time

Read

tLZ

tOLZ

tHZ

tOHZ

tOH

tWC

tCW

tAS

100

Chip select to end of write

Address set-up time

Address valid to end of write

Write pulse width

tAW

tWP

tWR

tWHZ

tDW

tDH

Write

Write recovery time

Write to output high-Z

Data to write time overlap

Data hold from write time

End write to output low-Z

tOW

1. The parameter is measured with 30pF test load

DATA RETENTION CHARACTERISTICS

Item

Vcc for data retention

Data retention current

Data retention set-up time

Recovery time

Symbol

VDR

Test Condition

CS³ Vcc-0.2V

Vcc=3.0V, CS³ Vcc-0.2V

Min

2.0

Typ

Max

Unit

3.6

IDR

tSDR

See data retention waveform

tRDR

Revision 1.0

November 1997

KM62V256D, KM62U256D Family

CMOS SRAM

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO

tHZ

tOE

tOHZ

tOLZ

tLZ

High-Z

Data out

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 1.0

November 1997

KM62V256D, KM62U256D Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tCW(2)

tWR(4)

tAW

tWP(1)

tAS(3)

tDW

tDH

Data Valid

Data in

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

tWC

Address

tCW(2)

tAS(3)

tWR(4)

tAW

tWP(1)

tDW

tDH

Data in

Data Valid

High-Z

Data out

High-Z

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE

going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write

to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

DATA RETENTION WAVE FORM

CS controlled

Data Retention Mode

tSDR

tRDR

VCC

3.0/2.7V

2.2V

VDR

CS³ VCC - 0.2V

GND

Revision 1.0

November 1997

KM62V256D, KM62U256D Family

CMOS SRAM

PACKAGE DIMENSIONS

Units :millimeter(inch)

28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)

0~8°

#28

#15

8.38±0.20

0.330±0.008

11.81±0.30

0.465±0.012

#14

1.02±0.20

0.040±0.008

+0.10

-0.05

+0.004

0.006

-0.002

0.15

2.59±0.20

0.102±0.008

18.69

0.736

MAX

3.00

0.118

MAX

18.29±0.20

0.720±0.008

0.10 MAX

0.004 MAX

0.89

0.035

1.27

0.050

0.41±0.10

0.016±0.004

(

)

0.05

0.002

MIN

Revision 1.0

November 1997

KM62V256D, KM62U256D Family

CMOS SRAM

PACKAGE DIMENSIONS

Units :millimeter(inch)

28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F)

13.40±0.20

0.528±0.008

+0.10

0.20

-0.05

+0.004

0.008

-0.002

#28

0.425

0.017

(

)

0.55

0.0217

#14

#15

0.25

0.010

11.80±0.10

0.465±0.004

+0.10

-0.05

TYP

0.15

0.006^+0.004

-0.002

1.00±0.10

0.039±0.004

0.05

0.002

MIN

0~8°

1.20

MAX

0.047

0.50

0.020

0.45 ~0.75

0.018 ~0.030

(

)

28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R)

13.40±0.20

0.528±0.008

+0.10

-0.05

0.20

0.008^+0.004

-0.002

#14

#15

0.425

0.017

(

)

0.55

0.0217

#28

1.00±0.10

0.05

0.002

MIN

0.25

0.010

11.80±0.10

0.465±0.004

0.039±0.004

+0.10

-0.05

TYP

0.15

0.006^+0.004

1.20

MAX

0.047

-0.002

0~8°

0.50

0.020

0.45 ~0.75

0.018 ~0.030

(

)

Revision 1.0

November 1997

KM62U256DLG-7L [SAMSUNG]

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