KM684002-25 [SAMSUNG]

512Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial, Extended and Industrial Temperature Range.; 512Kx8位高速静态RAM （ 5V工作），革命销出去。工作在商用，扩展和工业温度范围。


型号：	KM684002-25
厂家：	SAMSUNG
描述：	512Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial, Extended and Industrial Temperature Range. 512Kx8位高速静态RAM （ 5V工作），革命销出去。工作在商用，扩展和工业温度范围。
文件：	总9页 (文件大小：152K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

KM684002, KM684002E, KM684002I

CMOS SRAM

Document Title

512Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.

Operated at Commercial, Extended and Industrial Temperature Range.

Revision History

RevNo.

History

Draft Data

Remark

Preliminary

Final

Rev. 0.0

Rev. 1.0

Initial release with Preliminary.

Jun. 1th, 1991

Oct. 4th, 1993

Release to final Data Sheet.

1.1. Delete Preliminary

Rev. 2.0

Rev. 3.0

2.1. Delete 15ns part

2.2. Add 17ns part.

2.3.Add the test condition for Voh1 with Vcc=5V±5% at 25°C

Apr. 2th, 1994

Jun. 17th, 1997

Final

3.1.Delete Low power product with Data Retention Mode.

3.1.1. Delete Data Retention Characteristics

3.2.Add Industrial and Extended Temperature Range parts with the

same parameters as Commercial Temperature Range parts.

3.2.1 Add KM684002I for Industrial Temperature Range.

3.2.2.Add KM684002E for Extended Temperature Range.

3.2.3.Add ordering information.

3.2.4. Add the condition for operating at Industrial and Extended

Temperature Range.

3.3.Add timing diagram to define tWP as ²(Timing Wave Form of

Write Cycle(CS=Controlled)²

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this

device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 1 -

Rev 3.0

June -1997

PRELIMINARY

KM684002, KM684002E, KM684002I

CMOS SRAM

512K x 8 Bit High-Speed CMOS Static RAM

FEATURES

Fast Access Time 17,20,25 (Max.)

GENERAL DESCRIPTION

¡ Ü

§À

The KM684002 is a 4,194,304-bit high-speed Static Random

Access Memory organized as 524,288 words by 8 bits. The

KM684002 uses 8 common input and output lines and has an

output enable pin which operates faster than address access

time at read cycle. The device is fabricated using Samsung's

advanced CMOS process and designed for high-speed circuit

technology. It is particularly well suited for use in high-density

high-speed system applications. The KM684002 is packaged in

a 400 mil 36-pin plastic SOJ.

¡ Ü

Low Power Dissipation

§Ì

: 60 (Max.)

Standby (TTL)

§Ì

(CMOS) : 10 (Max.)

§Ì

Operating KM684002 - 17 : 180 (Max.)

KM684002 - 20 : 170 (Max.)

KM684002 - 25 : 160 (Max.)

¡ Ü

Single 5.0V±10% Power Supply

TTL Compatible Inputs and Outputs

I/O Compatible with 3.3V Device

Fully Static Operation

- No Clock or Refresh required

Three State Outputs

Center Power/Ground Pin Configuration

Standard Pin Configuration

KM684002J : 36-SOJ-400

PIN CONFIGURATION(Top View)

¡ Ü

36 N.C

35 A18

34 A17

33 A16

32 A15

31 OE

30 I/O8

29 I/O7

28 Vss

27 Vcc

26 I/O6

25 I/O5

24 A14

23 A13

22 A12

21 A11

20 A10

19 N.C

ORDERING INFORMATION

KM684002 -17/20/25

KM684002E -17/20/25

KM684002I -17/20/25

Commercial Temp.

Extended Temp.

Industrial Temp.

I/O1

I/O2

Vcc

SOJ

FUNCTIONAL BLOCK DIAGRAM

Vss 10

I/O3 11

I/O4 12

WE 13

A5 14

A6 15

A7 16

A8 17

A9 18

Clk Gen.

Pre-Charge Circuit

Memory Array

1024 Rows

512x8 Columns

A13

A14

PIN FUNCTION

Data

Cont.

I/O Circuit

Column Select

I/O1 ~ I/O8

Pin Name

Pin Function

Address Inputs

Write Enable

A0 - A18

CLK

Gen.

Chip Select

Output Enable

A11

A10 A12

A15

A17

A16 A18

I/O1 ~ I/O8

VCC

Data Inputs/Outputs

Power(+5.0V)

Ground

VSS

N.C

No Connection

- 2 -

Rev 3.0

June -1997

PRELIMINARY

KM684002, KM684002E, KM684002I

CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

Parameter

Voltage on Any Pin Relative to VSS

Voltage on VCC Supply Relative to VSS

Power Dissipation

Symbol

VIN, VOUT

VCC

Rating

-0.5 to 7.0

1.0

Unit

°C

Storage Temperature

TSTG

-65 to 150

0 to 70

Commercial

Operating Temperature

Extended

Industrial

-25 to 85

-40 to 85

°C

* Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress ra ting only and func-

tional operation of the device at these at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)

Parameter

Min

Symbol

Typ

5.0

Max

5.5

Unit

Supply Voltage

VCC

VSS

4.5

Ground

Input Low Voltage

VIH

VIL

2.2

VCC+0.5**

-0.5*

0.8

NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.

§Ì

* VIL(Min) = -2.0V a.c(Pulse Width £10ns) for I£20

§Ì

** VIH(Max) = VCC + 2.0V a.c (Pulse Width£10ns) for I£20

DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc= 5.0V±10%, unless otherwise specified)

Min

Max

Parameter

Symbol

Test Conditions

VIN = VSS to VCC

Unit

Input Leakage Current

ILI

-2

CS=VIH or OE=VIH or WE=VIL

VOUT = VSS to VCC

Output Leakage Current

ILO

-2

17ns

20ns

25ns

180

170

160

Min. Cycle, 100% Duty

CS=VIL, VIN = VIH or VIL, IOUT=0mA

Operating Current

ICC

§Ì

ISB

ISB1

VOL

Min. Cycle, CS=VIH

§Ì

Standby Current

f=0MHz, CS³ VCC-0.2V,

VIN³ VCC-0.2V or VIN£0.2V

Output Low Voltage Level

Output High Voltage Level

IOL=8mA

2.4

0.4

VOH

IOH=-4mA

IOH1=-0.1mA

VOH1*

3.95

NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.

* VCC=5.0V±5% Temp. = 25°C

CAPACITANCE*(TA=25°C, f=1.0MHz)

Item

Symbol

Test Conditions

VI/O=0V

MIN

Max

Unit

Input/Output Capacitance

Input Capacitance

CI/O

VIN=0V

CIN

* NOTE : Capacitance is sampled and not 100% tested .

- 3 -

Rev 3.0

June -1997

PRELIMINARY

KM684002, KM684002E, KM684002I

CMOS SRAM

AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)

TEST CONDITIONS

Parameter

Input Pulse Levels

Value

0V to 3V

Input Rise and Fall Times

§À

Input and Output timing Reference Levels

Output Loads

1.5V

See below

NOTE: Above test conditions are also applied at industrial temperature ranges.

Output Loads(A)

Output Loads(B)

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

+5.0V

480W

DOUT

255W

30pF*

5pF*

* Including Scope and Jig Capacitance

READ CYCLE

Parameter

KM684002-17

Min Max

KM684002-20

KM684002-25

Unit

Symbol

Min

Max

Min

Max

Read Cycle Time

tRC

tAA

tCO

tOE

tLZ

§À

Address Access Time

Chip Select to Output

Output Enable to Valid Output

Chip Enable to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

Chip Selection to Power Up Time

Chip Selection to Power DownTime

tOLZ

tHZ

tOHZ

tOH

tPU

tPD

NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.

- 4 -

Rev 3.0

June -1997

PRELIMINARY

KM684002, KM684002E, KM684002I

CMOS SRAM

WRITE CYCLE

Parameter

Write Cycle Time

KM684002-17

KM684002-20

Min Max

KM684002-25

Unit

Symbol

Min

Max

Min

Max

tWC

tCW

tAS

§À

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width(OE High)

Write Pulse Width(OE Low)

Write Recovery Time

tAW

tWP

tWP1

tWR

tWHZ

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

tDW

tDH

tOW

NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.

TIMING DIAGRAMS

TIMING WAVE FORM OF READ CYCLE(1()Address Controlled, CS=OE=VIL, WE=VIH)

tRC

ADD

tAA

tOH

Data Out

Previous Data Valid

Data Valid

- 5 -

Rev 3.0

June -1997

PRELIMINARY

KM684002, KM684002E, KM684002I

CMOS SRAM

TIMING WAVE FORM OF READ CYCLE(2()WE=VIH)

tRC

ADD

tAA

tHZ(3,4,5)

tCO

tOHZ

tOE

tOLZ

tOH

tLZ(4,5)

Data Valid

Data Out

tPU

tPD

Icc

Vcc

50%

ISB

Current

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL Levels.

4. At any given temperature and voltage condition, t HZ(Max.) is less than tLZ (Min.) both for a given device and from device to device.

§Æ

5. Transition is measured ±200

from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.

TIMING WAVE FORM OF WRITE CYCLE(1()OE=Clock)

tWC

ADD

tWR(5)

tAW

tCW(3)

tAS(4)

tWP(2)

tDW

tDH

High-Z

Data Valid

Data In

tOHZ(6)

High-Z(8)

Data Out

- 6 -

Rev 3.0

June -1997

PRELIMINARY

KM684002, KM684002E, KM684002I

CMOS SRAM

TIMING WAVE FORM OF WRITE CYCLE(2()OE=Low Fixed)

tWC

ADD

tAW

tWR(5)

tCW(3)

tOH

tAS(4)

tWP1(2)

tDW

tDH

High-Z

Data Valid

Data In

tWHZ(6)

(10)

(9)

tOW

High-Z(8)

Data Out

TIMING WAVE FORM OF WRITE CYCLE(3()CS=Controlled)

tWC

ADD

tAW

tWR(5)

tCW(3)

tAS(4)

tWP(2)

tDW

tDH

High-Z

Data In

Data Valid

tWHZ(6)

tLZ

High-Z

High-Z(8)

Data Out

- 7 -

Rev 3.0

June -1997

PRELIMINARY

KM684002, KM684002E, KM684002I

CMOS SRAM

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the ear-

liest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.

3. tCW is measured from the later of CS going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output mus t not

be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.

FUNCTIONAL DESCRIPTION

Mode

Not Select

Output Disable

Read

I/O Pin

High-Z

DOUT

Supply Current

ISB, ISB1

ICC

Write

DIN

ICC

* NOTE : X means Don't Care.

- 8 -

Rev 3.0

June -1997

PRELIMINARY

KM684002, KM684002E, KM684002I

CMOS SRAM

PACKAGE DIMENSIONS

Units : Inches (millimeters)

36-SOJ-400

#36

#19

11.18±0.12

0.440±0.005

9.40±0.25

0.370±0.010

+0.10

-0.05

0.20

+0.004

-0.002

0.008

#18

0.69

MIN

0.027

23.90

MAX

1.19

0.047

(

)

0.941

23.50±0.12

0.925±0.005

3.76

0.148

MAX

0.10

0.004

MAX

+0.10

-0.05

0.43

+0.004

-0.002

+0.10

-0.05

+0.004

-0.002

1.27

0.050

0.017

0.71

(

)

0.95

0.0375

1.27

0.050

(

)

0.028

- 9 -

Rev 3.0

June -1997

KM684002-25 [SAMSUNG]

相关型号：

KM684002A-15

KM684002A-20

KM684002AE-17

KM684002AE-20

KM684002AI-15

KM684002AI-20

KM684002AJ-15000

KM684002AJ-17000

KM684002AJ-20000

KM684002AJE-1500

KM684002AJE-1700

KM684002AJE-20