KM684002CJE-2000 [SAMSUNG]
Standard SRAM, 512KX8, 20ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36;型号: | KM684002CJE-2000 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 512KX8, 20ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36 静态存储器 光电二极管 |
文件: | 总9页 (文件大小:183K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
CMOS SRAM
KM684002C, KM684002CE, KM684002CI
Document Title
512Kx8 Bit High Speed Static RAM(5V Operating).
Operated at Extended and Industrial Temperature Ranges.
Revision History
RevNo.
Rev. 0.0
Rev. 1.0
History
Draft Data
Remark
Initial release with Preliminary.
Feb. 12. 1999
Mar. 29. 1999
Preliminary
Preliminary
1.1 Removed Low power Version.
1.2 Removed Data Retention Characteristics.
1.3 Changed ISB1 to 20mA
Rev. 2.0
2.1 Relax D.C parameters.
Aug. 19. 1999
Preliminary
Item
Previous
Current
195mA
190mA
185mA
12ns
15ns
20ns
170mA
165mA
160mA
ICC
2.2 Relax Absolute Maximum Rating.
Item
Previous
Current
Voltage on Any Pin Relative to Vss
-0.5 to 7.0
-0.5 to Vcc+0.5
3.1 Delete Preliminary
Rev. 3.0
Mar. 27. 2000
Final
3.2 Update D.C parameters and 10ns part.
Previous
Current
ICC
-
195mA
190mA
185mA
Isb
Isb1
ICC
Isb
Isb1
10ns
12ns
15ns
20ns
170mA
160mA
150mA
140mA
70mA
20mA
60mA
10mA
3.3 Added Extended temperature range
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev 3.0
March 2000
- 1 -
PRELIMINARY
CMOS SRAM
KM684002C, KM684002CE, KM684002CI
512K x 8 Bit High-Speed CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
The KM684002C is a 4,194,304-bit high-speed Static Random
Access Memory organized as 524,288 words by 8 bits. The
KM684002C uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG¢s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM684002C is packaged
in a 400 mil 36-pin plastic SOJ and 44-pin plastic TSOP type II.
Standby (TTL)
: 60mA(Max.)
(CMOS) : 10mA(Max.)
Operating KM684002C-10 : 170mA(Max.)
KM684002C-12 : 160mA(Max.)
KM684002C-15 : 150mA(Max.)
KM684002C-20 : 140mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM684002CJ : 36-SOJ-400
KM684002CT: 44-TSOP2-400BF
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
KM684002C-10/12/15/20
KM684002C-10/12/15/20
KM684002C-10/12/15/20
Commercial Temp.
Extended Temp.
Industrial Temp.
Clk Gen.
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Memory Array
1024 Rows
512 x 8 Columns
Data
Cont.
I/O Circuit
Column Select
I/O1~I/O8
CLK
Gen.
A10 A11 A12 A13 A14 A15 A16 A17 A18
CS
WE
OE
Rev 3.0
March 2000
- 2 -
PRELIMINARY
CMOS SRAM
KM684002C, KM684002CE, KM684002CI
PIN CONFIGURATION (Top View)
N.C
N.C
A0
1
2
3
4
5
6
7
8
9
44 N.C
43 N.C
42 N.C
41 A18
40 A17
39 A16
38 A15
37 OE
36 I/O8
35 I/O7
34 Vss
33 Vcc
32 I/O6
31 I/O5
30 A14
29 A13
28 A12
27 A11
26 A10
25 N.C
24 N.C
23 N.C
A0
A1
1
2
3
4
5
6
7
8
9
36 N.C
35 A18
34 A17
33 A16
32 A15
31 OE
30 I/O8
29 I/O7
28 Vss
27 Vcc
26 I/O6
25 I/O5
24 A14
23 A13
22 A12
21 A11
20 A10
19 N.C
A2
A1
A3
A2
A4
A3
A4
CS
I/O1
I/O2
Vcc
CS
I/O1
I/O2 10
Vcc 11
Vss 12
I/O3 13
I/O4 14
WE 15
A5 16
A6 17
A7 18
A8 19
A9 20
N.C 21
N.C 22
36-SOJ
44-TSOP2
Vss 10
I/O3 11
I/O4 12
WE 13
A5 14
A6 15
A7 16
A8 17
A9 18
PIN FUNCTION
Pin Name
A0 - A18
WE
Pin Function
Address Inputs
Write Enable
Chip Select
CS
OE
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
I/O1 ~ I/O8
VCC
VSS
N.C
No Connection
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
VIN, VOUT
VCC
Rating
-0.5 to VCC+0.5
-0.5 to 7.0
1.0
Unit
V
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
V
PD
W
Storage Temperature
TSTG
TA
-65 to 150
0 to 70
°C
°C
°C
°C
Operating Temperature
Commercial
Extended
Industrial
TA
-25 to 85
-40 to 85
TA
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Rev 3.0
March 2000
- 3 -
PRELIMINARY
CMOS SRAM
KM684002C, KM684002CE, KM684002CI
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Parameter
Min
Symbol
VCC
VSS
Typ
Max
Unit
V
Supply Voltage
4.5
5.0
5.5
Ground
0
0
-
0
V
Input High Voltage
Input Low Voltage
VIH
2.2
VCC+0.5***
0.8
V
VIL
-0.5**
-
V
*
The above parameters are also guaranteed at extended and industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width £ 8ns) for I £ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 8ns) for I £ 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Min
Max
Parameter
Symbol
ILI
Test Conditions
Unit
mA
Input Leakage Current
Output Leakage Current
VIN=VSS to VCC
-2
2
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
2
mA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL, IOUT=0mA
Com.
10ns
12ns
15ns
20ns
10ns
12ns
15ns
20ns
-
-
-
-
-
-
-
-
-
-
170
160
150
140
185
175
165
155
60
mA
Ext.
Ind.
Standby Current
ISB
Min. Cycle, CS=VIH
mA
mA
ISB1
f=0MHz, CS³ VCC-0.2V,
10
VIN³ VCC-0.2V or VIN£0.2V
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
-
2.4
-
0.4
-
V
V
V
IOH=-4mA
IOH1=-0.1mA
VOH1**
3.95
* The above parameters are also guaranteed at extended and industrial temperature range.
** VCC=5.0V±5%, Temp.=25°C.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
Test Conditions
VI/O=0V
MIN
Max
8
Unit
pF
CI/O
-
-
VIN=0V
CIN
7
pF
* Capacitance is sampled and not 100% tested.
Rev 3.0
March 2000
- 4 -
PRELIMINARY
CMOS SRAM
KM684002C, KM684002CE, KM684002CI
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
Input Pulse Levels
0V to 3V
3ns
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
* The above test conditions are also applied at extended and industrial temperature range.
Output Loads(A)
DOUT
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V
RL = 50W
VL = 1.5V
30pF*
480W
DOUT
ZO = 50W
255W
5pF*
* Including Scope and Jig Capacitance
* Capacitive Load consists of all components of the
test environment.
READ CYCLE*
KM684002C-10
KM684002C-12
KM684002C-15
KM684002C-20
Parameter
Symbol
Unit
Min
10
-
Max
Min
12
-
Max
Min
15
-
Max
Min
20
-
Max
Read Cycle Time
tRC
tAA
tCO
tOE
tLZ
-
10
10
5
-
12
12
6
-
15
15
7
-
20
20
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
-
-
-
-
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address
Chip Selection to Power Up Time
Chip Selection to Power Down-
-
-
-
-
3
-
3
-
3
-
3
-
tOLZ
tHZ
tOHZ
tOH
tPU
0
-
0
-
0
-
0
-
0
5
0
6
0
7
0
9
0
5
0
6
0
7
0
9
3
-
3
-
3
-
3
-
0
-
0
-
0
-
0
-
tPD
-
10
-
12
-
15
-
20
* The above parameters are also guaranteed at extended and industrial temperature range.
Rev 3.0
March 2000
- 5 -
PRELIMINARY
CMOS SRAM
KM684002C, KM684002CE, KM684002CI
WRITE CYCLE*
KM684002C-10
KM684002C-12
KM684002C-15
KM684002C-20
Parameter
Symbol
Unit
Min
10
7
Max
Min
12
8
Max
Min
15
10
0
Max
Min
20
12
0
Max
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
7
-
-
-
-
-
-
-
-
-
-
9
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set-up Time
0
0
Address Valid to End of
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
7
8
10
10
15
0
12
12
20
0
7
8
10
0
12
0
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
0
0
0
0
5
6
7
9
0
0
0
0
tOW
3
3
3
3
* The above parameters are also guaranteed at extended and industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Valid Data
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tHZ(3,4,5)
tCO
CS
tOE
tOHZ
tOH
OE
tOLZ
tLZ(4,5)
Data out
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
NOTES(WRITE CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
Rev 3.0
March 2000
- 6 -
PRELIMINARY
CMOS SRAM
KM684002C, KM684002CE, KM684002CI
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
tWR(5)
tAW
OE
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
tDH
High-Z
Data in
Data out
Valid Data
tOHZ(6)
High-Z(8)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tWR(5)
tAW
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDH
tDW
High-Z
Data in
Valid Data
tWHZ(6)
tOW
(10)
(9)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
tWP(2)
CS
tAS(4)
WE
tDH
tDW
High-Z
High-Z
High-Z
Data in
Data out
Valid Data
tLZ
tWHZ(6)
High-Z(8)
Rev 3.0
March 2000
- 7 -
PRELIMINARY
CMOS SRAM
KM684002C, KM684002CE, KM684002CI
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write
ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the
output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS
WE
X
OE
X*
H
Mode
Not Select
Output Disable
Read
I/O Pin
High-Z
High-Z
DOUT
Supply Current
H
ISB, ISB1
ICC
L
H
L
H
L
ICC
L
L
X
Write
DIN
ICC
* X means Don¢t Care.
Rev 3.0
March 2000
- 8 -
PRELIMINARY
CMOS SRAM
KM684002C, KM684002CE, KM684002CI
Units:millimeters/Inches
PACKAGE DIMENSIONS
36-SOJ-400
#36
#19
9.40 ±0.25
0.370 ±0.010
11.18 ±0.12
0.440 ±0.005
+0.10
-0.05
0.20
+0.004
-0.002
#1
#18
0.008
0.69
MIN
0.027
23.90
MAX
0.941
23.50 ±0.12
0.925 ±0.005
1.19
0.047
1.27
(
(
)
)
3.76
0.148
0.10
0.004
MAX
MAX
0.050
+0.10
-0.05
0.43
+0.10
+0.004
-0.002
0.71
0.028
-0.05
0.017
0.95
0.0375
1.27
0.050
(
)
+0.004
-0.002
44-TSOP2-400BF
Units:millimeters/Inches
0~8°
0.25
0.010
TYP
#23
#44
0.45 ~0.75
0.018 ~ 0.030
11.76 ±0.20
0.463 ±0.008
0.50
0.020
(
)
#1
#22
18.81
0.741
MAX
+ 0.075
- 0.035
+ 0.003
- 0.001
0.125
0.005
18.41 ±0.10
0.725 ±0.004
1.00 ±0.10
0.039 ±0.004
1.20
0.047
MAX
0.10
0.004
MAX
+0.10
- 0.05
+0.004
- 0.002
0.05
0.002
0.30
MIN
0.80
0.0315
0.805
0.032
(
)
0.012
Rev 3.0
March 2000
- 9 -
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