KM68FS8100FI-7 [SAMSUNG]

Standard SRAM, 1MX8, 70ns, CMOS, PBGA48, 8 X 12 MM, 0.75 MM PITCH, FBGA-48;


型号：	KM68FS8100FI-7
厂家：	SAMSUNG
描述：	Standard SRAM, 1MX8, 70ns, CMOS, PBGA48, 8 X 12 MM, 0.75 MM PITCH, FBGA-48 静态存储器内存集成电路
文件：	总9页 (文件大小：153K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Preliminary

KM68FS8100 Family

CMOS SRAM

Document Title

1M x8 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No. History

Draft Date

August 25, 1999

Remark

0.0

Initial draft

Preliminary

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 0.0

August 1999

Preliminary

KM68FS8100 Family

CMOS SRAM

1M x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology: Full CMOS

· Organization: 1M x8

The KM68FS8100 families are fabricated by SAMSUNG¢s

advanced full CMOS process technology. The families support

industrial operating temperature ranges and have chip scale

package for user flexibility of system design. The families also

support low data retention voltage for battery back-up operation

with low data retention current.

· Power Supply Voltage: 2.3~2.7V

· Low Data Retention Voltage: 1.5V(Min)

· Three state output and TTL Compatible

· Package Type: 48-FBGA-8.00x12.00

PRODUCT FAMILY

Power Dissipation

Product Family

Operating Temperature Vcc Range

Speed

PKG Type

Standby

(ISB1, Typ.)

Operating

(ICC1, Max)

KM68FS8100I

Industrial(-40~85°C)

2.3~2.7V

70*/85ns

0.5mA

3mA

48-FBGA-8.00x12.00

1. The parameter is measured with 30pF test load.

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

Clk gen.

Precharge circuit.

DNU

I/O2

I/O3

DNU

CS2

DNU

I/O5

Vcc

Vss

CS1

DNU

I/O6

I/O7

DNU

Row

Addresses

Memory array

2048 rows

256´ 8 columns

Row

select

I/O1

Vss

A17

VCC

A14

A12

I/O Circuit

Column select

Data

cont

Vcc

I/O4

DNU

A18

A16

A15

A13

A10

Vss

I/O1~I/O8

I/O8

DNU

A19

Data

cont

Column Addresses

A11

CS1

CS2

48-FBGA: Top View (Ball Down)

Control Logic

Name

Function

Name

Function

CS1, CS2 Chip Select Inputs

A0~A19 Address Inputs

Output Enable Input

Write Enable Input

Vcc

Vss

Power

Ground

I/O1~I/O16 Data Inputs/Outputs

DNU Do Not Use

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 0.0

August 1999

Preliminary

KM68FS8100 Family

CMOS SRAM

PRODUCT LIST

Industrial Temperature Products(-40~85°C)

Part Name

Function

KM68FS8100FI-7

KM68FS8100FI-8

48-FBGA, 70ns, 2.5V

48-FBGA, 85ns, 2.5V

FUNCTIONAL DESCRIPTION

CS1

CS2

X¹⁾

I/O1~8

High-Z

Dout

Mode

Deselected

Output Disabled

Read

Power

Standby

Active

X¹⁾

Active

X¹⁾

Din

Write

Active

1. X means don¢t care. (Must be low or high state)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

Symbol

Ratings

-0.2 to 3.0

-0.2 to 3.6

1.0

Unit

VIN,VOUT

VCC

Storage temperature

TSTG

-55 to 150

-40 to 85

°C

Operating Temperature

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 0.0

August 1999

Preliminary

KM68FS8100 Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

Vcc

Min

2.3

Typ

Max

Unit

Supply voltage

Ground

2.5

2.7

Vss

Vcc+0.2²⁾

0.4

Input high voltage

Input low voltage

Note:

VIH

2.2

-0.2³⁾

VIL

1. TA=-40 to 85°C, otherwise specified

2. Overshoot: VCC+1.0V in case of pulse width £20ns.

3. Undershoot: -1.0V in case of pulse width £20ns.

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Test Conditions

Min

-1

Typ

Max

Unit

Input leakage current

VIN=Vss to Vcc

Output leakage current

Operating power supply current

ILO

CS1=VIH, CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS1=VIL, CS2=VIH, WE=VIH, VIN=VIH or VIL

ICC

Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V,

CS2³ Vcc-0.2V, VIN£0.2V or VIN³ VCC-0.2V

ICC1

ICC2

Average operating current

Cycle time=Min, IIO=0mA, 100% duty,

CS1=VIL, CS2=VIH, VIN=VIL or VIH

Output low voltage

Output high voltage

Standby Current(TTL)

VOL

VOH

ISB

IOL = 2.1mA

0.4

IOH = -1.0mA

2.2

CS1=VIH, CS2=VIL, Other inputs=VIH or VIL

0.3

CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or

CS2£0.2V(CS2 controlled), Other inputs=0~Vcc

20¹⁾

Standby Current(CMOS)

ISB1

0.5

1. Super low power product=10mA with special handling.

Revision 0.0

August 1999

Preliminary

KM68FS8100 Family

CMOS SRAM

VTM

AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Input/Output Reference)

Input pulse level: 0.2 to 2.2V

Input rising and falling time: 5ns

Input and output reference voltage:1.1V

Output load(see right): CL=100pF+1TTL

CL=30pF+1TTL

1. Including scope and jig capacitance

2. R1=3070W, R2=3150W

3. VTM =2.3V

AC CHARACTERISTICS (Vcc=2.3~2.7V, TA=-40 to 85°C)

Speed Bins

Parameter List

Symbol

Units

70ns

85ns

Min

Max

Min

Max

Read cycle time

tRC

tAA

Address access time

Chip select to output

tCO1, tCO2

tOE

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

OE disable to high-Z output

Output hold from address change

Write cycle time

Read

tLZ1, tLZ2

tOLZ

tHZ1, tHZ2

tOHZ

tOH

tWC

Chip select to end of write

Address set-up time

tCW1, tCW2

tAS

Address valid to end of write

Write pulse width

tAW

tWP

Write

Write recovery time

tWR

Write to output high-Z

tWHZ

tDW

Data to write time overlap

Data hold from write time

End write to output low-Z

tDH

tOW

DATA RETENTION CHARACTERISTICS

Item

Symbol

Test Condition

CS1³ Vcc-0.2V¹⁾

Min

1.5

Typ

Max

Unit

Vcc for data retention

Data retention current

Data retention set-up time

Recovery time

VDR

0.5

2.7

6²⁾

Vcc=1.5V, CS1³ Vcc-0.2V¹⁾

IDR

tSDR

See data retention waveform

tRDR

tRC

1. CS1³ Vcc-0.2V,CS2³ Vcc-0.2V(CS1 controlled) or CS2³ Vcc-0.2V(CS2 controlled).

2. Super low power product=4mA with special handling.

Revision 0.0

August 1999

Preliminary

KM68FS8100 Family

CMOS SRAM

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO1

CS1

tHZ(1,2)

CS2

tCO2

tOE

tOHZ

tOLZ

tLZ

High-Z

Data out

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 0.0

August 1999

Preliminary

KM68FS8100 Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tCW(2)

tWR(4)

CS1

tAW

CS2

tCW(2)

tWP(1)

tAS(3)

tDW

tDH

Data Valid

Data in

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS¹Controlled)

tWC

Address

CS1

tCW(2)

tAS(3)

tWR(4)

tAW

CS2

tWP(1)

tDW

tDH

Data in

Data out

Data Valid

High-Z

Revision 0.0

August 1999

Preliminary

KM68FS8100 Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

tWC

Address

CS1

tAS(3)

tCW(2)

tWR(4)

tAW

CS2

tCW(2)

tWP(1)

tDH

tDW

Data in

Data Valid

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,

CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,

tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS¹going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied

in case a write ends as CS2 going to low.

DATA RETENTION WAVE FORM

CS1 controlled

Data Retention Mode

tSDR

tRDR

VCC

2.3V

2.0V

VDR

CS1³ VCC - 0.2V

CS1

GND

CS2 controlled

Data Retention Mode

VCC

2.3V

CS2

tSDR

tRDR

VDR

CS2£0.2V

0.4V

GND

Revision 0.0

August 1999

Preliminary

KM68FS8100 Family

CMOS SRAM

Unit: millimeters

PACKAGE DIMENSION

48 BALL FINE PITCH BGA(0.75mm ball pitch)

Top View

Bottom View

A1 INDEX MARK

0.50

#A1

B/2

Detail A

Side View

Min

Typ

0.75

8.00

3.75

12.00

5.25

0.35

1.10

0.85

0.25

Max

Notes.

7.90

8.10

1. Bump counts: 48(8row x 6column)

2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are +/-0.050 unless

otherwise specified.

11.90

12.10

4. Typ : Typical

0.30

0.40

1.20

5. Y is coplanarity: 0.08(Max)

0.20

0.30

0.08

Revision 0.0

August 1999

KM68FS8100FI-7 [SAMSUNG]

相关型号：

KM68FS8100FI-8

KM68FU1000AFI-7

KM68FU1000ATGI-10

KM68FU1000ATGI-7

KM68FU1000G-8

KM68FU1000GI-7

KM68FU1000GI7H

KM68FU1000GI8H

KM68FU1000R7H

KM68FU1000R8H

KM68FU1000RI-7

KM68FU1000RI7H