KM68U1000BLR-100 [SAMSUNG]
Standard SRAM, 128KX8, 100ns, CMOS, PDSO32, 8 X 20 MM, REVERSE, TSOP1-32;型号: | KM68U1000BLR-100 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 128KX8, 100ns, CMOS, PDSO32, 8 X 20 MM, REVERSE, TSOP1-32 静态存储器 光电二极管 内存集成电路 |
文件: | 总10页 (文件大小:183K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
KM68V1000B, KM68U1000B Family
CMOS SRAM
Document Title
128K x8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
1.0
2.0
Initial draft
August 12, 1995 Preliminary
Finalize
April 12, 1996
March 7, 1998
Final
Final
Revise
- Change datasheet format
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family
CMOS SRAM
128K x8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology : Poly Load
· Organization : 128Kx8
The KM68V1000B and KM68U1000B families are fabricated
by SAMSUNG¢s advanced CMOS process technology. The
families support various operating temperature ranges and
have various package types for user flexibility of system
design. The families also support low data retention voltage for
battery back-up operation with low data retention current.
· Power Supply Voltage :
KM68V1000B family : 3.0~3.6V
KM68U1000B family : 2.7~3.3V
· Low Data Retention Voltage : 2V(Min)
· Three state output and TTL Compatible
· Package Type : 32-SOP, 32-TSOP1-0820F/R
PRODUCT FAMILY
Power Dissipation
PKG Type
Product Family
Operating Temperature Vcc Range Speed(ns)
Standby
Operating
(ICC2, Max)
(ISB1, Max)
701)/100
100
701)/100
KM68V1000BL/L-L
KM68U1000BL/L-L
KM68V1000BLE/LE-L
KM68U1000BLE/LE-L
KM68V1000BLI/LI-L
KM68U1000BLI/LI-L
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
50/15mA
50/15mA
Commercial(0~70°C)
Extended(-25~85°C)
Industrial(-40~85°C)
32-SOP
32-TSOP1- R/F
100/20mA
50/15mA
40mA
100
701)/100
100
100/20mA
50/15mA
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
Clk gen.
Precharge circuit.
VCC
A15
CS2
N.C
A16
A14
A12
A7
1
32
A4
32-TSOP
2
31
A5
9
3
30
A6
A16
WE A14
Type 1 - Forward
10
11
12
13
14
15
16
4
29
A7
Memory array
512 rows
256´ 8 columns
A12
28
A13
A7
5
Row
select
A12
A13
A14
A15
A16
A6
A5
A9
A4
A1
A2
A3
27
A8
A6
6
26
A5
7
32-SOP 25
A11
A4
8
24
23
22
21
20
19
18
17
OE
A4
A3
9
16
15
14
13
12
11
10
9
8
7
6
5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
A10 A5
A6
A2
10
11
12
13
14
15
16
CS1
A7
A1
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS1
A10
OE
A12
I/O8
A0
A14
I/O Circuit
I/O1
I/O8
Data
cont
I/O7
A16
I/O1
I/O2
I/O3
VSS
32-TSOP
NC
A15
VCC
CS2
A13
WE
A8
Column select
I/O6
Type 1 - Reverse
I/O5
I/O4
Data
cont
4
3
2
1
A9
A11
A0 A1 A2 A3 A8 A9 A10 A11
Name
CS1,CS2
OE
Function
Chip Select Inputs
Output Enable Input
Write Enable Input
Address Inputs
Data Inputs/Outputs
Power
CS1
CS2
WE
Control
Logic
WE
OE
A0~A16
I/O1~I/O8
Vcc
Vss
Ground
N.C
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family
CMOS SRAM
PRODUCT LIST
Commercial Temperarure Products
Extended Temperarure Products
(-25~85°C)
Industrial Temperarure Products
(0~70°C)
(-40~85°C)
Part Name
Function
Part Name
Function
Part Name
Function
KM68V1000BLG-7
KM68V1000BLG-10
KM68V1000BLT-7
KM68V1000BLT-10
KM68V1000BLR-7
KM68V1000BLR-10
32-SOP,70ns,3.3V,L
KM68V1000BLGE-7
KM68V1000BLGE-10
KM68V1000BLTE-7
KM68V1000BLTE-10
KM68V1000BLRE-7
KM68V1000BLRE-10
32-SOP,70ns,3.3V,L
KM68V1000BLGI-7
KM68V1000BLGI-10
KM68V1000BLTI-7
KM68V1000BLTI-10
KM68V1000BLRI-7
KM68V1000BLRI-10
32-SOP,70ns,3.3V,L
32-SOP,100ns,3.3V,L
32-TSOP F,70ns,3.3V,L
32-TSOP F,100ns,3.3V,L
32-TSOP R,70ns,3.3V,L
32-TSOP R,100ns,3.3V,L
32-SOP,100ns,3.3V,L
32-TSOP F,70ns,3.3V,L
32-TSOP F,100ns,3.3V,L
32-TSOP R,70ns,3.3V,L
32-TSOP R,100ns,3.3V,L
32-SOP,100ns,3.3V,L
32-TSOP F,70ns,3.3V,L
32-TSOP F,100ns,3.3V,L
32-TSOP R,70ns,3.3V,L
32-TSOP R,100ns,3.3V,L
KM68V1000BLG-7L
KM68V1000BLG-10L 32-SOP,100ns,3.3V,LL
KM68V1000BLT-7L
KM68V1000BLT-10L
KM68V1000BLR-7L
32-SOP,70ns,3.3V,LL
KM68V1000BLGE-7L
KM68V1000BLGE-10L 32-SOP,100ns,3.3V,LL
KM68V1000BLTE-7L
32-SOP,70ns,3.3V,LL
KM68V1000BLGI-7L
KM68V1000BLGI-10L
KM68V1000BLTI-7L
KM68V1000BLTI-10L
KM68V1000BLRI-7L
32-SOP,70ns,3.3V,LL
32-SOP,100ns,3.3V,LL
32-TSOP F,70ns,3.3V,LL
32-TSOP F,100ns,3.3V,LL
32-TSOP R,70ns,3.3V,LL
32-TSOP R,100ns,3.3V,LL
32-TSOP F,70ns,3.3V,LL
32-TSOP F,100ns,3.3V,LL KM68V1000BLTE-10L
32-TSOP R,70ns,3.3V,LL KM68V1000BLRE-7L
32-TSOP F,70ns,3.3V,LL
32-TSOP F,100ns,3.3V,LL
32-TSOP R,70ns,3.3V,LL
KM68V1000BLR-10L 32-TSOP R,100ns,3.3V,LL KM68V1000BLRE-10L 32-TSOP R,100ns,3.3V,LL KM68V1000BLRI-10L
KM68U1000BLG-10
KM68U1000BLT-10
KM68U1000BLR-10
32-SOP,100ns,3.0V,L
32-TSOP F,100ns,3.0V,L
32-TSOP R,100ns,3.0V,L
KM68U1000BLGE-10
KM68U1000BLTE-10
KM68U1000BLRE-10
32-SOP,100ns,3.0V,L
32-TSOP F,100ns,3.0V,L
32-TSOP R,100ns,3.0V,L
KM68U1000BLGI-10
KM68U1000BLTI-10
KM68U1000BLRI-10
32-SOP,100ns,3.0V,L
32-TSOP F,100ns,3.0V,L
32-TSOP R,100ns,3.0V,L
KM68U1000BLG-10L 32-SOP,100ns,3.0V,LL
KM68U1000BLT-10L
KM68U1000BLR-10L 32-TSOP R,100ns,3.0V,LL KM68U1000BLRE-10L 32-TSOP R,100ns,3.0V,LL KM68U1000BLRI-10L
KM68U1000BLGE-10L 32-SOP,100ns,3.0V,LL
32-TSOP F,100ns,3.0V,LL
KM68U1000BLGI-10L
KM68U1000BLTI-10L
32-SOP,100ns,3.0V,LL
32-TSOP F,100ns,3.0V,LL
32-TSOP R,100ns,3.0V,LL
32-TSOP F,100ns,3.0V,LL KM68U1000BLTE-10L
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O Pin
High-Z
High-Z
High-Z
Dout
Mode
Deselected
Deselected
Output Disabled
Read
Power
Standby
Standby
Active
X1)
L
X1)
X1)
H
X1)
L
X1)
H
X1)
H
H
H
H
L
L
L
H
L
Active
X1)
Din
Write
Active
1. X means don¢t care(Must be in high or low status.)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
VIN,VOU
VCC
Ratings
-0.5 to VCC+0.5
-0.3 to 4.6
Unit
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
V
V
-
-
PD
0.7
W
°C
°C
°C
°C
-
-
Storage temperature
TSTG
-65 to 150
-
0 to 70
KM68V1000BL, KM68U1000BL
KM68V1000BLE, KM68U1000BLE
KM68V1000BLI, KM68U1000BLI
-
Operating Temperature
TA
-25 to 85
-40 to 85
Soldering temperature and time
TSOLDER
260°C, 10sec (Lead Only)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Product
Min
Max
Unit
Typ
KM68V1000B Family
KM68U1000B Family
3.0
2.7
3.3
3.0
3.6
3.3
Supply voltage
Vcc
V
Ground
Vss
VIH
VIL
All Family
0
0
-
0
V
V
V
Vcc+0.32)
0.4
Input high voltage
Input low voltage
KM68V1000B, KM68U1000B Family
KM68V1000B, KM68U1000B Family
2.2
-0.33)
-
Note:
1. Commercial Product : TA=0 to 70°C, unless otherwise specified
Extended Product : TA=-25 to 85°C, unless otherwise specified
Industrial Product : TA=-40 to 85°C, unless otherwise specified
2. Overshoot : VCC+3.0V in case of pulse width£30ns
3. Undershoot : -3.0V in case of pulse width£30ns
4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Symbol
CIN
Test Condition
VIN=0V
Min
Max
Unit
Input capacitance
-
-
6
8
pF
pF
Input/Output capacitance
CIO
VIO=0V
1. Capacitance is sampled not, 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min
-1
-1
-
Typ
Max Unit
Input leakage current
VIN=Vss to Vcc
-
-
1
1
5
mA
mA
mA
Output leakage current
Operating power supply current
ILO
CS1=VIH or CS2=VIL or WE=VIL, Vio=Vss to Vcc
CS1=VIL,CS2=VIH,VIN=VIH or VIL, IIO=0mA
ICC
2
Cycle time=1ms, 100% duty, IIO=0mA, CS1£0.2V,
CS2³ VCC-0.2V, VIN£0.2V or VIN³ VCC-0.2V
ICC1
-
3
5
mA
Average operating current
ICC2
VOL
VOH
ISB
Min cycle, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH
-
-
30
-
40
0.4
-
mA
V
Output low voltage
Output high voltage
Standby Current(TTL)
IOL=2.1mA
IOH=-1.0mA
2.2
-
-
V
CS1=VIH, CS2=VIL
-
0.3
mA
Low Power
Low Low Power
-
-
1.0
0.5
50
15
KM68V1000BL/L-L
mA
mA
mA
mA
Low Power
Low Low Power
-
-
KM68V1000BLE/LE-L
KM68V1000BLI/LI-L
1.0
0.5
100
20
Standby
Current
(CMOS)
CS1³ Vcc-0.2V
CS2³ Vcc-0.2V or CS2£0.2V
Other input =0~Vcc
ISB1
Low Power
Low Low Power
-
-
1.0
0.5
50
15
KM68U1000BL/L-L
Low Power
Low Low Power
-
-
50
15
KM68U1000BLE/LE-L
KM68U1000BLI/LI-L
1.0
0.5
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
1)
Input rising and falling time : 5ns
CL
Input and output reference voltage :1.5V
Output load(see right) : CL=100pF+1TTL
CL=30pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS (Commercial product :TA=0 to 70°C, Extended product :TA=-25 to 85°C, Industrial product : TA=-40 to 85°C
KM68V1000B Family:Vcc=3.0~3.6V, KM68U1000B Family:Vcc=2.7~3.3V)
Speed Bins
Parameter List
Symbol
Units
70ns
100ns
Min
70
-
Max
Min
100
-
Max
Read cycle time
tRC
tAA
-
70
70
35
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
100
Chip select to output
tCO
tOE
tLZ
-
-
100
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
-
-
50
-
Read
10
5
10
5
tOLZ
tHZ
-
-
0
25
25
-
0
30
30
-
tOHZ
tOH
tWC
tCW
tAS
0
0
10
70
60
0
15
100
80
0
-
-
Chip select to end of write
Address set-up time
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
60
55
0
-
80
70
0
-
-
-
Write
Write recovery time
-
-
Write to output high-Z
0
25
-
0
30
-
Data to write time overlap
Data hold from write time
End write to output low-Z
30
0
40
0
-
-
5
-
5
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
Min
Typ
Max
Unit
Test Condition
1)
Vcc for data retention
VDR
2.0
-
3.6
V
CS1 ³ Vcc-0.2V
Low Power
Low Low Power
-
-
1
0.5
30
15
KM68V1000BL/L-L
KM68V1000BLE/LE-L
KM68V1000BLI/LI-L
Low Power
Low Low Power
-
-
-
-
50
20
Vcc=3.0V
CS1³ Vcc-0.2V
CS2³ Vcc-0.2V
or CS2£0.2V
Data retention current
IDR
mA
Low Power
Low Low Power
-
-
-
-
25
10
KM68U1000BL/L-L
KM68U1000BLE/LE-L
KM68U1000BLI/LI-L
Low Power
Low Low Power
-
-
-
-
25
15
Data retention set-up time
Recovery time
tSDR
tRDR
0
5
-
-
-
-
See data retention waveform
ms
1. CS³ VCC-0.2V, CS2³ VCC-0.2V(CS1 controlled) or CS2£0.2V(CS2 controlled)
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VlL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
Data out
tWHZ
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
CS1
tCW(2)
tAS(3)
tWR(4)
tAW
CS2
tWP(1)
WE
tDW
tDH
Data in
Data out
Data Valid
High-Z
High-Z
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 Controlled)
tWC
Address
CS1
tAS(3)
tCW(2)
tWR(4)
tAW
CS2
tCW(2)
tWP(1)
WE
tDH
tDW
Data Valid
Data in
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)
applied in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0/2.7V1)
2.2V
VDR
CS1³ VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
3.0/2.7V1)
CS2
tSDR
tRDR
VDR
CS2£0.2V
0.4V
GND
1. 3.0V for KM68V1000B Family , 2.7V for KM68U1000B Family
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family
CMOS SRAM
Units : millimeter(inch)
PACKAGE DIMENSIONS
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#32
#17
14.12±0.30
0.556±0.012
11.43±0.20
0.450±0.008
#1
#16
0.80±0.20
0.031±0.008
+0.10
0.20
-0.05
2.74±0.20
20.87
0.822
MAX
0.108±0.008
+0.004
-0.002
0.008
3.00
0.118
MAX
20.47±0.20
0.806±0.008
0.10 MAX
0.004 MAX
+0.100
-0.050
0.41
0.71
0.028
1.27
0.050
+0.004
-0.002
(
)
0.05
0.002
0.016
MIN
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family
CMOS SRAM
Units : millimeter(inch)
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
+0.10
-0.05
20.00±0.20
0.787±0.008
0.20
0.008+0.004
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#16
#17
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
18.40±0.10
0.724±0.004
TYP
+0.10
0.15
-0.05
0.006+0.004
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820R)
+0.10
-0.05
20.00±0.20
0.787±0.008
0.20
+0.004
-0.002
0.008
#16
#17
0.25
0.010
(
)
0.50
0.0197
#1
#32
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
18.40±0.10
0.724±0.004
0.25
0.010
TYP
+0.10
-0.05
0.15
+0.004
-0.002
0.006
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
Revision 2.0
March 1998
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
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